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d61e0bf3 JC |
1 | /* |
2 | * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved. | |
3 | * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved. | |
4 | ||
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public | |
7 | * License as published by the Free Software Foundation; | |
8 | * either version 2, or (at your option) any later version. | |
9 | ||
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even | |
12 | * the implied warranty of MERCHANTABILITY or FITNESS FOR | |
13 | * A PARTICULAR PURPOSE.See the GNU General Public License | |
14 | * for more details. | |
15 | ||
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., | |
19 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
20 | */ | |
21 | ||
22 | #ifndef __HW_H__ | |
23 | #define __HW_H__ | |
24 | ||
dd73d686 | 25 | #include "viamode.h" |
d61e0bf3 JC |
26 | #include "global.h" |
27 | ||
28 | /*************************************************** | |
29 | * Definition IGA1 Design Method of CRTC Registers * | |
30 | ****************************************************/ | |
31 | #define IGA1_HOR_TOTAL_FORMULA(x) (((x)/8)-5) | |
32 | #define IGA1_HOR_ADDR_FORMULA(x) (((x)/8)-1) | |
33 | #define IGA1_HOR_BLANK_START_FORMULA(x) (((x)/8)-1) | |
34 | #define IGA1_HOR_BLANK_END_FORMULA(x, y) (((x+y)/8)-1) | |
35 | #define IGA1_HOR_SYNC_START_FORMULA(x) ((x)/8) | |
36 | #define IGA1_HOR_SYNC_END_FORMULA(x, y) ((x+y)/8) | |
37 | ||
38 | #define IGA1_VER_TOTAL_FORMULA(x) ((x)-2) | |
39 | #define IGA1_VER_ADDR_FORMULA(x) ((x)-1) | |
40 | #define IGA1_VER_BLANK_START_FORMULA(x) ((x)-1) | |
41 | #define IGA1_VER_BLANK_END_FORMULA(x, y) ((x+y)-1) | |
42 | #define IGA1_VER_SYNC_START_FORMULA(x) ((x)-1) | |
43 | #define IGA1_VER_SYNC_END_FORMULA(x, y) ((x+y)-1) | |
44 | ||
45 | /*************************************************** | |
46 | ** Definition IGA2 Design Method of CRTC Registers * | |
47 | ****************************************************/ | |
48 | #define IGA2_HOR_TOTAL_FORMULA(x) ((x)-1) | |
49 | #define IGA2_HOR_ADDR_FORMULA(x) ((x)-1) | |
50 | #define IGA2_HOR_BLANK_START_FORMULA(x) ((x)-1) | |
51 | #define IGA2_HOR_BLANK_END_FORMULA(x, y) ((x+y)-1) | |
52 | #define IGA2_HOR_SYNC_START_FORMULA(x) ((x)-1) | |
53 | #define IGA2_HOR_SYNC_END_FORMULA(x, y) ((x+y)-1) | |
54 | ||
55 | #define IGA2_VER_TOTAL_FORMULA(x) ((x)-1) | |
56 | #define IGA2_VER_ADDR_FORMULA(x) ((x)-1) | |
57 | #define IGA2_VER_BLANK_START_FORMULA(x) ((x)-1) | |
58 | #define IGA2_VER_BLANK_END_FORMULA(x, y) ((x+y)-1) | |
59 | #define IGA2_VER_SYNC_START_FORMULA(x) ((x)-1) | |
60 | #define IGA2_VER_SYNC_END_FORMULA(x, y) ((x+y)-1) | |
61 | ||
62 | /**********************************************************/ | |
63 | /* Definition IGA2 Design Method of CRTC Shadow Registers */ | |
64 | /**********************************************************/ | |
65 | #define IGA2_HOR_TOTAL_SHADOW_FORMULA(x) ((x/8)-5) | |
66 | #define IGA2_HOR_BLANK_END_SHADOW_FORMULA(x, y) (((x+y)/8)-1) | |
67 | #define IGA2_VER_TOTAL_SHADOW_FORMULA(x) ((x)-2) | |
68 | #define IGA2_VER_ADDR_SHADOW_FORMULA(x) ((x)-1) | |
69 | #define IGA2_VER_BLANK_START_SHADOW_FORMULA(x) ((x)-1) | |
70 | #define IGA2_VER_BLANK_END_SHADOW_FORMULA(x, y) ((x+y)-1) | |
71 | #define IGA2_VER_SYNC_START_SHADOW_FORMULA(x) (x) | |
72 | #define IGA2_VER_SYNC_END_SHADOW_FORMULA(x, y) (x+y) | |
73 | ||
74 | /* Define Register Number for IGA1 CRTC Timing */ | |
75 | ||
76 | /* location: {CR00,0,7},{CR36,3,3} */ | |
77 | #define IGA1_HOR_TOTAL_REG_NUM 2 | |
78 | /* location: {CR01,0,7} */ | |
79 | #define IGA1_HOR_ADDR_REG_NUM 1 | |
80 | /* location: {CR02,0,7} */ | |
81 | #define IGA1_HOR_BLANK_START_REG_NUM 1 | |
82 | /* location: {CR03,0,4},{CR05,7,7},{CR33,5,5} */ | |
83 | #define IGA1_HOR_BLANK_END_REG_NUM 3 | |
84 | /* location: {CR04,0,7},{CR33,4,4} */ | |
85 | #define IGA1_HOR_SYNC_START_REG_NUM 2 | |
86 | /* location: {CR05,0,4} */ | |
87 | #define IGA1_HOR_SYNC_END_REG_NUM 1 | |
88 | /* location: {CR06,0,7},{CR07,0,0},{CR07,5,5},{CR35,0,0} */ | |
89 | #define IGA1_VER_TOTAL_REG_NUM 4 | |
90 | /* location: {CR12,0,7},{CR07,1,1},{CR07,6,6},{CR35,2,2} */ | |
91 | #define IGA1_VER_ADDR_REG_NUM 4 | |
92 | /* location: {CR15,0,7},{CR07,3,3},{CR09,5,5},{CR35,3,3} */ | |
93 | #define IGA1_VER_BLANK_START_REG_NUM 4 | |
94 | /* location: {CR16,0,7} */ | |
95 | #define IGA1_VER_BLANK_END_REG_NUM 1 | |
96 | /* location: {CR10,0,7},{CR07,2,2},{CR07,7,7},{CR35,1,1} */ | |
97 | #define IGA1_VER_SYNC_START_REG_NUM 4 | |
98 | /* location: {CR11,0,3} */ | |
99 | #define IGA1_VER_SYNC_END_REG_NUM 1 | |
100 | ||
101 | /* Define Register Number for IGA2 Shadow CRTC Timing */ | |
102 | ||
103 | /* location: {CR6D,0,7},{CR71,3,3} */ | |
104 | #define IGA2_SHADOW_HOR_TOTAL_REG_NUM 2 | |
105 | /* location: {CR6E,0,7} */ | |
106 | #define IGA2_SHADOW_HOR_BLANK_END_REG_NUM 1 | |
107 | /* location: {CR6F,0,7},{CR71,0,2} */ | |
108 | #define IGA2_SHADOW_VER_TOTAL_REG_NUM 2 | |
109 | /* location: {CR70,0,7},{CR71,4,6} */ | |
110 | #define IGA2_SHADOW_VER_ADDR_REG_NUM 2 | |
111 | /* location: {CR72,0,7},{CR74,4,6} */ | |
112 | #define IGA2_SHADOW_VER_BLANK_START_REG_NUM 2 | |
113 | /* location: {CR73,0,7},{CR74,0,2} */ | |
114 | #define IGA2_SHADOW_VER_BLANK_END_REG_NUM 2 | |
115 | /* location: {CR75,0,7},{CR76,4,6} */ | |
116 | #define IGA2_SHADOW_VER_SYNC_START_REG_NUM 2 | |
117 | /* location: {CR76,0,3} */ | |
118 | #define IGA2_SHADOW_VER_SYNC_END_REG_NUM 1 | |
119 | ||
120 | /* Define Register Number for IGA2 CRTC Timing */ | |
121 | ||
122 | /* location: {CR50,0,7},{CR55,0,3} */ | |
123 | #define IGA2_HOR_TOTAL_REG_NUM 2 | |
124 | /* location: {CR51,0,7},{CR55,4,6} */ | |
125 | #define IGA2_HOR_ADDR_REG_NUM 2 | |
126 | /* location: {CR52,0,7},{CR54,0,2} */ | |
127 | #define IGA2_HOR_BLANK_START_REG_NUM 2 | |
128 | /* location: CLE266: {CR53,0,7},{CR54,3,5} => CLE266's CR5D[6] | |
129 | is reserved, so it may have problem to set 1600x1200 on IGA2. */ | |
130 | /* Others: {CR53,0,7},{CR54,3,5},{CR5D,6,6} */ | |
131 | #define IGA2_HOR_BLANK_END_REG_NUM 3 | |
132 | /* location: {CR56,0,7},{CR54,6,7},{CR5C,7,7} */ | |
133 | /* VT3314 and Later: {CR56,0,7},{CR54,6,7},{CR5C,7,7}, {CR5D,7,7} */ | |
134 | #define IGA2_HOR_SYNC_START_REG_NUM 4 | |
135 | ||
136 | /* location: {CR57,0,7},{CR5C,6,6} */ | |
137 | #define IGA2_HOR_SYNC_END_REG_NUM 2 | |
138 | /* location: {CR58,0,7},{CR5D,0,2} */ | |
139 | #define IGA2_VER_TOTAL_REG_NUM 2 | |
140 | /* location: {CR59,0,7},{CR5D,3,5} */ | |
141 | #define IGA2_VER_ADDR_REG_NUM 2 | |
142 | /* location: {CR5A,0,7},{CR5C,0,2} */ | |
143 | #define IGA2_VER_BLANK_START_REG_NUM 2 | |
144 | /* location: {CR5E,0,7},{CR5C,3,5} */ | |
145 | #define IGA2_VER_BLANK_END_REG_NUM 2 | |
146 | /* location: {CR5E,0,7},{CR5F,5,7} */ | |
147 | #define IGA2_VER_SYNC_START_REG_NUM 2 | |
148 | /* location: {CR5F,0,4} */ | |
149 | #define IGA2_VER_SYNC_END_REG_NUM 1 | |
150 | ||
2d6e8851 | 151 | /* Define Fetch Count Register*/ |
d61e0bf3 | 152 | |
d61e0bf3 JC |
153 | /* location: {SR1C,0,7},{SR1D,0,1} */ |
154 | #define IGA1_FETCH_COUNT_REG_NUM 2 | |
155 | /* 16 bytes alignment. */ | |
156 | #define IGA1_FETCH_COUNT_ALIGN_BYTE 16 | |
157 | /* x: H resolution, y: color depth */ | |
158 | #define IGA1_FETCH_COUNT_PATCH_VALUE 4 | |
159 | #define IGA1_FETCH_COUNT_FORMULA(x, y) \ | |
160 | (((x*y)/IGA1_FETCH_COUNT_ALIGN_BYTE) + IGA1_FETCH_COUNT_PATCH_VALUE) | |
161 | ||
d61e0bf3 JC |
162 | /* location: {CR65,0,7},{CR67,2,3} */ |
163 | #define IGA2_FETCH_COUNT_REG_NUM 2 | |
164 | #define IGA2_FETCH_COUNT_ALIGN_BYTE 16 | |
165 | #define IGA2_FETCH_COUNT_PATCH_VALUE 0 | |
166 | #define IGA2_FETCH_COUNT_FORMULA(x, y) \ | |
167 | (((x*y)/IGA2_FETCH_COUNT_ALIGN_BYTE) + IGA2_FETCH_COUNT_PATCH_VALUE) | |
168 | ||
169 | /* Staring Address*/ | |
170 | ||
171 | /* location: {CR0C,0,7},{CR0D,0,7},{CR34,0,7},{CR48,0,1} */ | |
172 | #define IGA1_STARTING_ADDR_REG_NUM 4 | |
173 | /* location: {CR62,1,7},{CR63,0,7},{CR64,0,7} */ | |
174 | #define IGA2_STARTING_ADDR_REG_NUM 3 | |
175 | ||
176 | /* Define Display OFFSET*/ | |
177 | /* These value are by HW suggested value*/ | |
178 | /* location: {SR17,0,7} */ | |
179 | #define K800_IGA1_FIFO_MAX_DEPTH 384 | |
180 | /* location: {SR16,0,5},{SR16,7,7} */ | |
181 | #define K800_IGA1_FIFO_THRESHOLD 328 | |
182 | /* location: {SR18,0,5},{SR18,7,7} */ | |
183 | #define K800_IGA1_FIFO_HIGH_THRESHOLD 296 | |
184 | /* location: {SR22,0,4}. (128/4) =64, K800 must be set zero, */ | |
185 | /* because HW only 5 bits */ | |
186 | #define K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 0 | |
187 | ||
188 | /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */ | |
189 | #define K800_IGA2_FIFO_MAX_DEPTH 384 | |
190 | /* location: {CR68,0,3},{CR95,4,6} */ | |
191 | #define K800_IGA2_FIFO_THRESHOLD 328 | |
192 | /* location: {CR92,0,3},{CR95,0,2} */ | |
193 | #define K800_IGA2_FIFO_HIGH_THRESHOLD 296 | |
194 | /* location: {CR94,0,6} */ | |
195 | #define K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128 | |
196 | ||
197 | /* location: {SR17,0,7} */ | |
198 | #define P880_IGA1_FIFO_MAX_DEPTH 192 | |
199 | /* location: {SR16,0,5},{SR16,7,7} */ | |
200 | #define P880_IGA1_FIFO_THRESHOLD 128 | |
201 | /* location: {SR18,0,5},{SR18,7,7} */ | |
202 | #define P880_IGA1_FIFO_HIGH_THRESHOLD 64 | |
203 | /* location: {SR22,0,4}. (128/4) =64, K800 must be set zero, */ | |
204 | /* because HW only 5 bits */ | |
205 | #define P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 0 | |
206 | ||
207 | /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */ | |
208 | #define P880_IGA2_FIFO_MAX_DEPTH 96 | |
209 | /* location: {CR68,0,3},{CR95,4,6} */ | |
210 | #define P880_IGA2_FIFO_THRESHOLD 64 | |
211 | /* location: {CR92,0,3},{CR95,0,2} */ | |
212 | #define P880_IGA2_FIFO_HIGH_THRESHOLD 32 | |
213 | /* location: {CR94,0,6} */ | |
214 | #define P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128 | |
215 | ||
216 | /* VT3314 chipset*/ | |
217 | ||
218 | /* location: {SR17,0,7} */ | |
219 | #define CN700_IGA1_FIFO_MAX_DEPTH 96 | |
220 | /* location: {SR16,0,5},{SR16,7,7} */ | |
221 | #define CN700_IGA1_FIFO_THRESHOLD 80 | |
222 | /* location: {SR18,0,5},{SR18,7,7} */ | |
223 | #define CN700_IGA1_FIFO_HIGH_THRESHOLD 64 | |
224 | /* location: {SR22,0,4}. (128/4) =64, P800 must be set zero, | |
225 | because HW only 5 bits */ | |
226 | #define CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 0 | |
227 | /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */ | |
228 | #define CN700_IGA2_FIFO_MAX_DEPTH 96 | |
229 | /* location: {CR68,0,3},{CR95,4,6} */ | |
230 | #define CN700_IGA2_FIFO_THRESHOLD 80 | |
231 | /* location: {CR92,0,3},{CR95,0,2} */ | |
232 | #define CN700_IGA2_FIFO_HIGH_THRESHOLD 32 | |
233 | /* location: {CR94,0,6} */ | |
234 | #define CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128 | |
235 | ||
236 | /* For VT3324, these values are suggested by HW */ | |
237 | /* location: {SR17,0,7} */ | |
238 | #define CX700_IGA1_FIFO_MAX_DEPTH 192 | |
239 | /* location: {SR16,0,5},{SR16,7,7} */ | |
240 | #define CX700_IGA1_FIFO_THRESHOLD 128 | |
241 | /* location: {SR18,0,5},{SR18,7,7} */ | |
242 | #define CX700_IGA1_FIFO_HIGH_THRESHOLD 128 | |
243 | /* location: {SR22,0,4} */ | |
244 | #define CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 124 | |
245 | ||
246 | /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */ | |
247 | #define CX700_IGA2_FIFO_MAX_DEPTH 96 | |
248 | /* location: {CR68,0,3},{CR95,4,6} */ | |
249 | #define CX700_IGA2_FIFO_THRESHOLD 64 | |
250 | /* location: {CR92,0,3},{CR95,0,2} */ | |
251 | #define CX700_IGA2_FIFO_HIGH_THRESHOLD 32 | |
252 | /* location: {CR94,0,6} */ | |
253 | #define CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128 | |
254 | ||
255 | /* VT3336 chipset*/ | |
256 | /* location: {SR17,0,7} */ | |
257 | #define K8M890_IGA1_FIFO_MAX_DEPTH 360 | |
258 | /* location: {SR16,0,5},{SR16,7,7} */ | |
259 | #define K8M890_IGA1_FIFO_THRESHOLD 328 | |
260 | /* location: {SR18,0,5},{SR18,7,7} */ | |
261 | #define K8M890_IGA1_FIFO_HIGH_THRESHOLD 296 | |
262 | /* location: {SR22,0,4}. */ | |
263 | #define K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 124 | |
264 | ||
265 | /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */ | |
266 | #define K8M890_IGA2_FIFO_MAX_DEPTH 360 | |
267 | /* location: {CR68,0,3},{CR95,4,6} */ | |
268 | #define K8M890_IGA2_FIFO_THRESHOLD 328 | |
269 | /* location: {CR92,0,3},{CR95,0,2} */ | |
270 | #define K8M890_IGA2_FIFO_HIGH_THRESHOLD 296 | |
271 | /* location: {CR94,0,6} */ | |
272 | #define K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 124 | |
273 | ||
274 | /* VT3327 chipset*/ | |
275 | /* location: {SR17,0,7} */ | |
276 | #define P4M890_IGA1_FIFO_MAX_DEPTH 96 | |
277 | /* location: {SR16,0,5},{SR16,7,7} */ | |
278 | #define P4M890_IGA1_FIFO_THRESHOLD 76 | |
279 | /* location: {SR18,0,5},{SR18,7,7} */ | |
280 | #define P4M890_IGA1_FIFO_HIGH_THRESHOLD 64 | |
281 | /* location: {SR22,0,4}. (32/4) =8 */ | |
282 | #define P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 32 | |
283 | /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */ | |
284 | #define P4M890_IGA2_FIFO_MAX_DEPTH 96 | |
285 | /* location: {CR68,0,3},{CR95,4,6} */ | |
286 | #define P4M890_IGA2_FIFO_THRESHOLD 76 | |
287 | /* location: {CR92,0,3},{CR95,0,2} */ | |
288 | #define P4M890_IGA2_FIFO_HIGH_THRESHOLD 64 | |
289 | /* location: {CR94,0,6} */ | |
290 | #define P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 32 | |
291 | ||
292 | /* VT3364 chipset*/ | |
293 | /* location: {SR17,0,7} */ | |
294 | #define P4M900_IGA1_FIFO_MAX_DEPTH 96 | |
295 | /* location: {SR16,0,5},{SR16,7,7} */ | |
296 | #define P4M900_IGA1_FIFO_THRESHOLD 76 | |
297 | /* location: {SR18,0,5},{SR18,7,7} */ | |
298 | #define P4M900_IGA1_FIFO_HIGH_THRESHOLD 76 | |
299 | /* location: {SR22,0,4}. */ | |
300 | #define P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 32 | |
301 | /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */ | |
302 | #define P4M900_IGA2_FIFO_MAX_DEPTH 96 | |
303 | /* location: {CR68,0,3},{CR95,4,6} */ | |
304 | #define P4M900_IGA2_FIFO_THRESHOLD 76 | |
305 | /* location: {CR92,0,3},{CR95,0,2} */ | |
306 | #define P4M900_IGA2_FIFO_HIGH_THRESHOLD 76 | |
307 | /* location: {CR94,0,6} */ | |
308 | #define P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 32 | |
309 | ||
310 | /* For VT3353, these values are suggested by HW */ | |
311 | /* location: {SR17,0,7} */ | |
312 | #define VX800_IGA1_FIFO_MAX_DEPTH 192 | |
313 | /* location: {SR16,0,5},{SR16,7,7} */ | |
314 | #define VX800_IGA1_FIFO_THRESHOLD 152 | |
315 | /* location: {SR18,0,5},{SR18,7,7} */ | |
316 | #define VX800_IGA1_FIFO_HIGH_THRESHOLD 152 | |
317 | /* location: {SR22,0,4} */ | |
318 | #define VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 64 | |
319 | /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */ | |
320 | #define VX800_IGA2_FIFO_MAX_DEPTH 96 | |
321 | /* location: {CR68,0,3},{CR95,4,6} */ | |
322 | #define VX800_IGA2_FIFO_THRESHOLD 64 | |
323 | /* location: {CR92,0,3},{CR95,0,2} */ | |
324 | #define VX800_IGA2_FIFO_HIGH_THRESHOLD 32 | |
325 | /* location: {CR94,0,6} */ | |
326 | #define VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128 | |
327 | ||
0306ab11 HW |
328 | /* For VT3409 */ |
329 | #define VX855_IGA1_FIFO_MAX_DEPTH 400 | |
330 | #define VX855_IGA1_FIFO_THRESHOLD 320 | |
331 | #define VX855_IGA1_FIFO_HIGH_THRESHOLD 320 | |
332 | #define VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 160 | |
333 | ||
334 | #define VX855_IGA2_FIFO_MAX_DEPTH 200 | |
335 | #define VX855_IGA2_FIFO_THRESHOLD 160 | |
336 | #define VX855_IGA2_FIFO_HIGH_THRESHOLD 160 | |
337 | #define VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 320 | |
338 | ||
d61e0bf3 JC |
339 | #define IGA1_FIFO_DEPTH_SELECT_REG_NUM 1 |
340 | #define IGA1_FIFO_THRESHOLD_REG_NUM 2 | |
341 | #define IGA1_FIFO_HIGH_THRESHOLD_REG_NUM 2 | |
342 | #define IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM 1 | |
343 | ||
344 | #define IGA2_FIFO_DEPTH_SELECT_REG_NUM 3 | |
345 | #define IGA2_FIFO_THRESHOLD_REG_NUM 2 | |
346 | #define IGA2_FIFO_HIGH_THRESHOLD_REG_NUM 2 | |
347 | #define IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM 1 | |
348 | ||
349 | #define IGA1_FIFO_DEPTH_SELECT_FORMULA(x) ((x/2)-1) | |
350 | #define IGA1_FIFO_THRESHOLD_FORMULA(x) (x/4) | |
351 | #define IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(x) (x/4) | |
352 | #define IGA1_FIFO_HIGH_THRESHOLD_FORMULA(x) (x/4) | |
353 | #define IGA2_FIFO_DEPTH_SELECT_FORMULA(x) (((x/2)/4)-1) | |
354 | #define IGA2_FIFO_THRESHOLD_FORMULA(x) (x/4) | |
355 | #define IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(x) (x/4) | |
356 | #define IGA2_FIFO_HIGH_THRESHOLD_FORMULA(x) (x/4) | |
357 | ||
358 | /************************************************************************/ | |
359 | /* LCD Timing */ | |
360 | /************************************************************************/ | |
361 | ||
362 | /* 500 ms = 500000 us */ | |
363 | #define LCD_POWER_SEQ_TD0 500000 | |
364 | /* 50 ms = 50000 us */ | |
365 | #define LCD_POWER_SEQ_TD1 50000 | |
366 | /* 0 us */ | |
367 | #define LCD_POWER_SEQ_TD2 0 | |
368 | /* 210 ms = 210000 us */ | |
369 | #define LCD_POWER_SEQ_TD3 210000 | |
370 | /* 2^10 * (1/14.31818M) = 71.475 us (K400.revA) */ | |
371 | #define CLE266_POWER_SEQ_UNIT 71 | |
372 | /* 2^11 * (1/14.31818M) = 142.95 us (K400.revB) */ | |
373 | #define K800_POWER_SEQ_UNIT 142 | |
374 | /* 2^13 * (1/14.31818M) = 572.1 us */ | |
375 | #define P880_POWER_SEQ_UNIT 572 | |
376 | ||
377 | #define CLE266_POWER_SEQ_FORMULA(x) ((x)/CLE266_POWER_SEQ_UNIT) | |
378 | #define K800_POWER_SEQ_FORMULA(x) ((x)/K800_POWER_SEQ_UNIT) | |
379 | #define P880_POWER_SEQ_FORMULA(x) ((x)/P880_POWER_SEQ_UNIT) | |
380 | ||
381 | /* location: {CR8B,0,7},{CR8F,0,3} */ | |
382 | #define LCD_POWER_SEQ_TD0_REG_NUM 2 | |
383 | /* location: {CR8C,0,7},{CR8F,4,7} */ | |
384 | #define LCD_POWER_SEQ_TD1_REG_NUM 2 | |
385 | /* location: {CR8D,0,7},{CR90,0,3} */ | |
386 | #define LCD_POWER_SEQ_TD2_REG_NUM 2 | |
387 | /* location: {CR8E,0,7},{CR90,4,7} */ | |
388 | #define LCD_POWER_SEQ_TD3_REG_NUM 2 | |
389 | ||
390 | /* LCD Scaling factor*/ | |
391 | /* x: indicate setting horizontal size*/ | |
392 | /* y: indicate panel horizontal size*/ | |
393 | ||
394 | /* Horizontal scaling factor 10 bits (2^10) */ | |
395 | #define CLE266_LCD_HOR_SCF_FORMULA(x, y) (((x-1)*1024)/(y-1)) | |
396 | /* Vertical scaling factor 10 bits (2^10) */ | |
397 | #define CLE266_LCD_VER_SCF_FORMULA(x, y) (((x-1)*1024)/(y-1)) | |
398 | /* Horizontal scaling factor 10 bits (2^12) */ | |
399 | #define K800_LCD_HOR_SCF_FORMULA(x, y) (((x-1)*4096)/(y-1)) | |
400 | /* Vertical scaling factor 10 bits (2^11) */ | |
401 | #define K800_LCD_VER_SCF_FORMULA(x, y) (((x-1)*2048)/(y-1)) | |
402 | ||
403 | /* location: {CR9F,0,1},{CR77,0,7},{CR79,4,5} */ | |
404 | #define LCD_HOR_SCALING_FACTOR_REG_NUM 3 | |
405 | /* location: {CR79,3,3},{CR78,0,7},{CR79,6,7} */ | |
406 | #define LCD_VER_SCALING_FACTOR_REG_NUM 3 | |
407 | /* location: {CR77,0,7},{CR79,4,5} */ | |
408 | #define LCD_HOR_SCALING_FACTOR_REG_NUM_CLE 2 | |
409 | /* location: {CR78,0,7},{CR79,6,7} */ | |
410 | #define LCD_VER_SCALING_FACTOR_REG_NUM_CLE 2 | |
411 | ||
412 | /************************************************ | |
413 | ***** Define IGA1 Display Timing ***** | |
414 | ************************************************/ | |
415 | struct io_register { | |
416 | u8 io_addr; | |
417 | u8 start_bit; | |
418 | u8 end_bit; | |
419 | }; | |
420 | ||
421 | /* IGA1 Horizontal Total */ | |
422 | struct iga1_hor_total { | |
423 | int reg_num; | |
424 | struct io_register reg[IGA1_HOR_TOTAL_REG_NUM]; | |
425 | }; | |
426 | ||
427 | /* IGA1 Horizontal Addressable Video */ | |
428 | struct iga1_hor_addr { | |
429 | int reg_num; | |
430 | struct io_register reg[IGA1_HOR_ADDR_REG_NUM]; | |
431 | }; | |
432 | ||
433 | /* IGA1 Horizontal Blank Start */ | |
434 | struct iga1_hor_blank_start { | |
435 | int reg_num; | |
436 | struct io_register reg[IGA1_HOR_BLANK_START_REG_NUM]; | |
437 | }; | |
438 | ||
439 | /* IGA1 Horizontal Blank End */ | |
440 | struct iga1_hor_blank_end { | |
441 | int reg_num; | |
442 | struct io_register reg[IGA1_HOR_BLANK_END_REG_NUM]; | |
443 | }; | |
444 | ||
445 | /* IGA1 Horizontal Sync Start */ | |
446 | struct iga1_hor_sync_start { | |
447 | int reg_num; | |
448 | struct io_register reg[IGA1_HOR_SYNC_START_REG_NUM]; | |
449 | }; | |
450 | ||
451 | /* IGA1 Horizontal Sync End */ | |
452 | struct iga1_hor_sync_end { | |
453 | int reg_num; | |
454 | struct io_register reg[IGA1_HOR_SYNC_END_REG_NUM]; | |
455 | }; | |
456 | ||
457 | /* IGA1 Vertical Total */ | |
458 | struct iga1_ver_total { | |
459 | int reg_num; | |
460 | struct io_register reg[IGA1_VER_TOTAL_REG_NUM]; | |
461 | }; | |
462 | ||
463 | /* IGA1 Vertical Addressable Video */ | |
464 | struct iga1_ver_addr { | |
465 | int reg_num; | |
466 | struct io_register reg[IGA1_VER_ADDR_REG_NUM]; | |
467 | }; | |
468 | ||
469 | /* IGA1 Vertical Blank Start */ | |
470 | struct iga1_ver_blank_start { | |
471 | int reg_num; | |
472 | struct io_register reg[IGA1_VER_BLANK_START_REG_NUM]; | |
473 | }; | |
474 | ||
475 | /* IGA1 Vertical Blank End */ | |
476 | struct iga1_ver_blank_end { | |
477 | int reg_num; | |
478 | struct io_register reg[IGA1_VER_BLANK_END_REG_NUM]; | |
479 | }; | |
480 | ||
481 | /* IGA1 Vertical Sync Start */ | |
482 | struct iga1_ver_sync_start { | |
483 | int reg_num; | |
484 | struct io_register reg[IGA1_VER_SYNC_START_REG_NUM]; | |
485 | }; | |
486 | ||
487 | /* IGA1 Vertical Sync End */ | |
488 | struct iga1_ver_sync_end { | |
489 | int reg_num; | |
490 | struct io_register reg[IGA1_VER_SYNC_END_REG_NUM]; | |
491 | }; | |
492 | ||
493 | /***************************************************** | |
494 | ** Define IGA2 Shadow Display Timing **** | |
495 | *****************************************************/ | |
496 | ||
497 | /* IGA2 Shadow Horizontal Total */ | |
498 | struct iga2_shadow_hor_total { | |
499 | int reg_num; | |
500 | struct io_register reg[IGA2_SHADOW_HOR_TOTAL_REG_NUM]; | |
501 | }; | |
502 | ||
503 | /* IGA2 Shadow Horizontal Blank End */ | |
504 | struct iga2_shadow_hor_blank_end { | |
505 | int reg_num; | |
506 | struct io_register reg[IGA2_SHADOW_HOR_BLANK_END_REG_NUM]; | |
507 | }; | |
508 | ||
509 | /* IGA2 Shadow Vertical Total */ | |
510 | struct iga2_shadow_ver_total { | |
511 | int reg_num; | |
512 | struct io_register reg[IGA2_SHADOW_VER_TOTAL_REG_NUM]; | |
513 | }; | |
514 | ||
515 | /* IGA2 Shadow Vertical Addressable Video */ | |
516 | struct iga2_shadow_ver_addr { | |
517 | int reg_num; | |
518 | struct io_register reg[IGA2_SHADOW_VER_ADDR_REG_NUM]; | |
519 | }; | |
520 | ||
521 | /* IGA2 Shadow Vertical Blank Start */ | |
522 | struct iga2_shadow_ver_blank_start { | |
523 | int reg_num; | |
524 | struct io_register reg[IGA2_SHADOW_VER_BLANK_START_REG_NUM]; | |
525 | }; | |
526 | ||
527 | /* IGA2 Shadow Vertical Blank End */ | |
528 | struct iga2_shadow_ver_blank_end { | |
529 | int reg_num; | |
530 | struct io_register reg[IGA2_SHADOW_VER_BLANK_END_REG_NUM]; | |
531 | }; | |
532 | ||
533 | /* IGA2 Shadow Vertical Sync Start */ | |
534 | struct iga2_shadow_ver_sync_start { | |
535 | int reg_num; | |
536 | struct io_register reg[IGA2_SHADOW_VER_SYNC_START_REG_NUM]; | |
537 | }; | |
538 | ||
539 | /* IGA2 Shadow Vertical Sync End */ | |
540 | struct iga2_shadow_ver_sync_end { | |
541 | int reg_num; | |
542 | struct io_register reg[IGA2_SHADOW_VER_SYNC_END_REG_NUM]; | |
543 | }; | |
544 | ||
545 | /***************************************************** | |
546 | ** Define IGA2 Display Timing **** | |
547 | ******************************************************/ | |
548 | ||
549 | /* IGA2 Horizontal Total */ | |
550 | struct iga2_hor_total { | |
551 | int reg_num; | |
552 | struct io_register reg[IGA2_HOR_TOTAL_REG_NUM]; | |
553 | }; | |
554 | ||
555 | /* IGA2 Horizontal Addressable Video */ | |
556 | struct iga2_hor_addr { | |
557 | int reg_num; | |
558 | struct io_register reg[IGA2_HOR_ADDR_REG_NUM]; | |
559 | }; | |
560 | ||
561 | /* IGA2 Horizontal Blank Start */ | |
562 | struct iga2_hor_blank_start { | |
563 | int reg_num; | |
564 | struct io_register reg[IGA2_HOR_BLANK_START_REG_NUM]; | |
565 | }; | |
566 | ||
567 | /* IGA2 Horizontal Blank End */ | |
568 | struct iga2_hor_blank_end { | |
569 | int reg_num; | |
570 | struct io_register reg[IGA2_HOR_BLANK_END_REG_NUM]; | |
571 | }; | |
572 | ||
573 | /* IGA2 Horizontal Sync Start */ | |
574 | struct iga2_hor_sync_start { | |
575 | int reg_num; | |
576 | struct io_register reg[IGA2_HOR_SYNC_START_REG_NUM]; | |
577 | }; | |
578 | ||
579 | /* IGA2 Horizontal Sync End */ | |
580 | struct iga2_hor_sync_end { | |
581 | int reg_num; | |
582 | struct io_register reg[IGA2_HOR_SYNC_END_REG_NUM]; | |
583 | }; | |
584 | ||
585 | /* IGA2 Vertical Total */ | |
586 | struct iga2_ver_total { | |
587 | int reg_num; | |
588 | struct io_register reg[IGA2_VER_TOTAL_REG_NUM]; | |
589 | }; | |
590 | ||
591 | /* IGA2 Vertical Addressable Video */ | |
592 | struct iga2_ver_addr { | |
593 | int reg_num; | |
594 | struct io_register reg[IGA2_VER_ADDR_REG_NUM]; | |
595 | }; | |
596 | ||
597 | /* IGA2 Vertical Blank Start */ | |
598 | struct iga2_ver_blank_start { | |
599 | int reg_num; | |
600 | struct io_register reg[IGA2_VER_BLANK_START_REG_NUM]; | |
601 | }; | |
602 | ||
603 | /* IGA2 Vertical Blank End */ | |
604 | struct iga2_ver_blank_end { | |
605 | int reg_num; | |
606 | struct io_register reg[IGA2_VER_BLANK_END_REG_NUM]; | |
607 | }; | |
608 | ||
609 | /* IGA2 Vertical Sync Start */ | |
610 | struct iga2_ver_sync_start { | |
611 | int reg_num; | |
612 | struct io_register reg[IGA2_VER_SYNC_START_REG_NUM]; | |
613 | }; | |
614 | ||
615 | /* IGA2 Vertical Sync End */ | |
616 | struct iga2_ver_sync_end { | |
617 | int reg_num; | |
618 | struct io_register reg[IGA2_VER_SYNC_END_REG_NUM]; | |
619 | }; | |
620 | ||
d61e0bf3 JC |
621 | /* IGA1 Fetch Count Register */ |
622 | struct iga1_fetch_count { | |
623 | int reg_num; | |
624 | struct io_register reg[IGA1_FETCH_COUNT_REG_NUM]; | |
625 | }; | |
626 | ||
627 | /* IGA2 Fetch Count Register */ | |
628 | struct iga2_fetch_count { | |
629 | int reg_num; | |
630 | struct io_register reg[IGA2_FETCH_COUNT_REG_NUM]; | |
631 | }; | |
632 | ||
633 | struct fetch_count { | |
634 | struct iga1_fetch_count iga1_fetch_count_reg; | |
635 | struct iga2_fetch_count iga2_fetch_count_reg; | |
636 | }; | |
637 | ||
638 | /* Starting Address Register */ | |
639 | struct iga1_starting_addr { | |
640 | int reg_num; | |
641 | struct io_register reg[IGA1_STARTING_ADDR_REG_NUM]; | |
642 | }; | |
643 | ||
644 | struct iga2_starting_addr { | |
645 | int reg_num; | |
646 | struct io_register reg[IGA2_STARTING_ADDR_REG_NUM]; | |
647 | }; | |
648 | ||
649 | struct starting_addr { | |
650 | struct iga1_starting_addr iga1_starting_addr_reg; | |
651 | struct iga2_starting_addr iga2_starting_addr_reg; | |
652 | }; | |
653 | ||
654 | /* LCD Power Sequence Timer */ | |
655 | struct lcd_pwd_seq_td0 { | |
656 | int reg_num; | |
657 | struct io_register reg[LCD_POWER_SEQ_TD0_REG_NUM]; | |
658 | }; | |
659 | ||
660 | struct lcd_pwd_seq_td1 { | |
661 | int reg_num; | |
662 | struct io_register reg[LCD_POWER_SEQ_TD1_REG_NUM]; | |
663 | }; | |
664 | ||
665 | struct lcd_pwd_seq_td2 { | |
666 | int reg_num; | |
667 | struct io_register reg[LCD_POWER_SEQ_TD2_REG_NUM]; | |
668 | }; | |
669 | ||
670 | struct lcd_pwd_seq_td3 { | |
671 | int reg_num; | |
672 | struct io_register reg[LCD_POWER_SEQ_TD3_REG_NUM]; | |
673 | }; | |
674 | ||
675 | struct _lcd_pwd_seq_timer { | |
676 | struct lcd_pwd_seq_td0 td0; | |
677 | struct lcd_pwd_seq_td1 td1; | |
678 | struct lcd_pwd_seq_td2 td2; | |
679 | struct lcd_pwd_seq_td3 td3; | |
680 | }; | |
681 | ||
682 | /* LCD Scaling Factor */ | |
683 | struct _lcd_hor_scaling_factor { | |
684 | int reg_num; | |
685 | struct io_register reg[LCD_HOR_SCALING_FACTOR_REG_NUM]; | |
686 | }; | |
687 | ||
688 | struct _lcd_ver_scaling_factor { | |
689 | int reg_num; | |
690 | struct io_register reg[LCD_VER_SCALING_FACTOR_REG_NUM]; | |
691 | }; | |
692 | ||
693 | struct _lcd_scaling_factor { | |
694 | struct _lcd_hor_scaling_factor lcd_hor_scaling_factor; | |
695 | struct _lcd_ver_scaling_factor lcd_ver_scaling_factor; | |
696 | }; | |
697 | ||
698 | struct pll_map { | |
699 | u32 clk; | |
700 | u32 cle266_pll; | |
701 | u32 k800_pll; | |
702 | u32 cx700_pll; | |
0306ab11 | 703 | u32 vx855_pll; |
d61e0bf3 JC |
704 | }; |
705 | ||
706 | struct rgbLUT { | |
707 | u8 red; | |
708 | u8 green; | |
709 | u8 blue; | |
710 | }; | |
711 | ||
712 | struct lcd_pwd_seq_timer { | |
713 | u16 td0; | |
714 | u16 td1; | |
715 | u16 td2; | |
716 | u16 td3; | |
717 | }; | |
718 | ||
719 | /* Display FIFO Relation Registers*/ | |
720 | struct iga1_fifo_depth_select { | |
721 | int reg_num; | |
722 | struct io_register reg[IGA1_FIFO_DEPTH_SELECT_REG_NUM]; | |
723 | }; | |
724 | ||
725 | struct iga1_fifo_threshold_select { | |
726 | int reg_num; | |
727 | struct io_register reg[IGA1_FIFO_THRESHOLD_REG_NUM]; | |
728 | }; | |
729 | ||
730 | struct iga1_fifo_high_threshold_select { | |
731 | int reg_num; | |
732 | struct io_register reg[IGA1_FIFO_HIGH_THRESHOLD_REG_NUM]; | |
733 | }; | |
734 | ||
735 | struct iga1_display_queue_expire_num { | |
736 | int reg_num; | |
737 | struct io_register reg[IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM]; | |
738 | }; | |
739 | ||
740 | struct iga2_fifo_depth_select { | |
741 | int reg_num; | |
742 | struct io_register reg[IGA2_FIFO_DEPTH_SELECT_REG_NUM]; | |
743 | }; | |
744 | ||
745 | struct iga2_fifo_threshold_select { | |
746 | int reg_num; | |
747 | struct io_register reg[IGA2_FIFO_THRESHOLD_REG_NUM]; | |
748 | }; | |
749 | ||
750 | struct iga2_fifo_high_threshold_select { | |
751 | int reg_num; | |
752 | struct io_register reg[IGA2_FIFO_HIGH_THRESHOLD_REG_NUM]; | |
753 | }; | |
754 | ||
755 | struct iga2_display_queue_expire_num { | |
756 | int reg_num; | |
757 | struct io_register reg[IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM]; | |
758 | }; | |
759 | ||
760 | struct fifo_depth_select { | |
761 | struct iga1_fifo_depth_select iga1_fifo_depth_select_reg; | |
762 | struct iga2_fifo_depth_select iga2_fifo_depth_select_reg; | |
763 | }; | |
764 | ||
765 | struct fifo_threshold_select { | |
766 | struct iga1_fifo_threshold_select iga1_fifo_threshold_select_reg; | |
767 | struct iga2_fifo_threshold_select iga2_fifo_threshold_select_reg; | |
768 | }; | |
769 | ||
770 | struct fifo_high_threshold_select { | |
771 | struct iga1_fifo_high_threshold_select | |
772 | iga1_fifo_high_threshold_select_reg; | |
773 | struct iga2_fifo_high_threshold_select | |
774 | iga2_fifo_high_threshold_select_reg; | |
775 | }; | |
776 | ||
777 | struct display_queue_expire_num { | |
778 | struct iga1_display_queue_expire_num | |
779 | iga1_display_queue_expire_num_reg; | |
780 | struct iga2_display_queue_expire_num | |
781 | iga2_display_queue_expire_num_reg; | |
782 | }; | |
783 | ||
784 | struct iga1_crtc_timing { | |
785 | struct iga1_hor_total hor_total; | |
786 | struct iga1_hor_addr hor_addr; | |
787 | struct iga1_hor_blank_start hor_blank_start; | |
788 | struct iga1_hor_blank_end hor_blank_end; | |
789 | struct iga1_hor_sync_start hor_sync_start; | |
790 | struct iga1_hor_sync_end hor_sync_end; | |
791 | struct iga1_ver_total ver_total; | |
792 | struct iga1_ver_addr ver_addr; | |
793 | struct iga1_ver_blank_start ver_blank_start; | |
794 | struct iga1_ver_blank_end ver_blank_end; | |
795 | struct iga1_ver_sync_start ver_sync_start; | |
796 | struct iga1_ver_sync_end ver_sync_end; | |
797 | }; | |
798 | ||
799 | struct iga2_shadow_crtc_timing { | |
800 | struct iga2_shadow_hor_total hor_total_shadow; | |
801 | struct iga2_shadow_hor_blank_end hor_blank_end_shadow; | |
802 | struct iga2_shadow_ver_total ver_total_shadow; | |
803 | struct iga2_shadow_ver_addr ver_addr_shadow; | |
804 | struct iga2_shadow_ver_blank_start ver_blank_start_shadow; | |
805 | struct iga2_shadow_ver_blank_end ver_blank_end_shadow; | |
806 | struct iga2_shadow_ver_sync_start ver_sync_start_shadow; | |
807 | struct iga2_shadow_ver_sync_end ver_sync_end_shadow; | |
808 | }; | |
809 | ||
810 | struct iga2_crtc_timing { | |
811 | struct iga2_hor_total hor_total; | |
812 | struct iga2_hor_addr hor_addr; | |
813 | struct iga2_hor_blank_start hor_blank_start; | |
814 | struct iga2_hor_blank_end hor_blank_end; | |
815 | struct iga2_hor_sync_start hor_sync_start; | |
816 | struct iga2_hor_sync_end hor_sync_end; | |
817 | struct iga2_ver_total ver_total; | |
818 | struct iga2_ver_addr ver_addr; | |
819 | struct iga2_ver_blank_start ver_blank_start; | |
820 | struct iga2_ver_blank_end ver_blank_end; | |
821 | struct iga2_ver_sync_start ver_sync_start; | |
822 | struct iga2_ver_sync_end ver_sync_end; | |
823 | }; | |
824 | ||
825 | /* device ID */ | |
b72a5070 HW |
826 | #define CLE266_FUNCTION3 0x3123 |
827 | #define KM400_FUNCTION3 0x3205 | |
d61e0bf3 JC |
828 | #define CN400_FUNCTION2 0x2259 |
829 | #define CN400_FUNCTION3 0x3259 | |
830 | /* support VT3314 chipset */ | |
831 | #define CN700_FUNCTION2 0x2314 | |
832 | #define CN700_FUNCTION3 0x3208 | |
833 | /* VT3324 chipset */ | |
834 | #define CX700_FUNCTION2 0x2324 | |
835 | #define CX700_FUNCTION3 0x3324 | |
836 | /* VT3204 chipset*/ | |
837 | #define KM800_FUNCTION3 0x3204 | |
838 | /* VT3336 chipset*/ | |
839 | #define KM890_FUNCTION3 0x3336 | |
840 | /* VT3327 chipset*/ | |
841 | #define P4M890_FUNCTION3 0x3327 | |
842 | /* VT3293 chipset*/ | |
843 | #define CN750_FUNCTION3 0x3208 | |
844 | /* VT3364 chipset*/ | |
845 | #define P4M900_FUNCTION3 0x3364 | |
846 | /* VT3353 chipset*/ | |
847 | #define VX800_FUNCTION3 0x3353 | |
0306ab11 HW |
848 | /* VT3409 chipset*/ |
849 | #define VX855_FUNCTION3 0x3409 | |
d61e0bf3 JC |
850 | |
851 | #define NUM_TOTAL_PLL_TABLE ARRAY_SIZE(pll_value) | |
852 | ||
853 | struct IODATA { | |
854 | u8 Index; | |
855 | u8 Mask; | |
856 | u8 Data; | |
857 | }; | |
858 | ||
859 | struct pci_device_id_info { | |
860 | u32 vendor; | |
861 | u32 device; | |
862 | u32 chip_index; | |
863 | }; | |
864 | ||
865 | extern unsigned int viafb_second_virtual_xres; | |
d61e0bf3 JC |
866 | extern int viafb_SAMM_ON; |
867 | extern int viafb_dual_fb; | |
868 | extern int viafb_LCD2_ON; | |
869 | extern int viafb_LCD_ON; | |
870 | extern int viafb_DVI_ON; | |
d61e0bf3 JC |
871 | extern int viafb_hotplug; |
872 | ||
873 | void viafb_write_reg_mask(u8 index, int io_port, u8 data, u8 mask); | |
874 | void viafb_set_output_path(int device, int set_iga, | |
875 | int output_interface); | |
dd73d686 | 876 | |
d61e0bf3 | 877 | void viafb_fill_crtc_timing(struct crt_mode_table *crt_table, |
dd73d686 | 878 | struct VideoModeTable *video_mode, int bpp_byte, int set_iga); |
d61e0bf3 JC |
879 | |
880 | void viafb_set_vclock(u32 CLK, int set_iga); | |
881 | void viafb_load_reg(int timing_value, int viafb_load_reg_num, | |
882 | struct io_register *reg, | |
883 | int io_type); | |
884 | void viafb_crt_disable(void); | |
885 | void viafb_crt_enable(void); | |
886 | void init_ad9389(void); | |
887 | /* Access I/O Function */ | |
888 | void viafb_write_reg(u8 index, u16 io_port, u8 data); | |
889 | u8 viafb_read_reg(int io_port, u8 index); | |
890 | void viafb_lock_crt(void); | |
891 | void viafb_unlock_crt(void); | |
d61e0bf3 JC |
892 | void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga); |
893 | void viafb_write_regx(struct io_reg RegTable[], int ItemNum); | |
d61e0bf3 JC |
894 | u32 viafb_get_clk_value(int clk); |
895 | void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active); | |
d61e0bf3 JC |
896 | void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\ |
897 | *p_gfx_dpa_setting); | |
898 | ||
dd73d686 FTS |
899 | int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp, |
900 | struct VideoModeTable *vmode_tbl1, int video_bpp1); | |
901 | void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh, | |
902 | struct VideoModeTable *vmode_tbl); | |
24b4d82e | 903 | void viafb_init_chip_info(int chip_type); |
d61e0bf3 JC |
904 | void viafb_init_dac(int set_iga); |
905 | int viafb_get_pixclock(int hres, int vres, int vmode_refresh); | |
906 | int viafb_get_refresh(int hres, int vres, u32 float_refresh); | |
907 | void viafb_update_device_setting(int hres, int vres, int bpp, | |
908 | int vmode_refresh, int flag); | |
d61e0bf3 JC |
909 | |
910 | void viafb_set_iga_path(void); | |
09cf1180 FTS |
911 | void viafb_set_primary_address(u32 addr); |
912 | void viafb_set_secondary_address(u32 addr); | |
2d6e8851 FTS |
913 | void viafb_set_primary_pitch(u32 pitch); |
914 | void viafb_set_secondary_pitch(u32 pitch); | |
415559fb FTS |
915 | void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue); |
916 | void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue); | |
d61e0bf3 JC |
917 | void viafb_get_fb_info(unsigned int *fb_base, unsigned int *fb_len); |
918 | ||
919 | #endif /* __HW_H__ */ |