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viafb: Separate global and fb-specific data
[deliverable/linux.git] / drivers / video / via / lcd.c
CommitLineData
ac6c97e2
JC		 1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
24b4d82e
JC		 21#include "via-core.h"
22#include "via_i2c.h"
ac6c97e2
JC		 23#include "global.h"
24#include "lcdtbl.h"
25
dd73d686
FTS		 26#define viafb_compact_res(x, y) (((x)<<16)|(y))
27
ac6c97e2
JC		 28static struct _lcd_scaling_factor lcd_scaling_factor = {
29 /* LCD Horizontal Scaling Factor Register */
30 {LCD_HOR_SCALING_FACTOR_REG_NUM,
31 {{CR9F, 0, 1}, {CR77, 0, 7}, {CR79, 4, 5} } },
32 /* LCD Vertical Scaling Factor Register */
33 {LCD_VER_SCALING_FACTOR_REG_NUM,
34 {{CR79, 3, 3}, {CR78, 0, 7}, {CR79, 6, 7} } }
35};
36static struct _lcd_scaling_factor lcd_scaling_factor_CLE = {
37 /* LCD Horizontal Scaling Factor Register */
38 {LCD_HOR_SCALING_FACTOR_REG_NUM_CLE, {{CR77, 0, 7}, {CR79, 4, 5} } },
39 /* LCD Vertical Scaling Factor Register */
40 {LCD_VER_SCALING_FACTOR_REG_NUM_CLE, {{CR78, 0, 7}, {CR79, 6, 7} } }
41};
42
43static int check_lvds_chip(int device_id_subaddr, int device_id);
44static bool lvds_identify_integratedlvds(void);
9b24b00c 45static void fp_id_to_vindex(int panel_id);
ac6c97e2
JC		 46static int lvds_register_read(int index);
47static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres,
48 int panel_vres);
ac6c97e2
JC		 49static void via_pitch_alignment_patch_lcd(
50 struct lvds_setting_information *plvds_setting_info,
51 struct lvds_chip_information
52 *plvds_chip_info);
53static void lcd_patch_skew_dvp0(struct lvds_setting_information
54 *plvds_setting_info,
55 struct lvds_chip_information *plvds_chip_info);
56static void lcd_patch_skew_dvp1(struct lvds_setting_information
57 *plvds_setting_info,
58 struct lvds_chip_information *plvds_chip_info);
59static void lcd_patch_skew(struct lvds_setting_information
60 *plvds_setting_info, struct lvds_chip_information *plvds_chip_info);
61
62static void integrated_lvds_disable(struct lvds_setting_information
63 *plvds_setting_info,
64 struct lvds_chip_information *plvds_chip_info);
65static void integrated_lvds_enable(struct lvds_setting_information
66 *plvds_setting_info,
67 struct lvds_chip_information *plvds_chip_info);
68static void lcd_powersequence_off(void);
69static void lcd_powersequence_on(void);
70static void fill_lcd_format(void);
71static void check_diport_of_integrated_lvds(
72 struct lvds_chip_information *plvds_chip_info,
73 struct lvds_setting_information
74 *plvds_setting_info);
75static struct display_timing lcd_centering_timging(struct display_timing
76 mode_crt_reg,
77 struct display_timing panel_crt_reg);
ac6c97e2
JC		 78static void viafb_load_scaling_factor_for_p4m900(int set_hres,
79 int set_vres, int panel_hres, int panel_vres);
80
81static int check_lvds_chip(int device_id_subaddr, int device_id)
82{
83 if (lvds_register_read(device_id_subaddr) == device_id)
84 return OK;
85 else
86 return FAIL;
87}
88
89void viafb_init_lcd_size(void)
90{
91 DEBUG_MSG(KERN_INFO "viafb_init_lcd_size()\n");
92 DEBUG_MSG(KERN_INFO
93 "viaparinfo->lvds_setting_info->get_lcd_size_method %d\n",
94 viaparinfo->lvds_setting_info->get_lcd_size_method);
95
96 switch (viaparinfo->lvds_setting_info->get_lcd_size_method) {
97 case GET_LCD_SIZE_BY_SYSTEM_BIOS:
98 break;
99 case GET_LCD_SZIE_BY_HW_STRAPPING:
100 break;
101 case GET_LCD_SIZE_BY_VGA_BIOS:
102 DEBUG_MSG(KERN_INFO "Get LCD Size method by VGA BIOS !!\n");
9b24b00c 103 fp_id_to_vindex(viafb_lcd_panel_id);
ac6c97e2
JC		 104 DEBUG_MSG(KERN_INFO "LCD Panel_ID = %d\n",
105 viaparinfo->lvds_setting_info->lcd_panel_id);
ac6c97e2
JC		 106 break;
107 case GET_LCD_SIZE_BY_USER_SETTING:
108 DEBUG_MSG(KERN_INFO "Get LCD Size method by user setting !!\n");
9b24b00c 109 fp_id_to_vindex(viafb_lcd_panel_id);
ac6c97e2
JC		 110 DEBUG_MSG(KERN_INFO "LCD Panel_ID = %d\n",
111 viaparinfo->lvds_setting_info->lcd_panel_id);
ac6c97e2
JC		 112 break;
113 default:
114 DEBUG_MSG(KERN_INFO "viafb_init_lcd_size fail\n");
115 viaparinfo->lvds_setting_info->lcd_panel_id =
116 LCD_PANEL_ID1_800X600;
9b24b00c 117 fp_id_to_vindex(LCD_PANEL_ID1_800X600);
ac6c97e2
JC		 118 }
119 viaparinfo->lvds_setting_info2->lcd_panel_id =
120 viaparinfo->lvds_setting_info->lcd_panel_id;
ac6c97e2
JC		 121 viaparinfo->lvds_setting_info2->lcd_panel_hres =
122 viaparinfo->lvds_setting_info->lcd_panel_hres;
123 viaparinfo->lvds_setting_info2->lcd_panel_vres =
124 viaparinfo->lvds_setting_info->lcd_panel_vres;
125 viaparinfo->lvds_setting_info2->device_lcd_dualedge =
126 viaparinfo->lvds_setting_info->device_lcd_dualedge;
127 viaparinfo->lvds_setting_info2->LCDDithering =
128 viaparinfo->lvds_setting_info->LCDDithering;
129}
130
131static bool lvds_identify_integratedlvds(void)
132{
133 if (viafb_display_hardware_layout == HW_LAYOUT_LCD_EXTERNAL_LCD2) {
134 /* Two dual channel LCD (Internal LVDS + External LVDS): */
135 /* If we have an external LVDS, such as VT1636, we should
136 have its chip ID already. */
137 if (viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
138 viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name =
139 INTEGRATED_LVDS;
2c0e0c88
JP		 140 DEBUG_MSG(KERN_INFO "Support two dual channel LVDS! "
141 "(Internal LVDS + External LVDS)\n");
ac6c97e2
JC		 142 } else {
143 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
144 INTEGRATED_LVDS;
2c0e0c88
JP		 145 DEBUG_MSG(KERN_INFO "Not found external LVDS, "
146 "so can't support two dual channel LVDS!\n");
ac6c97e2
JC		 147 }
148 } else if (viafb_display_hardware_layout == HW_LAYOUT_LCD1_LCD2) {
149 /* Two single channel LCD (Internal LVDS + Internal LVDS): */
150 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
151 INTEGRATED_LVDS;
152 viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name =
153 INTEGRATED_LVDS;
2c0e0c88
JP		 154 DEBUG_MSG(KERN_INFO "Support two single channel LVDS! "
155 "(Internal LVDS + Internal LVDS)\n");
ac6c97e2
JC		 156 } else if (viafb_display_hardware_layout != HW_LAYOUT_DVI_ONLY) {
157 /* If we have found external LVDS, just use it,
158 otherwise, we will use internal LVDS as default. */
159 if (!viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
160 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
161 INTEGRATED_LVDS;
162 DEBUG_MSG(KERN_INFO "Found Integrated LVDS!\n");
163 }
164 } else {
165 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
166 NON_LVDS_TRANSMITTER;
167 DEBUG_MSG(KERN_INFO "Do not support LVDS!\n");
168 return false;
169 }
170
171 return true;
172}
173
174int viafb_lvds_trasmitter_identify(void)
175{
f045f77b
JC		 176 if (viafb_lvds_identify_vt1636(VIA_PORT_31)) {
177 viaparinfo->chip_info->lvds_chip_info.i2c_port = VIA_PORT_31;
ac6c97e2 178 DEBUG_MSG(KERN_INFO
277d32a3 179 "Found VIA VT1636 LVDS on port i2c 0x31\n");
ac6c97e2 180 } else {
f045f77b 181 if (viafb_lvds_identify_vt1636(VIA_PORT_2C)) {
ac6c97e2 182 viaparinfo->chip_info->lvds_chip_info.i2c_port =
f045f77b 183 VIA_PORT_2C;
ac6c97e2 184 DEBUG_MSG(KERN_INFO
277d32a3 185 "Found VIA VT1636 LVDS on port gpio 0x2c\n");
ac6c97e2
JC		 186 }
187 }
188
189 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
190 lvds_identify_integratedlvds();
191
192 if (viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
193 return true;
194 /* Check for VT1631: */
195 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name = VT1631_LVDS;
196 viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr =
197 VT1631_LVDS_I2C_ADDR;
198
199 if (check_lvds_chip(VT1631_DEVICE_ID_REG, VT1631_DEVICE_ID) != FAIL) {
200 DEBUG_MSG(KERN_INFO "\n VT1631 LVDS ! \n");
201 DEBUG_MSG(KERN_INFO "\n %2d",
202 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
203 DEBUG_MSG(KERN_INFO "\n %2d",
204 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
205 return OK;
206 }
207
208 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
209 NON_LVDS_TRANSMITTER;
210 viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr =
211 VT1631_LVDS_I2C_ADDR;
212 return FAIL;
213}
214
9b24b00c 215static void fp_id_to_vindex(int panel_id)
ac6c97e2
JC		 216{
217 DEBUG_MSG(KERN_INFO "fp_get_panel_id()\n");
218
219 if (panel_id > LCD_PANEL_ID_MAXIMUM)
220 viafb_lcd_panel_id = panel_id =
221 viafb_read_reg(VIACR, CR3F) & 0x0F;
222
223 switch (panel_id) {
224 case 0x0:
225 viaparinfo->lvds_setting_info->lcd_panel_hres = 640;
226 viaparinfo->lvds_setting_info->lcd_panel_vres = 480;
227 viaparinfo->lvds_setting_info->lcd_panel_id =
228 LCD_PANEL_ID0_640X480;
229 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
230 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 231 break;
232 case 0x1:
233 viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
234 viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
235 viaparinfo->lvds_setting_info->lcd_panel_id =
236 LCD_PANEL_ID1_800X600;
237 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
238 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 239 break;
240 case 0x2:
241 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
242 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
243 viaparinfo->lvds_setting_info->lcd_panel_id =
244 LCD_PANEL_ID2_1024X768;
245 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
246 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 247 break;
248 case 0x3:
249 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
250 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
251 viaparinfo->lvds_setting_info->lcd_panel_id =
252 LCD_PANEL_ID3_1280X768;
253 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
254 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 255 break;
256 case 0x4:
257 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
258 viaparinfo->lvds_setting_info->lcd_panel_vres = 1024;
259 viaparinfo->lvds_setting_info->lcd_panel_id =
260 LCD_PANEL_ID4_1280X1024;
261 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
262 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 263 break;
264 case 0x5:
265 viaparinfo->lvds_setting_info->lcd_panel_hres = 1400;
266 viaparinfo->lvds_setting_info->lcd_panel_vres = 1050;
267 viaparinfo->lvds_setting_info->lcd_panel_id =
268 LCD_PANEL_ID5_1400X1050;
269 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
270 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 271 break;
272 case 0x6:
273 viaparinfo->lvds_setting_info->lcd_panel_hres = 1600;
274 viaparinfo->lvds_setting_info->lcd_panel_vres = 1200;
275 viaparinfo->lvds_setting_info->lcd_panel_id =
276 LCD_PANEL_ID6_1600X1200;
277 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
278 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 279 break;
280 case 0x8:
281 viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
282 viaparinfo->lvds_setting_info->lcd_panel_vres = 480;
283 viaparinfo->lvds_setting_info->lcd_panel_id =
284 LCD_PANEL_IDA_800X480;
285 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
286 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 287 break;
288 case 0x9:
289 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
290 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
291 viaparinfo->lvds_setting_info->lcd_panel_id =
292 LCD_PANEL_ID2_1024X768;
293 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
294 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 295 break;
296 case 0xA:
297 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
298 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
299 viaparinfo->lvds_setting_info->lcd_panel_id =
300 LCD_PANEL_ID2_1024X768;
301 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
302 viaparinfo->lvds_setting_info->LCDDithering = 0;
ac6c97e2
JC		 303 break;
304 case 0xB:
305 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
306 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
307 viaparinfo->lvds_setting_info->lcd_panel_id =
308 LCD_PANEL_ID2_1024X768;
309 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
310 viaparinfo->lvds_setting_info->LCDDithering = 0;
ac6c97e2
JC		 311 break;
312 case 0xC:
313 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
314 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
315 viaparinfo->lvds_setting_info->lcd_panel_id =
316 LCD_PANEL_ID3_1280X768;
317 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
318 viaparinfo->lvds_setting_info->LCDDithering = 0;
ac6c97e2
JC		 319 break;
320 case 0xD:
321 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
322 viaparinfo->lvds_setting_info->lcd_panel_vres = 1024;
323 viaparinfo->lvds_setting_info->lcd_panel_id =
324 LCD_PANEL_ID4_1280X1024;
325 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
326 viaparinfo->lvds_setting_info->LCDDithering = 0;
ac6c97e2
JC		 327 break;
328 case 0xE:
329 viaparinfo->lvds_setting_info->lcd_panel_hres = 1400;
330 viaparinfo->lvds_setting_info->lcd_panel_vres = 1050;
331 viaparinfo->lvds_setting_info->lcd_panel_id =
332 LCD_PANEL_ID5_1400X1050;
333 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
334 viaparinfo->lvds_setting_info->LCDDithering = 0;
ac6c97e2
JC		 335 break;
336 case 0xF:
337 viaparinfo->lvds_setting_info->lcd_panel_hres = 1600;
338 viaparinfo->lvds_setting_info->lcd_panel_vres = 1200;
339 viaparinfo->lvds_setting_info->lcd_panel_id =
340 LCD_PANEL_ID6_1600X1200;
341 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
342 viaparinfo->lvds_setting_info->LCDDithering = 0;
ac6c97e2
JC		 343 break;
344 case 0x10:
345 viaparinfo->lvds_setting_info->lcd_panel_hres = 1366;
346 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
347 viaparinfo->lvds_setting_info->lcd_panel_id =
348 LCD_PANEL_ID7_1366X768;
349 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
350 viaparinfo->lvds_setting_info->LCDDithering = 0;
ac6c97e2
JC		 351 break;
352 case 0x11:
353 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
354 viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
355 viaparinfo->lvds_setting_info->lcd_panel_id =
356 LCD_PANEL_ID8_1024X600;
357 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
358 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 359 break;
360 case 0x12:
361 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
362 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
363 viaparinfo->lvds_setting_info->lcd_panel_id =
364 LCD_PANEL_ID3_1280X768;
365 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
366 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 367 break;
368 case 0x13:
369 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
370 viaparinfo->lvds_setting_info->lcd_panel_vres = 800;
371 viaparinfo->lvds_setting_info->lcd_panel_id =
372 LCD_PANEL_ID9_1280X800;
373 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
374 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 375 break;
376 case 0x14:
377 viaparinfo->lvds_setting_info->lcd_panel_hres = 1360;
378 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
379 viaparinfo->lvds_setting_info->lcd_panel_id =
380 LCD_PANEL_IDB_1360X768;
381 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
382 viaparinfo->lvds_setting_info->LCDDithering = 0;
ac6c97e2
JC		 383 break;
384 case 0x15:
385 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
386 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
387 viaparinfo->lvds_setting_info->lcd_panel_id =
388 LCD_PANEL_ID3_1280X768;
389 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
390 viaparinfo->lvds_setting_info->LCDDithering = 0;
ac6c97e2
JC		 391 break;
392 case 0x16:
393 viaparinfo->lvds_setting_info->lcd_panel_hres = 480;
394 viaparinfo->lvds_setting_info->lcd_panel_vres = 640;
395 viaparinfo->lvds_setting_info->lcd_panel_id =
396 LCD_PANEL_IDC_480X640;
397 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
398 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2 399 break;
c205d932
CB		 400 case 0x17:
401 /* OLPC XO-1.5 panel */
402 viaparinfo->lvds_setting_info->lcd_panel_hres = 1200;
403 viaparinfo->lvds_setting_info->lcd_panel_vres = 900;
404 viaparinfo->lvds_setting_info->lcd_panel_id =
405 LCD_PANEL_IDD_1200X900;
406 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
407 viaparinfo->lvds_setting_info->LCDDithering = 0;
408 break;
ac6c97e2
JC		 409 default:
410 viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
411 viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
412 viaparinfo->lvds_setting_info->lcd_panel_id =
413 LCD_PANEL_ID1_800X600;
414 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
415 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 416 }
417}
418
419static int lvds_register_read(int index)
420{
421 u8 data;
422
f045f77b 423 viafb_i2c_readbyte(VIA_PORT_2C,
277d32a3 424 (u8) viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr,
ac6c97e2
JC		 425 (u8) index, &data);
426 return data;
427}
428
429static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres,
430 int panel_vres)
431{
432 int reg_value = 0;
433 int viafb_load_reg_num;
434 struct io_register *reg = NULL;
435
436 DEBUG_MSG(KERN_INFO "load_lcd_scaling()!!\n");
437
438 /* LCD Scaling Enable */
439 viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2);
440 if (UNICHROME_P4M900 == viaparinfo->chip_info->gfx_chip_name) {
441 viafb_load_scaling_factor_for_p4m900(set_hres, set_vres,
442 panel_hres, panel_vres);
443 return;
444 }
445
446 /* Check if expansion for horizontal */
447 if (set_hres != panel_hres) {
448 /* Load Horizontal Scaling Factor */
449 switch (viaparinfo->chip_info->gfx_chip_name) {
450 case UNICHROME_CLE266:
451 case UNICHROME_K400:
452 reg_value =
453 CLE266_LCD_HOR_SCF_FORMULA(set_hres, panel_hres);
454 viafb_load_reg_num =
455 lcd_scaling_factor_CLE.lcd_hor_scaling_factor.
456 reg_num;
457 reg = lcd_scaling_factor_CLE.lcd_hor_scaling_factor.reg;
458 viafb_load_reg(reg_value,
459 viafb_load_reg_num, reg, VIACR);
460 break;
461 case UNICHROME_K800:
462 case UNICHROME_PM800:
463 case UNICHROME_CN700:
464 case UNICHROME_CX700:
465 case UNICHROME_K8M890:
466 case UNICHROME_P4M890:
467 reg_value =
468 K800_LCD_HOR_SCF_FORMULA(set_hres, panel_hres);
469 /* Horizontal scaling enabled */
470 viafb_write_reg_mask(CRA2, VIACR, 0xC0, BIT7 + BIT6);
471 viafb_load_reg_num =
472 lcd_scaling_factor.lcd_hor_scaling_factor.reg_num;
473 reg = lcd_scaling_factor.lcd_hor_scaling_factor.reg;
474 viafb_load_reg(reg_value,
475 viafb_load_reg_num, reg, VIACR);
476 break;
477 }
478
479 DEBUG_MSG(KERN_INFO "Horizontal Scaling value = %d", reg_value);
480 } else {
481 /* Horizontal scaling disabled */
482 viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT7);
483 }
484
485 /* Check if expansion for vertical */
486 if (set_vres != panel_vres) {
487 /* Load Vertical Scaling Factor */
488 switch (viaparinfo->chip_info->gfx_chip_name) {
489 case UNICHROME_CLE266:
490 case UNICHROME_K400:
491 reg_value =
492 CLE266_LCD_VER_SCF_FORMULA(set_vres, panel_vres);
493 viafb_load_reg_num =
494 lcd_scaling_factor_CLE.lcd_ver_scaling_factor.
495 reg_num;
496 reg = lcd_scaling_factor_CLE.lcd_ver_scaling_factor.reg;
497 viafb_load_reg(reg_value,
498 viafb_load_reg_num, reg, VIACR);
499 break;
500 case UNICHROME_K800:
501 case UNICHROME_PM800:
502 case UNICHROME_CN700:
503 case UNICHROME_CX700:
504 case UNICHROME_K8M890:
505 case UNICHROME_P4M890:
506 reg_value =
507 K800_LCD_VER_SCF_FORMULA(set_vres, panel_vres);
508 /* Vertical scaling enabled */
509 viafb_write_reg_mask(CRA2, VIACR, 0x08, BIT3);
510 viafb_load_reg_num =
511 lcd_scaling_factor.lcd_ver_scaling_factor.reg_num;
512 reg = lcd_scaling_factor.lcd_ver_scaling_factor.reg;
513 viafb_load_reg(reg_value,
514 viafb_load_reg_num, reg, VIACR);
515 break;
516 }
517
518 DEBUG_MSG(KERN_INFO "Vertical Scaling value = %d", reg_value);
519 } else {
520 /* Vertical scaling disabled */
521 viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT3);
522 }
523}
524
ac6c97e2
JC		 525static void via_pitch_alignment_patch_lcd(
526 struct lvds_setting_information *plvds_setting_info,
527 struct lvds_chip_information
528 *plvds_chip_info)
529{
530 unsigned char cr13, cr35, cr65, cr66, cr67;
531 unsigned long dwScreenPitch = 0;
532 unsigned long dwPitch;
533
534 dwPitch = plvds_setting_info->h_active * (plvds_setting_info->bpp >> 3);
535 if (dwPitch & 0x1F) {
536 dwScreenPitch = ((dwPitch + 31) & ~31) >> 3;
537 if (plvds_setting_info->iga_path == IGA2) {
538 if (plvds_setting_info->bpp > 8) {
539 cr66 = (unsigned char)(dwScreenPitch & 0xFF);
540 viafb_write_reg(CR66, VIACR, cr66);
541 cr67 = viafb_read_reg(VIACR, CR67) & 0xFC;
542 cr67 |=
543 (unsigned
544 char)((dwScreenPitch & 0x300) >> 8);
545 viafb_write_reg(CR67, VIACR, cr67);
546 }
547
548 /* Fetch Count */
549 cr67 = viafb_read_reg(VIACR, CR67) & 0xF3;
550 cr67 |= (unsigned char)((dwScreenPitch & 0x600) >> 7);
551 viafb_write_reg(CR67, VIACR, cr67);
552 cr65 = (unsigned char)((dwScreenPitch >> 1) & 0xFF);
553 cr65 += 2;
554 viafb_write_reg(CR65, VIACR, cr65);
555 } else {
556 if (plvds_setting_info->bpp > 8) {
557 cr13 = (unsigned char)(dwScreenPitch & 0xFF);
558 viafb_write_reg(CR13, VIACR, cr13);
559 cr35 = viafb_read_reg(VIACR, CR35) & 0x1F;
560 cr35 |=
561 (unsigned
562 char)((dwScreenPitch & 0x700) >> 3);
563 viafb_write_reg(CR35, VIACR, cr35);
564 }
565 }
566 }
567}
568static void lcd_patch_skew_dvp0(struct lvds_setting_information
569 *plvds_setting_info,
570 struct lvds_chip_information *plvds_chip_info)
571{
572 if (VT1636_LVDS == plvds_chip_info->lvds_chip_name) {
573 switch (viaparinfo->chip_info->gfx_chip_name) {
574 case UNICHROME_P4M900:
575 viafb_vt1636_patch_skew_on_vt3364(plvds_setting_info,
576 plvds_chip_info);
577 break;
578 case UNICHROME_P4M890:
579 viafb_vt1636_patch_skew_on_vt3327(plvds_setting_info,
580 plvds_chip_info);
581 break;
582 }
583 }
584}
585static void lcd_patch_skew_dvp1(struct lvds_setting_information
586 *plvds_setting_info,
587 struct lvds_chip_information *plvds_chip_info)
588{
589 if (VT1636_LVDS == plvds_chip_info->lvds_chip_name) {
590 switch (viaparinfo->chip_info->gfx_chip_name) {
591 case UNICHROME_CX700:
592 viafb_vt1636_patch_skew_on_vt3324(plvds_setting_info,
593 plvds_chip_info);
594 break;
595 }
596 }
597}
598static void lcd_patch_skew(struct lvds_setting_information
599 *plvds_setting_info, struct lvds_chip_information *plvds_chip_info)
600{
601 DEBUG_MSG(KERN_INFO "lcd_patch_skew\n");
602 switch (plvds_chip_info->output_interface) {
603 case INTERFACE_DVP0:
604 lcd_patch_skew_dvp0(plvds_setting_info, plvds_chip_info);
605 break;
606 case INTERFACE_DVP1:
607 lcd_patch_skew_dvp1(plvds_setting_info, plvds_chip_info);
608 break;
609 case INTERFACE_DFP_LOW:
610 if (UNICHROME_P4M900 == viaparinfo->chip_info->gfx_chip_name) {
611 viafb_write_reg_mask(CR99, VIACR, 0x08,
612 BIT0 + BIT1 + BIT2 + BIT3);
613 }
614 break;
615 }
616}
617
618/* LCD Set Mode */
619void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
620 struct lvds_setting_information *plvds_setting_info,
621 struct lvds_chip_information *plvds_chip_info)
622{
ac6c97e2
JC		 623 int set_iga = plvds_setting_info->iga_path;
624 int mode_bpp = plvds_setting_info->bpp;
dd73d686
FTS		 625 int set_hres = plvds_setting_info->h_active;
626 int set_vres = plvds_setting_info->v_active;
627 int panel_hres = plvds_setting_info->lcd_panel_hres;
628 int panel_vres = plvds_setting_info->lcd_panel_vres;
ac6c97e2 629 u32 pll_D_N;
ac6c97e2
JC		 630 struct display_timing mode_crt_reg, panel_crt_reg;
631 struct crt_mode_table *panel_crt_table = NULL;
dd73d686
FTS		 632 struct VideoModeTable *vmode_tbl = viafb_get_mode(panel_hres,
633 panel_vres);
ac6c97e2
JC		 634
635 DEBUG_MSG(KERN_INFO "viafb_lcd_set_mode!!\n");
636 /* Get mode table */
637 mode_crt_reg = mode_crt_table->crtc;
638 /* Get panel table Pointer */
ac6c97e2
JC		 639 panel_crt_table = vmode_tbl->crtc;
640 panel_crt_reg = panel_crt_table->crtc;
641 DEBUG_MSG(KERN_INFO "bellow viafb_lcd_set_mode!!\n");
ac6c97e2
JC		 642 if (VT1636_LVDS == plvds_chip_info->lvds_chip_name)
643 viafb_init_lvds_vt1636(plvds_setting_info, plvds_chip_info);
644 plvds_setting_info->vclk = panel_crt_table->clk;
645 if (set_iga == IGA1) {
646 /* IGA1 doesn't have LCD scaling, so set it as centering. */
647 viafb_load_crtc_timing(lcd_centering_timging
648 (mode_crt_reg, panel_crt_reg), IGA1);
649 } else {
650 /* Expansion */
651 if ((plvds_setting_info->display_method ==
652 LCD_EXPANDSION) & ((set_hres != panel_hres)
653 || (set_vres != panel_vres))) {
654 /* expansion timing IGA2 loaded panel set timing*/
655 viafb_load_crtc_timing(panel_crt_reg, IGA2);
656 DEBUG_MSG(KERN_INFO "viafb_load_crtc_timing!!\n");
657 load_lcd_scaling(set_hres, set_vres, panel_hres,
658 panel_vres);
659 DEBUG_MSG(KERN_INFO "load_lcd_scaling!!\n");
660 } else { /* Centering */
661 /* centering timing IGA2 always loaded panel
662 and mode releative timing */
663 viafb_load_crtc_timing(lcd_centering_timging
664 (mode_crt_reg, panel_crt_reg), IGA2);
665 viafb_write_reg_mask(CR79, VIACR, 0x00,
666 BIT0 + BIT1 + BIT2);
667 /* LCD scaling disabled */
668 }
669 }
670
4bbac05f
FTS		 671 /* Fetch count for IGA2 only */
672 viafb_load_fetch_count_reg(set_hres, mode_bpp / 8, set_iga);
ac6c97e2 673
4bbac05f
FTS		 674 if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
675 && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
676 viafb_load_FIFO_reg(set_iga, set_hres, set_vres);
ac6c97e2
JC		 677
678 fill_lcd_format();
679
680 pll_D_N = viafb_get_clk_value(panel_crt_table[0].clk);
681 DEBUG_MSG(KERN_INFO "PLL=0x%x", pll_D_N);
682 viafb_set_vclock(pll_D_N, set_iga);
683
684 viafb_set_output_path(DEVICE_LCD, set_iga,
685 plvds_chip_info->output_interface);
686 lcd_patch_skew(plvds_setting_info, plvds_chip_info);
687
688 /* If K8M800, enable LCD Prefetch Mode. */
689 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
690 || (UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name))
691 viafb_write_reg_mask(CR6A, VIACR, 0x01, BIT0);
692
ac6c97e2
JC		 693 /* Patch for non 32bit alignment mode */
694 via_pitch_alignment_patch_lcd(plvds_setting_info, plvds_chip_info);
695}
696
697static void integrated_lvds_disable(struct lvds_setting_information
698 *plvds_setting_info,
699 struct lvds_chip_information *plvds_chip_info)
700{
701 bool turn_off_first_powersequence = false;
702 bool turn_off_second_powersequence = false;
703 if (INTERFACE_LVDS0LVDS1 == plvds_chip_info->output_interface)
704 turn_off_first_powersequence = true;
705 if (INTERFACE_LVDS0 == plvds_chip_info->output_interface)
706 turn_off_first_powersequence = true;
707 if (INTERFACE_LVDS1 == plvds_chip_info->output_interface)
708 turn_off_second_powersequence = true;
709 if (turn_off_second_powersequence) {
710 /* Use second power sequence control: */
711
712 /* Turn off power sequence. */
713 viafb_write_reg_mask(CRD4, VIACR, 0, BIT1);
714
715 /* Turn off back light. */
716 viafb_write_reg_mask(CRD3, VIACR, 0xC0, BIT6 + BIT7);
717 }
718 if (turn_off_first_powersequence) {
719 /* Use first power sequence control: */
720
721 /* Turn off power sequence. */
722 viafb_write_reg_mask(CR6A, VIACR, 0, BIT3);
723
724 /* Turn off back light. */
725 viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7);
726 }
727
728 /* Turn DFP High/Low Pad off. */
729 viafb_write_reg_mask(SR2A, VIASR, 0, BIT0 + BIT1 + BIT2 + BIT3);
730
731 /* Power off LVDS channel. */
732 switch (plvds_chip_info->output_interface) {
733 case INTERFACE_LVDS0:
734 {
735 viafb_write_reg_mask(CRD2, VIACR, 0x80, BIT7);
736 break;
737 }
738
739 case INTERFACE_LVDS1:
740 {
741 viafb_write_reg_mask(CRD2, VIACR, 0x40, BIT6);
742 break;
743 }
744
745 case INTERFACE_LVDS0LVDS1:
746 {
747 viafb_write_reg_mask(CRD2, VIACR, 0xC0, BIT6 + BIT7);
748 break;
749 }
750 }
751}
752
753static void integrated_lvds_enable(struct lvds_setting_information
754 *plvds_setting_info,
755 struct lvds_chip_information *plvds_chip_info)
756{
ac6c97e2
JC		 757 DEBUG_MSG(KERN_INFO "integrated_lvds_enable, out_interface:%d\n",
758 plvds_chip_info->output_interface);
759 if (plvds_setting_info->lcd_mode == LCD_SPWG)
760 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1);
e6bf0d2c 761 else
ac6c97e2 762 viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1);
ac6c97e2 763
e6bf0d2c
HW		 764 switch (plvds_chip_info->output_interface) {
765 case INTERFACE_LVDS0LVDS1:
766 case INTERFACE_LVDS0:
ac6c97e2 767 /* Use first power sequence control: */
ac6c97e2
JC		 768 /* Use hardware control power sequence. */
769 viafb_write_reg_mask(CR91, VIACR, 0, BIT0);
ac6c97e2
JC		 770 /* Turn on back light. */
771 viafb_write_reg_mask(CR91, VIACR, 0, BIT6 + BIT7);
ac6c97e2
JC		 772 /* Turn on hardware power sequence. */
773 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
e6bf0d2c
HW		 774 break;
775 case INTERFACE_LVDS1:
776 /* Use second power sequence control: */
777 /* Use hardware control power sequence. */
778 viafb_write_reg_mask(CRD3, VIACR, 0, BIT0);
779 /* Turn on back light. */
780 viafb_write_reg_mask(CRD3, VIACR, 0, BIT6 + BIT7);
781 /* Turn on hardware power sequence. */
782 viafb_write_reg_mask(CRD4, VIACR, 0x02, BIT1);
783 break;
ac6c97e2
JC		 784 }
785
786 /* Turn DFP High/Low pad on. */
787 viafb_write_reg_mask(SR2A, VIASR, 0x0F, BIT0 + BIT1 + BIT2 + BIT3);
788
789 /* Power on LVDS channel. */
790 switch (plvds_chip_info->output_interface) {
791 case INTERFACE_LVDS0:
792 {
793 viafb_write_reg_mask(CRD2, VIACR, 0, BIT7);
794 break;
795 }
796
797 case INTERFACE_LVDS1:
798 {
799 viafb_write_reg_mask(CRD2, VIACR, 0, BIT6);
800 break;
801 }
802
803 case INTERFACE_LVDS0LVDS1:
804 {
805 viafb_write_reg_mask(CRD2, VIACR, 0, BIT6 + BIT7);
806 break;
807 }
808 }
809}
810
811void viafb_lcd_disable(void)
812{
813
814 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
815 lcd_powersequence_off();
816 /* DI1 pad off */
817 viafb_write_reg_mask(SR1E, VIASR, 0x00, 0x30);
818 } else if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
819 if (viafb_LCD2_ON
820 && (INTEGRATED_LVDS ==
821 viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name))
822 integrated_lvds_disable(viaparinfo->lvds_setting_info,
823 &viaparinfo->chip_info->lvds_chip_info2);
824 if (INTEGRATED_LVDS ==
825 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
826 integrated_lvds_disable(viaparinfo->lvds_setting_info,
827 &viaparinfo->chip_info->lvds_chip_info);
828 if (VT1636_LVDS == viaparinfo->chip_info->
829 lvds_chip_info.lvds_chip_name)
830 viafb_disable_lvds_vt1636(viaparinfo->lvds_setting_info,
831 &viaparinfo->chip_info->lvds_chip_info);
832 } else if (VT1636_LVDS ==
833 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
834 viafb_disable_lvds_vt1636(viaparinfo->lvds_setting_info,
835 &viaparinfo->chip_info->lvds_chip_info);
836 } else {
837 /* DFP-HL pad off */
838 viafb_write_reg_mask(SR2A, VIASR, 0x00, 0x0F);
839 /* Backlight off */
840 viafb_write_reg_mask(SR3D, VIASR, 0x00, 0x20);
841 /* 24 bit DI data paht off */
842 viafb_write_reg_mask(CR91, VIACR, 0x80, 0x80);
843 /* Simultaneout disabled */
844 viafb_write_reg_mask(CR6B, VIACR, 0x00, 0x08);
845 }
846
847 /* Disable expansion bit */
848 viafb_write_reg_mask(CR79, VIACR, 0x00, 0x01);
849 /* CRT path set to IGA1 */
850 viafb_write_reg_mask(SR16, VIASR, 0x00, 0x40);
851 /* Simultaneout disabled */
852 viafb_write_reg_mask(CR6B, VIACR, 0x00, 0x08);
853 /* IGA2 path disabled */
854 viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x80);
855
856}
857
858void viafb_lcd_enable(void)
859{
860 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
861 /* DI1 pad on */
862 viafb_write_reg_mask(SR1E, VIASR, 0x30, 0x30);
863 lcd_powersequence_on();
864 } else if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
865 if (viafb_LCD2_ON && (INTEGRATED_LVDS ==
866 viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name))
867 integrated_lvds_enable(viaparinfo->lvds_setting_info2, \
868 &viaparinfo->chip_info->lvds_chip_info2);
869 if (INTEGRATED_LVDS ==
870 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
871 integrated_lvds_enable(viaparinfo->lvds_setting_info,
872 &viaparinfo->chip_info->lvds_chip_info);
873 if (VT1636_LVDS == viaparinfo->chip_info->
874 lvds_chip_info.lvds_chip_name)
875 viafb_enable_lvds_vt1636(viaparinfo->
876 lvds_setting_info, &viaparinfo->chip_info->
877 lvds_chip_info);
878 } else if (VT1636_LVDS ==
879 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
880 viafb_enable_lvds_vt1636(viaparinfo->lvds_setting_info,
881 &viaparinfo->chip_info->lvds_chip_info);
882 } else {
883 /* DFP-HL pad on */
884 viafb_write_reg_mask(SR2A, VIASR, 0x0F, 0x0F);
885 /* Backlight on */
886 viafb_write_reg_mask(SR3D, VIASR, 0x20, 0x20);
887 /* 24 bit DI data paht on */
888 viafb_write_reg_mask(CR91, VIACR, 0x00, 0x80);
889
890 /* Set data source selection bit by iga path */
891 if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
892 /* DFP-H set to IGA1 */
893 viafb_write_reg_mask(CR97, VIACR, 0x00, 0x10);
894 /* DFP-L set to IGA1 */
895 viafb_write_reg_mask(CR99, VIACR, 0x00, 0x10);
896 } else {
897 /* DFP-H set to IGA2 */
898 viafb_write_reg_mask(CR97, VIACR, 0x10, 0x10);
899 /* DFP-L set to IGA2 */
900 viafb_write_reg_mask(CR99, VIACR, 0x10, 0x10);
901 }
902 /* LCD enabled */
903 viafb_write_reg_mask(CR6A, VIACR, 0x48, 0x48);
904 }
905
4bbac05f 906 if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
ac6c97e2
JC		 907 /* CRT path set to IGA2 */
908 viafb_write_reg_mask(SR16, VIASR, 0x40, 0x40);
909 /* IGA2 path disabled */
910 viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x80);
911 /* IGA2 path enabled */
912 } else { /* IGA2 */
913 viafb_write_reg_mask(CR6A, VIACR, 0x80, 0x80);
914 }
915
916}
917
918static void lcd_powersequence_off(void)
919{
920 int i, mask, data;
921
922 /* Software control power sequence */
923 viafb_write_reg_mask(CR91, VIACR, 0x11, 0x11);
924
925 for (i = 0; i < 3; i++) {
926 mask = PowerSequenceOff[0][i];
927 data = PowerSequenceOff[1][i] & mask;
928 viafb_write_reg_mask(CR91, VIACR, (u8) data, (u8) mask);
929 udelay(PowerSequenceOff[2][i]);
930 }
931
932 /* Disable LCD */
933 viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x08);
934}
935
936static void lcd_powersequence_on(void)
937{
938 int i, mask, data;
939
940 /* Software control power sequence */
941 viafb_write_reg_mask(CR91, VIACR, 0x11, 0x11);
942
943 /* Enable LCD */
944 viafb_write_reg_mask(CR6A, VIACR, 0x08, 0x08);
945
946 for (i = 0; i < 3; i++) {
947 mask = PowerSequenceOn[0][i];
948 data = PowerSequenceOn[1][i] & mask;
949 viafb_write_reg_mask(CR91, VIACR, (u8) data, (u8) mask);
950 udelay(PowerSequenceOn[2][i]);
951 }
952
953 udelay(1);
954}
955
956static void fill_lcd_format(void)
957{
958 u8 bdithering = 0, bdual = 0;
959
960 if (viaparinfo->lvds_setting_info->device_lcd_dualedge)
961 bdual = BIT4;
962 if (viaparinfo->lvds_setting_info->LCDDithering)
963 bdithering = BIT0;
964 /* Dual & Dithering */
965 viafb_write_reg_mask(CR88, VIACR, (bdithering | bdual), BIT4 + BIT0);
966}
967
968static void check_diport_of_integrated_lvds(
969 struct lvds_chip_information *plvds_chip_info,
970 struct lvds_setting_information
971 *plvds_setting_info)
972{
973 /* Determine LCD DI Port by hardware layout. */
974 switch (viafb_display_hardware_layout) {
975 case HW_LAYOUT_LCD_ONLY:
976 {
977 if (plvds_setting_info->device_lcd_dualedge) {
978 plvds_chip_info->output_interface =
979 INTERFACE_LVDS0LVDS1;
980 } else {
981 plvds_chip_info->output_interface =
982 INTERFACE_LVDS0;
983 }
984
985 break;
986 }
987
988 case HW_LAYOUT_DVI_ONLY:
989 {
990 plvds_chip_info->output_interface = INTERFACE_NONE;
991 break;
992 }
993
994 case HW_LAYOUT_LCD1_LCD2:
995 case HW_LAYOUT_LCD_EXTERNAL_LCD2:
996 {
997 plvds_chip_info->output_interface =
998 INTERFACE_LVDS0LVDS1;
999 break;
1000 }
1001
1002 case HW_LAYOUT_LCD_DVI:
1003 {
1004 plvds_chip_info->output_interface = INTERFACE_LVDS1;
1005 break;
1006 }
1007
1008 default:
1009 {
1010 plvds_chip_info->output_interface = INTERFACE_LVDS1;
1011 break;
1012 }
1013 }
1014
1015 DEBUG_MSG(KERN_INFO
1016 "Display Hardware Layout: 0x%x, LCD DI Port: 0x%x\n",
1017 viafb_display_hardware_layout,
1018 plvds_chip_info->output_interface);
1019}
1020
1021void viafb_init_lvds_output_interface(struct lvds_chip_information
1022 *plvds_chip_info,
1023 struct lvds_setting_information
1024 *plvds_setting_info)
1025{
1026 if (INTERFACE_NONE != plvds_chip_info->output_interface) {
1027 /*Do nothing, lcd port is specified by module parameter */
1028 return;
1029 }
1030
1031 switch (plvds_chip_info->lvds_chip_name) {
1032
1033 case VT1636_LVDS:
1034 switch (viaparinfo->chip_info->gfx_chip_name) {
1035 case UNICHROME_CX700:
1036 plvds_chip_info->output_interface = INTERFACE_DVP1;
1037 break;
1038 case UNICHROME_CN700:
1039 plvds_chip_info->output_interface = INTERFACE_DFP_LOW;
1040 break;
1041 default:
1042 plvds_chip_info->output_interface = INTERFACE_DVP0;
1043 break;
1044 }
1045 break;
1046
1047 case INTEGRATED_LVDS:
1048 check_diport_of_integrated_lvds(plvds_chip_info,
1049 plvds_setting_info);
1050 break;
1051
1052 default:
1053 switch (viaparinfo->chip_info->gfx_chip_name) {
1054 case UNICHROME_K8M890:
1055 case UNICHROME_P4M900:
1056 case UNICHROME_P4M890:
1057 plvds_chip_info->output_interface = INTERFACE_DFP_LOW;
1058 break;
1059 default:
1060 plvds_chip_info->output_interface = INTERFACE_DFP;
1061 break;
1062 }
1063 break;
1064 }
1065}
1066
1067static struct display_timing lcd_centering_timging(struct display_timing
1068 mode_crt_reg,
1069 struct display_timing panel_crt_reg)
1070{
1071 struct display_timing crt_reg;
1072
1073 crt_reg.hor_total = panel_crt_reg.hor_total;
1074 crt_reg.hor_addr = mode_crt_reg.hor_addr;
1075 crt_reg.hor_blank_start =
1076 (panel_crt_reg.hor_addr - mode_crt_reg.hor_addr) / 2 +
1077 crt_reg.hor_addr;
1078 crt_reg.hor_blank_end = panel_crt_reg.hor_blank_end;
1079 crt_reg.hor_sync_start =
1080 (panel_crt_reg.hor_sync_start -
1081 panel_crt_reg.hor_blank_start) + crt_reg.hor_blank_start;
1082 crt_reg.hor_sync_end = panel_crt_reg.hor_sync_end;
1083
1084 crt_reg.ver_total = panel_crt_reg.ver_total;
1085 crt_reg.ver_addr = mode_crt_reg.ver_addr;
1086 crt_reg.ver_blank_start =
1087 (panel_crt_reg.ver_addr - mode_crt_reg.ver_addr) / 2 +
1088 crt_reg.ver_addr;
1089 crt_reg.ver_blank_end = panel_crt_reg.ver_blank_end;
1090 crt_reg.ver_sync_start =
1091 (panel_crt_reg.ver_sync_start -
1092 panel_crt_reg.ver_blank_start) + crt_reg.ver_blank_start;
1093 crt_reg.ver_sync_end = panel_crt_reg.ver_sync_end;
1094
1095 return crt_reg;
1096}
1097
ac6c97e2
JC		 1098bool viafb_lcd_get_mobile_state(bool *mobile)
1099{
1100 unsigned char *romptr, *tableptr;
1101 u8 core_base;
1102 unsigned char *biosptr;
1103 /* Rom address */
1104 u32 romaddr = 0x000C0000;
1105 u16 start_pattern = 0;
1106
1107 biosptr = ioremap(romaddr, 0x10000);
1108
1109 memcpy(&start_pattern, biosptr, 2);
1110 /* Compare pattern */
1111 if (start_pattern == 0xAA55) {
1112 /* Get the start of Table */
1113 /* 0x1B means BIOS offset position */
1114 romptr = biosptr + 0x1B;
1115 tableptr = biosptr + *((u16 *) romptr);
1116
1117 /* Get the start of biosver structure */
1118 /* 18 means BIOS version position. */
1119 romptr = tableptr + 18;
1120 romptr = biosptr + *((u16 *) romptr);
1121
1122 /* The offset should be 44, but the
1123 actual image is less three char. */
1124 /* pRom += 44; */
1125 romptr += 41;
1126
1127 core_base = *romptr++;
1128
1129 if (core_base & 0x8)
1130 *mobile = false;
1131 else
1132 *mobile = true;
1133 /* release memory */
1134 iounmap(biosptr);
1135
1136 return true;
1137 } else {
1138 iounmap(biosptr);
1139 return false;
1140 }
1141}
1142
1143static void viafb_load_scaling_factor_for_p4m900(int set_hres,
1144 int set_vres, int panel_hres, int panel_vres)
1145{
1146 int h_scaling_factor;
1147 int v_scaling_factor;
1148 u8 cra2 = 0;
1149 u8 cr77 = 0;
1150 u8 cr78 = 0;
1151 u8 cr79 = 0;
1152 u8 cr9f = 0;
1153 /* Check if expansion for horizontal */
1154 if (set_hres < panel_hres) {
1155 /* Load Horizontal Scaling Factor */
1156
1157 /* For VIA_K8M800 or later chipsets. */
1158 h_scaling_factor =
1159 K800_LCD_HOR_SCF_FORMULA(set_hres, panel_hres);
1160 /* HSCaleFactor[1:0] at CR9F[1:0] */
1161 cr9f = h_scaling_factor & 0x0003;
1162 /* HSCaleFactor[9:2] at CR77[7:0] */
1163 cr77 = (h_scaling_factor & 0x03FC) >> 2;
1164 /* HSCaleFactor[11:10] at CR79[5:4] */
1165 cr79 = (h_scaling_factor & 0x0C00) >> 10;
1166 cr79 <<= 4;
1167
1168 /* Horizontal scaling enabled */
1169 cra2 = 0xC0;
1170
1171 DEBUG_MSG(KERN_INFO "Horizontal Scaling value = %d\n",
1172 h_scaling_factor);
1173 } else {
1174 /* Horizontal scaling disabled */
1175 cra2 = 0x00;
1176 }
1177
1178 /* Check if expansion for vertical */
1179 if (set_vres < panel_vres) {
1180 /* Load Vertical Scaling Factor */
1181
1182 /* For VIA_K8M800 or later chipsets. */
1183 v_scaling_factor =
1184 K800_LCD_VER_SCF_FORMULA(set_vres, panel_vres);
1185
1186 /* Vertical scaling enabled */
1187 cra2 |= 0x08;
1188 /* VSCaleFactor[0] at CR79[3] */
1189 cr79 |= ((v_scaling_factor & 0x0001) << 3);
1190 /* VSCaleFactor[8:1] at CR78[7:0] */
1191 cr78 |= (v_scaling_factor & 0x01FE) >> 1;
1192 /* VSCaleFactor[10:9] at CR79[7:6] */
1193 cr79 |= ((v_scaling_factor & 0x0600) >> 9) << 6;
1194
1195 DEBUG_MSG(KERN_INFO "Vertical Scaling value = %d\n",
1196 v_scaling_factor);
1197 } else {
1198 /* Vertical scaling disabled */
1199 cra2 |= 0x00;
1200 }
1201
1202 viafb_write_reg_mask(CRA2, VIACR, cra2, BIT3 + BIT6 + BIT7);
1203 viafb_write_reg_mask(CR77, VIACR, cr77, 0xFF);
1204 viafb_write_reg_mask(CR78, VIACR, cr78, 0xFF);
1205 viafb_write_reg_mask(CR79, VIACR, cr79, 0xF8);
1206 viafb_write_reg_mask(CR9F, VIACR, cr9f, BIT0 + BIT1);
1207}
Linux kernel - Deliverables
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