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37773cf5 JC |
1 | /* |
2 | * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved. | |
3 | * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved. | |
4 | ||
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public | |
7 | * License as published by the Free Software Foundation; | |
8 | * either version 2, or (at your option) any later version. | |
9 | ||
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even | |
12 | * the implied warranty of MERCHANTABILITY or FITNESS FOR | |
13 | * A PARTICULAR PURPOSE.See the GNU General Public License | |
14 | * for more details. | |
15 | ||
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., | |
19 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
20 | */ | |
21 | ||
22 | #ifndef __SHARE_H__ | |
23 | #define __SHARE_H__ | |
24 | ||
d60defb7 FTS |
25 | #include "via_modesetting.h" |
26 | ||
37773cf5 JC |
27 | /* Define Bit Field */ |
28 | #define BIT0 0x01 | |
29 | #define BIT1 0x02 | |
30 | #define BIT2 0x04 | |
31 | #define BIT3 0x08 | |
32 | #define BIT4 0x10 | |
33 | #define BIT5 0x20 | |
34 | #define BIT6 0x40 | |
35 | #define BIT7 0x80 | |
36 | ||
37 | /* Video Memory Size */ | |
38 | #define VIDEO_MEMORY_SIZE_16M 0x1000000 | |
39 | ||
64a6bd6a JC |
40 | /* |
41 | * Lengths of the VPIT structure arrays. | |
42 | */ | |
37773cf5 JC |
43 | #define StdCR 0x19 |
44 | #define StdSR 0x04 | |
45 | #define StdGR 0x09 | |
46 | #define StdAR 0x14 | |
47 | ||
48 | #define PatchCR 11 | |
49 | ||
50 | /* Display path */ | |
51 | #define IGA1 1 | |
52 | #define IGA2 2 | |
37773cf5 JC |
53 | |
54 | /* Define Color Depth */ | |
55 | #define MODE_8BPP 1 | |
56 | #define MODE_16BPP 2 | |
57 | #define MODE_32BPP 4 | |
58 | ||
59 | #define GR20 0x20 | |
60 | #define GR21 0x21 | |
61 | #define GR22 0x22 | |
62 | ||
63 | /* Sequencer Registers */ | |
64 | #define SR01 0x01 | |
65 | #define SR10 0x10 | |
66 | #define SR12 0x12 | |
67 | #define SR15 0x15 | |
68 | #define SR16 0x16 | |
69 | #define SR17 0x17 | |
70 | #define SR18 0x18 | |
71 | #define SR1B 0x1B | |
72 | #define SR1A 0x1A | |
73 | #define SR1C 0x1C | |
74 | #define SR1D 0x1D | |
75 | #define SR1E 0x1E | |
76 | #define SR1F 0x1F | |
77 | #define SR20 0x20 | |
78 | #define SR21 0x21 | |
79 | #define SR22 0x22 | |
80 | #define SR2A 0x2A | |
81 | #define SR2D 0x2D | |
82 | #define SR2E 0x2E | |
83 | ||
84 | #define SR30 0x30 | |
85 | #define SR39 0x39 | |
86 | #define SR3D 0x3D | |
87 | #define SR3E 0x3E | |
88 | #define SR3F 0x3F | |
89 | #define SR40 0x40 | |
90 | #define SR43 0x43 | |
91 | #define SR44 0x44 | |
92 | #define SR45 0x45 | |
93 | #define SR46 0x46 | |
94 | #define SR47 0x47 | |
95 | #define SR48 0x48 | |
96 | #define SR49 0x49 | |
97 | #define SR4A 0x4A | |
98 | #define SR4B 0x4B | |
99 | #define SR4C 0x4C | |
100 | #define SR52 0x52 | |
0306ab11 HW |
101 | #define SR57 0x57 |
102 | #define SR58 0x58 | |
103 | #define SR59 0x59 | |
104 | #define SR5D 0x5D | |
37773cf5 JC |
105 | #define SR5E 0x5E |
106 | #define SR65 0x65 | |
107 | ||
108 | /* CRT Controller Registers */ | |
109 | #define CR00 0x00 | |
110 | #define CR01 0x01 | |
111 | #define CR02 0x02 | |
112 | #define CR03 0x03 | |
113 | #define CR04 0x04 | |
114 | #define CR05 0x05 | |
115 | #define CR06 0x06 | |
116 | #define CR07 0x07 | |
117 | #define CR08 0x08 | |
118 | #define CR09 0x09 | |
119 | #define CR0A 0x0A | |
120 | #define CR0B 0x0B | |
121 | #define CR0C 0x0C | |
122 | #define CR0D 0x0D | |
123 | #define CR0E 0x0E | |
124 | #define CR0F 0x0F | |
125 | #define CR10 0x10 | |
126 | #define CR11 0x11 | |
127 | #define CR12 0x12 | |
128 | #define CR13 0x13 | |
129 | #define CR14 0x14 | |
130 | #define CR15 0x15 | |
131 | #define CR16 0x16 | |
132 | #define CR17 0x17 | |
133 | #define CR18 0x18 | |
134 | ||
135 | /* Extend CRT Controller Registers */ | |
136 | #define CR30 0x30 | |
137 | #define CR31 0x31 | |
138 | #define CR32 0x32 | |
139 | #define CR33 0x33 | |
140 | #define CR34 0x34 | |
141 | #define CR35 0x35 | |
142 | #define CR36 0x36 | |
143 | #define CR37 0x37 | |
144 | #define CR38 0x38 | |
145 | #define CR39 0x39 | |
146 | #define CR3A 0x3A | |
147 | #define CR3B 0x3B | |
148 | #define CR3C 0x3C | |
149 | #define CR3D 0x3D | |
150 | #define CR3E 0x3E | |
151 | #define CR3F 0x3F | |
152 | #define CR40 0x40 | |
153 | #define CR41 0x41 | |
154 | #define CR42 0x42 | |
155 | #define CR43 0x43 | |
156 | #define CR44 0x44 | |
157 | #define CR45 0x45 | |
158 | #define CR46 0x46 | |
159 | #define CR47 0x47 | |
160 | #define CR48 0x48 | |
161 | #define CR49 0x49 | |
162 | #define CR4A 0x4A | |
163 | #define CR4B 0x4B | |
164 | #define CR4C 0x4C | |
165 | #define CR4D 0x4D | |
166 | #define CR4E 0x4E | |
167 | #define CR4F 0x4F | |
168 | #define CR50 0x50 | |
169 | #define CR51 0x51 | |
170 | #define CR52 0x52 | |
171 | #define CR53 0x53 | |
172 | #define CR54 0x54 | |
173 | #define CR55 0x55 | |
174 | #define CR56 0x56 | |
175 | #define CR57 0x57 | |
176 | #define CR58 0x58 | |
177 | #define CR59 0x59 | |
178 | #define CR5A 0x5A | |
179 | #define CR5B 0x5B | |
180 | #define CR5C 0x5C | |
181 | #define CR5D 0x5D | |
182 | #define CR5E 0x5E | |
183 | #define CR5F 0x5F | |
184 | #define CR60 0x60 | |
185 | #define CR61 0x61 | |
186 | #define CR62 0x62 | |
187 | #define CR63 0x63 | |
188 | #define CR64 0x64 | |
189 | #define CR65 0x65 | |
190 | #define CR66 0x66 | |
191 | #define CR67 0x67 | |
192 | #define CR68 0x68 | |
193 | #define CR69 0x69 | |
194 | #define CR6A 0x6A | |
195 | #define CR6B 0x6B | |
196 | #define CR6C 0x6C | |
197 | #define CR6D 0x6D | |
198 | #define CR6E 0x6E | |
199 | #define CR6F 0x6F | |
200 | #define CR70 0x70 | |
201 | #define CR71 0x71 | |
202 | #define CR72 0x72 | |
203 | #define CR73 0x73 | |
204 | #define CR74 0x74 | |
205 | #define CR75 0x75 | |
206 | #define CR76 0x76 | |
207 | #define CR77 0x77 | |
208 | #define CR78 0x78 | |
209 | #define CR79 0x79 | |
210 | #define CR7A 0x7A | |
211 | #define CR7B 0x7B | |
212 | #define CR7C 0x7C | |
213 | #define CR7D 0x7D | |
214 | #define CR7E 0x7E | |
215 | #define CR7F 0x7F | |
216 | #define CR80 0x80 | |
217 | #define CR81 0x81 | |
218 | #define CR82 0x82 | |
219 | #define CR83 0x83 | |
220 | #define CR84 0x84 | |
221 | #define CR85 0x85 | |
222 | #define CR86 0x86 | |
223 | #define CR87 0x87 | |
224 | #define CR88 0x88 | |
225 | #define CR89 0x89 | |
226 | #define CR8A 0x8A | |
227 | #define CR8B 0x8B | |
228 | #define CR8C 0x8C | |
229 | #define CR8D 0x8D | |
230 | #define CR8E 0x8E | |
231 | #define CR8F 0x8F | |
232 | #define CR90 0x90 | |
233 | #define CR91 0x91 | |
234 | #define CR92 0x92 | |
235 | #define CR93 0x93 | |
236 | #define CR94 0x94 | |
237 | #define CR95 0x95 | |
238 | #define CR96 0x96 | |
239 | #define CR97 0x97 | |
240 | #define CR98 0x98 | |
241 | #define CR99 0x99 | |
242 | #define CR9A 0x9A | |
243 | #define CR9B 0x9B | |
244 | #define CR9C 0x9C | |
245 | #define CR9D 0x9D | |
246 | #define CR9E 0x9E | |
247 | #define CR9F 0x9F | |
248 | #define CRA0 0xA0 | |
249 | #define CRA1 0xA1 | |
250 | #define CRA2 0xA2 | |
251 | #define CRA3 0xA3 | |
252 | #define CRD2 0xD2 | |
253 | #define CRD3 0xD3 | |
254 | #define CRD4 0xD4 | |
255 | ||
256 | /* LUT Table*/ | |
257 | #define LUT_DATA 0x3C9 /* DACDATA */ | |
258 | #define LUT_INDEX_READ 0x3C7 /* DACRX */ | |
259 | #define LUT_INDEX_WRITE 0x3C8 /* DACWX */ | |
260 | #define DACMASK 0x3C6 | |
261 | ||
262 | /* Definition Device */ | |
263 | #define DEVICE_CRT 0x01 | |
264 | #define DEVICE_DVI 0x03 | |
265 | #define DEVICE_LCD 0x04 | |
266 | ||
267 | /* Device output interface */ | |
268 | #define INTERFACE_NONE 0x00 | |
269 | #define INTERFACE_ANALOG_RGB 0x01 | |
270 | #define INTERFACE_DVP0 0x02 | |
271 | #define INTERFACE_DVP1 0x03 | |
272 | #define INTERFACE_DFP_HIGH 0x04 | |
273 | #define INTERFACE_DFP_LOW 0x05 | |
274 | #define INTERFACE_DFP 0x06 | |
275 | #define INTERFACE_LVDS0 0x07 | |
276 | #define INTERFACE_LVDS1 0x08 | |
277 | #define INTERFACE_LVDS0LVDS1 0x09 | |
278 | #define INTERFACE_TMDS 0x0A | |
279 | ||
280 | #define HW_LAYOUT_LCD_ONLY 0x01 | |
281 | #define HW_LAYOUT_DVI_ONLY 0x02 | |
282 | #define HW_LAYOUT_LCD_DVI 0x03 | |
283 | #define HW_LAYOUT_LCD1_LCD2 0x04 | |
284 | #define HW_LAYOUT_LCD_EXTERNAL_LCD2 0x10 | |
285 | ||
37773cf5 JC |
286 | /* Definition CRTC Timing Index */ |
287 | #define H_TOTAL_INDEX 0 | |
288 | #define H_ADDR_INDEX 1 | |
289 | #define H_BLANK_START_INDEX 2 | |
290 | #define H_BLANK_END_INDEX 3 | |
291 | #define H_SYNC_START_INDEX 4 | |
292 | #define H_SYNC_END_INDEX 5 | |
293 | #define V_TOTAL_INDEX 6 | |
294 | #define V_ADDR_INDEX 7 | |
295 | #define V_BLANK_START_INDEX 8 | |
296 | #define V_BLANK_END_INDEX 9 | |
297 | #define V_SYNC_START_INDEX 10 | |
298 | #define V_SYNC_END_INDEX 11 | |
299 | #define H_TOTAL_SHADOW_INDEX 12 | |
300 | #define H_BLANK_END_SHADOW_INDEX 13 | |
301 | #define V_TOTAL_SHADOW_INDEX 14 | |
302 | #define V_ADDR_SHADOW_INDEX 15 | |
303 | #define V_BLANK_SATRT_SHADOW_INDEX 16 | |
304 | #define V_BLANK_END_SHADOW_INDEX 17 | |
305 | #define V_SYNC_SATRT_SHADOW_INDEX 18 | |
306 | #define V_SYNC_END_SHADOW_INDEX 19 | |
307 | ||
37773cf5 JC |
308 | /* LCD display method |
309 | */ | |
310 | #define LCD_EXPANDSION 0x00 | |
311 | #define LCD_CENTERING 0x01 | |
312 | ||
313 | /* LCD mode | |
314 | */ | |
315 | #define LCD_OPENLDI 0x00 | |
316 | #define LCD_SPWG 0x01 | |
317 | ||
37773cf5 JC |
318 | struct crt_mode_table { |
319 | int refresh_rate; | |
37773cf5 JC |
320 | int h_sync_polarity; |
321 | int v_sync_polarity; | |
ea4f3111 | 322 | struct via_display_timing crtc; |
37773cf5 JC |
323 | }; |
324 | ||
325 | struct io_reg { | |
326 | int port; | |
327 | u8 index; | |
328 | u8 mask; | |
329 | u8 value; | |
330 | }; | |
331 | ||
332 | #endif /* __SHARE_H__ */ |