projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| d42823ef JC |
1 | /* |
| 2 | * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved. | |
| 3 | * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved. | |
| 4 | ||
| 5 | * This program is free software; you can redistribute it and/or | |
| 6 | * modify it under the terms of the GNU General Public | |
| 7 | * License as published by the Free Software Foundation; | |
| 8 | * either version 2, or (at your option) any later version. | |
| 9 | ||
| 10 | * This program is distributed in the hope that it will be useful, | |
| 11 | * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even | |
| 12 | * the implied warranty of MERCHANTABILITY or FITNESS FOR | |
| 13 | * A PARTICULAR PURPOSE.See the GNU General Public License | |
| 14 | * for more details. | |
| 15 | ||
| 16 | * You should have received a copy of the GNU General Public License | |
| 17 | * along with this program; if not, write to the Free Software | |
| 18 | * Foundation, Inc., | |
| 19 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
| 20 | */ | |
| 21 | ||
| 22 | #include "global.h" | |
| d42823ef JC |
23 | |
| 24 | struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3324[] = { | |
| 25 | /* ClkRange, DVP0, DVP0DataDriving, DVP0ClockDriving, DVP1, | |
| 26 | DVP1Driving, DFPHigh, DFPLow */ | |
| 27 | /* CR96, SR2A[5], SR1B[1], SR2A[4], SR1E[2], CR9B, | |
| 28 | SR65, CR97, CR99 */ | |
| 29 | /* LCK/VCK < 30000000 will use this value */ | |
| 30 | {DPA_CLK_RANGE_30M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, | |
| 31 | 0x00}, | |
| 32 | /* 30000000 < LCK/VCK < 50000000 will use this value */ | |
| 33 | {DPA_CLK_RANGE_30_50M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, | |
| 34 | 0x00}, | |
| 35 | /* 50000000 < LCK/VCK < 70000000 will use this value */ | |
| 36 | {DPA_CLK_RANGE_50_70M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, | |
| 37 | 0x00}, | |
| 38 | /* 70000000 < LCK/VCK < 100000000 will use this value */ | |
| 39 | {DPA_CLK_RANGE_70_100M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, | |
| 40 | 0x00}, | |
| 41 | /* 100000000 < LCK/VCK < 15000000 will use this value */ | |
| 42 | {DPA_CLK_RANGE_100_150M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, | |
| 43 | 0x00}, | |
| 44 | /* 15000000 < LCK/VCK will use this value */ | |
| 45 | {DPA_CLK_RANGE_150M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x0E, 0x00, | |
| 46 | 0x00}, | |
| 47 | }; | |
| 48 | ||
| d42823ef JC |
49 | struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3327[] = { |
| 50 | /* ClkRange,DVP0, DVP0DataDriving, DVP0ClockDriving, DVP1, | |
| 51 | DVP1Driving, DFPHigh, DFPLow */ | |
| 52 | /* CR96, SR2A[5], SR1B[1], SR2A[4], SR1E[2], CR9B, | |
| 53 | SR65, CR97, CR99 */ | |
| 54 | /* LCK/VCK < 30000000 will use this value */ | |
| 55 | {DPA_CLK_RANGE_30M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x08, 0x01}, | |
| 56 | /* 30000000 < LCK/VCK < 50000000 will use this value */ | |
| 57 | {DPA_CLK_RANGE_30_50M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x08, 0x01}, | |
| 58 | /* 50000000 < LCK/VCK < 70000000 will use this value */ | |
| 59 | {DPA_CLK_RANGE_50_70M, 0x06, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x08, 0x01}, | |
| 60 | /* 70000000 < LCK/VCK < 100000000 will use this value */ | |
| 61 | {DPA_CLK_RANGE_70_100M, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x08, 0x03}, | |
| 62 | /* 100000000 < LCK/VCK < 15000000 will use this value */ | |
| 63 | {DPA_CLK_RANGE_100_150M, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x01, 0x02}, | |
| 64 | /* 15000000 < LCK/VCK will use this value */ | |
| 65 | {DPA_CLK_RANGE_150M, 0x00, 0x20, 0x00, 0x10, 0x00, 0x03, 0x00, 0x0D, 0x03}, | |
| 66 | }; | |
| 67 | ||
| 68 | /* For VT3364: */ | |
| 69 | struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3364[] = { | |
| 70 | /* ClkRange,DVP0, DVP0DataDriving, DVP0ClockDriving, DVP1, | |
| 71 | DVP1Driving, DFPHigh, DFPLow */ | |
| 72 | /* CR96, SR2A[5], SR1B[1], SR2A[4], SR1E[2], CR9B, | |
| 73 | SR65, CR97, CR99 */ | |
| 74 | /* LCK/VCK < 30000000 will use this value */ | |
| 75 | {DPA_CLK_RANGE_30M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08}, | |
| 76 | /* 30000000 < LCK/VCK < 50000000 will use this value */ | |
| 77 | {DPA_CLK_RANGE_30_50M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08}, | |
| 78 | /* 50000000 < LCK/VCK < 70000000 will use this value */ | |
| 79 | {DPA_CLK_RANGE_50_70M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08}, | |
| 80 | /* 70000000 < LCK/VCK < 100000000 will use this value */ | |
| 81 | {DPA_CLK_RANGE_70_100M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08}, | |
| 82 | /* 100000000 < LCK/VCK < 15000000 will use this value */ | |
| 83 | {DPA_CLK_RANGE_100_150M, 0x03, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08}, | |
| 84 | /* 15000000 < LCK/VCK will use this value */ | |
| 85 | {DPA_CLK_RANGE_150M, 0x01, 0x00, 0x02, 0x10, 0x00, 0x03, 0x00, 0x00, 0x08}, | |
| 86 | }; |