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100e74a1 FTS |
1 | /* |
2 | * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved. | |
3 | * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved. | |
4 | * Copyright 2010 Florian Tobias Schandinat <FlorianSchandinat@gmx.de> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public | |
8 | * License as published by the Free Software Foundation; | |
9 | * either version 2, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even | |
13 | * the implied warranty of MERCHANTABILITY or FITNESS FOR | |
14 | * A PARTICULAR PURPOSE.See the GNU General Public License | |
15 | * for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., | |
20 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
21 | */ | |
22 | /* | |
23 | * basic modesetting functions | |
24 | */ | |
25 | ||
26 | #include <linux/kernel.h> | |
ec66841e | 27 | #include <linux/via-core.h> |
100e74a1 | 28 | #include "via_modesetting.h" |
100e74a1 FTS |
29 | #include "share.h" |
30 | #include "debug.h" | |
31 | ||
d60defb7 | 32 | |
ea4f3111 | 33 | void via_set_primary_timing(const struct via_display_timing *timing) |
d60defb7 | 34 | { |
ea4f3111 | 35 | struct via_display_timing raw; |
d60defb7 FTS |
36 | |
37 | raw.hor_total = timing->hor_total / 8 - 5; | |
38 | raw.hor_addr = timing->hor_addr / 8 - 1; | |
39 | raw.hor_blank_start = timing->hor_blank_start / 8 - 1; | |
40 | raw.hor_blank_end = timing->hor_blank_end / 8 - 1; | |
41 | raw.hor_sync_start = timing->hor_sync_start / 8; | |
42 | raw.hor_sync_end = timing->hor_sync_end / 8; | |
43 | raw.ver_total = timing->ver_total - 2; | |
44 | raw.ver_addr = timing->ver_addr - 1; | |
45 | raw.ver_blank_start = timing->ver_blank_start - 1; | |
46 | raw.ver_blank_end = timing->ver_blank_end - 1; | |
47 | raw.ver_sync_start = timing->ver_sync_start - 1; | |
48 | raw.ver_sync_end = timing->ver_sync_end - 1; | |
49 | ||
50 | /* unlock timing registers */ | |
51 | via_write_reg_mask(VIACR, 0x11, 0x00, 0x80); | |
52 | ||
53 | via_write_reg(VIACR, 0x00, raw.hor_total & 0xFF); | |
54 | via_write_reg(VIACR, 0x01, raw.hor_addr & 0xFF); | |
55 | via_write_reg(VIACR, 0x02, raw.hor_blank_start & 0xFF); | |
56 | via_write_reg_mask(VIACR, 0x03, raw.hor_blank_end & 0x1F, 0x1F); | |
57 | via_write_reg(VIACR, 0x04, raw.hor_sync_start & 0xFF); | |
58 | via_write_reg_mask(VIACR, 0x05, (raw.hor_sync_end & 0x1F) | |
59 | | (raw.hor_blank_end << (7 - 5) & 0x80), 0x9F); | |
60 | via_write_reg(VIACR, 0x06, raw.ver_total & 0xFF); | |
61 | via_write_reg_mask(VIACR, 0x07, (raw.ver_total >> 8 & 0x01) | |
62 | | (raw.ver_addr >> (8 - 1) & 0x02) | |
63 | | (raw.ver_sync_start >> (8 - 2) & 0x04) | |
64 | | (raw.ver_blank_start >> (8 - 3) & 0x08) | |
65 | | (raw.ver_total >> (9 - 5) & 0x20) | |
66 | | (raw.ver_addr >> (9 - 6) & 0x40) | |
67 | | (raw.ver_sync_start >> (9 - 7) & 0x80), 0xEF); | |
68 | via_write_reg_mask(VIACR, 0x09, raw.ver_blank_start >> (9 - 5) & 0x20, | |
69 | 0x20); | |
70 | via_write_reg(VIACR, 0x10, raw.ver_sync_start & 0xFF); | |
71 | via_write_reg_mask(VIACR, 0x11, raw.ver_sync_end & 0x0F, 0x0F); | |
72 | via_write_reg(VIACR, 0x12, raw.ver_addr & 0xFF); | |
73 | via_write_reg(VIACR, 0x15, raw.ver_blank_start & 0xFF); | |
74 | via_write_reg(VIACR, 0x16, raw.ver_blank_end & 0xFF); | |
75 | via_write_reg_mask(VIACR, 0x33, (raw.hor_sync_start >> (8 - 4) & 0x10) | |
76 | | (raw.hor_blank_end >> (6 - 5) & 0x20), 0x30); | |
77 | via_write_reg_mask(VIACR, 0x35, (raw.ver_total >> 10 & 0x01) | |
78 | | (raw.ver_sync_start >> (10 - 1) & 0x02) | |
79 | | (raw.ver_addr >> (10 - 2) & 0x04) | |
80 | | (raw.ver_blank_start >> (10 - 3) & 0x08), 0x0F); | |
81 | via_write_reg_mask(VIACR, 0x36, raw.hor_total >> (8 - 3) & 0x08, 0x08); | |
82 | ||
83 | /* lock timing registers */ | |
84 | via_write_reg_mask(VIACR, 0x11, 0x80, 0x80); | |
c174e3a3 FTS |
85 | |
86 | /* reset timing control */ | |
87 | via_write_reg_mask(VIACR, 0x17, 0x00, 0x80); | |
88 | via_write_reg_mask(VIACR, 0x17, 0x80, 0x80); | |
d60defb7 FTS |
89 | } |
90 | ||
ea4f3111 | 91 | void via_set_secondary_timing(const struct via_display_timing *timing) |
d60defb7 | 92 | { |
ea4f3111 | 93 | struct via_display_timing raw; |
d60defb7 FTS |
94 | |
95 | raw.hor_total = timing->hor_total - 1; | |
96 | raw.hor_addr = timing->hor_addr - 1; | |
97 | raw.hor_blank_start = timing->hor_blank_start - 1; | |
98 | raw.hor_blank_end = timing->hor_blank_end - 1; | |
99 | raw.hor_sync_start = timing->hor_sync_start - 1; | |
100 | raw.hor_sync_end = timing->hor_sync_end - 1; | |
101 | raw.ver_total = timing->ver_total - 1; | |
102 | raw.ver_addr = timing->ver_addr - 1; | |
103 | raw.ver_blank_start = timing->ver_blank_start - 1; | |
104 | raw.ver_blank_end = timing->ver_blank_end - 1; | |
105 | raw.ver_sync_start = timing->ver_sync_start - 1; | |
106 | raw.ver_sync_end = timing->ver_sync_end - 1; | |
107 | ||
108 | via_write_reg(VIACR, 0x50, raw.hor_total & 0xFF); | |
109 | via_write_reg(VIACR, 0x51, raw.hor_addr & 0xFF); | |
110 | via_write_reg(VIACR, 0x52, raw.hor_blank_start & 0xFF); | |
111 | via_write_reg(VIACR, 0x53, raw.hor_blank_end & 0xFF); | |
112 | via_write_reg(VIACR, 0x54, (raw.hor_blank_start >> 8 & 0x07) | |
113 | | (raw.hor_blank_end >> (8 - 3) & 0x38) | |
114 | | (raw.hor_sync_start >> (8 - 6) & 0xC0)); | |
115 | via_write_reg_mask(VIACR, 0x55, (raw.hor_total >> 8 & 0x0F) | |
116 | | (raw.hor_addr >> (8 - 4) & 0x70), 0x7F); | |
117 | via_write_reg(VIACR, 0x56, raw.hor_sync_start & 0xFF); | |
118 | via_write_reg(VIACR, 0x57, raw.hor_sync_end & 0xFF); | |
119 | via_write_reg(VIACR, 0x58, raw.ver_total & 0xFF); | |
120 | via_write_reg(VIACR, 0x59, raw.ver_addr & 0xFF); | |
121 | via_write_reg(VIACR, 0x5A, raw.ver_blank_start & 0xFF); | |
122 | via_write_reg(VIACR, 0x5B, raw.ver_blank_end & 0xFF); | |
123 | via_write_reg(VIACR, 0x5C, (raw.ver_blank_start >> 8 & 0x07) | |
124 | | (raw.ver_blank_end >> (8 - 3) & 0x38) | |
125 | | (raw.hor_sync_end >> (8 - 6) & 0x40) | |
126 | | (raw.hor_sync_start >> (10 - 7) & 0x80)); | |
127 | via_write_reg(VIACR, 0x5D, (raw.ver_total >> 8 & 0x07) | |
128 | | (raw.ver_addr >> (8 - 3) & 0x38) | |
129 | | (raw.hor_blank_end >> (11 - 6) & 0x40) | |
130 | | (raw.hor_sync_start >> (11 - 7) & 0x80)); | |
131 | via_write_reg(VIACR, 0x5E, raw.ver_sync_start & 0xFF); | |
132 | via_write_reg(VIACR, 0x5F, (raw.ver_sync_end & 0x1F) | |
133 | | (raw.ver_sync_start >> (8 - 5) & 0xE0)); | |
134 | } | |
135 | ||
100e74a1 FTS |
136 | void via_set_primary_address(u32 addr) |
137 | { | |
138 | DEBUG_MSG(KERN_DEBUG "via_set_primary_address(0x%08X)\n", addr); | |
139 | via_write_reg(VIACR, 0x0D, addr & 0xFF); | |
140 | via_write_reg(VIACR, 0x0C, (addr >> 8) & 0xFF); | |
141 | via_write_reg(VIACR, 0x34, (addr >> 16) & 0xFF); | |
142 | via_write_reg_mask(VIACR, 0x48, (addr >> 24) & 0x1F, 0x1F); | |
143 | } | |
144 | ||
145 | void via_set_secondary_address(u32 addr) | |
146 | { | |
147 | DEBUG_MSG(KERN_DEBUG "via_set_secondary_address(0x%08X)\n", addr); | |
148 | /* secondary display supports only quadword aligned memory */ | |
149 | via_write_reg_mask(VIACR, 0x62, (addr >> 2) & 0xFE, 0xFE); | |
150 | via_write_reg(VIACR, 0x63, (addr >> 10) & 0xFF); | |
151 | via_write_reg(VIACR, 0x64, (addr >> 18) & 0xFF); | |
152 | via_write_reg_mask(VIACR, 0xA3, (addr >> 26) & 0x07, 0x07); | |
153 | } | |
154 | ||
155 | void via_set_primary_pitch(u32 pitch) | |
156 | { | |
157 | DEBUG_MSG(KERN_DEBUG "via_set_primary_pitch(0x%08X)\n", pitch); | |
158 | /* spec does not say that first adapter skips 3 bits but old | |
159 | * code did it and seems to be reasonable in analogy to 2nd adapter | |
160 | */ | |
161 | pitch = pitch >> 3; | |
162 | via_write_reg(VIACR, 0x13, pitch & 0xFF); | |
163 | via_write_reg_mask(VIACR, 0x35, (pitch >> (8 - 5)) & 0xE0, 0xE0); | |
164 | } | |
165 | ||
166 | void via_set_secondary_pitch(u32 pitch) | |
167 | { | |
168 | DEBUG_MSG(KERN_DEBUG "via_set_secondary_pitch(0x%08X)\n", pitch); | |
169 | pitch = pitch >> 3; | |
170 | via_write_reg(VIACR, 0x66, pitch & 0xFF); | |
171 | via_write_reg_mask(VIACR, 0x67, (pitch >> 8) & 0x03, 0x03); | |
172 | via_write_reg_mask(VIACR, 0x71, (pitch >> (10 - 7)) & 0x80, 0x80); | |
173 | } | |
174 | ||
175 | void via_set_primary_color_depth(u8 depth) | |
176 | { | |
177 | u8 value; | |
178 | ||
179 | DEBUG_MSG(KERN_DEBUG "via_set_primary_color_depth(%d)\n", depth); | |
180 | switch (depth) { | |
181 | case 8: | |
182 | value = 0x00; | |
183 | break; | |
184 | case 15: | |
185 | value = 0x04; | |
186 | break; | |
187 | case 16: | |
188 | value = 0x14; | |
189 | break; | |
190 | case 24: | |
191 | value = 0x0C; | |
192 | break; | |
193 | case 30: | |
194 | value = 0x08; | |
195 | break; | |
196 | default: | |
197 | printk(KERN_WARNING "via_set_primary_color_depth: " | |
198 | "Unsupported depth: %d\n", depth); | |
199 | return; | |
200 | } | |
201 | ||
202 | via_write_reg_mask(VIASR, 0x15, value, 0x1C); | |
203 | } | |
204 | ||
205 | void via_set_secondary_color_depth(u8 depth) | |
206 | { | |
207 | u8 value; | |
208 | ||
209 | DEBUG_MSG(KERN_DEBUG "via_set_secondary_color_depth(%d)\n", depth); | |
210 | switch (depth) { | |
211 | case 8: | |
212 | value = 0x00; | |
213 | break; | |
214 | case 16: | |
215 | value = 0x40; | |
216 | break; | |
217 | case 24: | |
218 | value = 0xC0; | |
219 | break; | |
220 | case 30: | |
221 | value = 0x80; | |
222 | break; | |
223 | default: | |
224 | printk(KERN_WARNING "via_set_secondary_color_depth: " | |
225 | "Unsupported depth: %d\n", depth); | |
226 | return; | |
227 | } | |
228 | ||
229 | via_write_reg_mask(VIACR, 0x67, value, 0xC0); | |
230 | } |