Commit | Line | Data |
---|---|---|
147394c8 AK |
1 | /* |
2 | * xilinxfb.c | |
3 | * | |
4 | * Xilinx TFT LCD frame buffer driver | |
5 | * | |
6 | * Author: MontaVista Software, Inc. | |
7 | * source@mvista.com | |
8 | * | |
9 | * 2002-2007 (c) MontaVista Software, Inc. This file is licensed under the | |
10 | * terms of the GNU General Public License version 2. This program is licensed | |
11 | * "as is" without any warranty of any kind, whether express or implied. | |
12 | */ | |
13 | ||
14 | /* | |
15 | * This driver was based on au1100fb.c by MontaVista rewritten for 2.6 | |
16 | * by Embedded Alley Solutions <source@embeddedalley.com>, which in turn | |
17 | * was based on skeletonfb.c, Skeleton for a frame buffer device by | |
18 | * Geert Uytterhoeven. | |
19 | */ | |
20 | ||
3cb3ec2c | 21 | #include <linux/device.h> |
147394c8 AK |
22 | #include <linux/module.h> |
23 | #include <linux/kernel.h> | |
24 | #include <linux/version.h> | |
25 | #include <linux/errno.h> | |
26 | #include <linux/string.h> | |
27 | #include <linux/mm.h> | |
28 | #include <linux/fb.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/dma-mapping.h> | |
31 | #include <linux/platform_device.h> | |
32 | ||
33 | #include <asm/io.h> | |
dc8afdc7 | 34 | #include <linux/xilinxfb.h> |
147394c8 AK |
35 | |
36 | #define DRIVER_NAME "xilinxfb" | |
37 | #define DRIVER_DESCRIPTION "Xilinx TFT LCD frame buffer driver" | |
38 | ||
39 | /* | |
40 | * Xilinx calls it "PLB TFT LCD Controller" though it can also be used for | |
41 | * the VGA port on the Xilinx ML40x board. This is a hardware display controller | |
42 | * for a 640x480 resolution TFT or VGA screen. | |
43 | * | |
44 | * The interface to the framebuffer is nice and simple. There are two | |
45 | * control registers. The first tells the LCD interface where in memory | |
46 | * the frame buffer is (only the 11 most significant bits are used, so | |
47 | * don't start thinking about scrolling). The second allows the LCD to | |
48 | * be turned on or off as well as rotated 180 degrees. | |
49 | */ | |
50 | #define NUM_REGS 2 | |
51 | #define REG_FB_ADDR 0 | |
52 | #define REG_CTRL 1 | |
53 | #define REG_CTRL_ENABLE 0x0001 | |
54 | #define REG_CTRL_ROTATE 0x0002 | |
55 | ||
56 | /* | |
57 | * The hardware only handles a single mode: 640x480 24 bit true | |
58 | * color. Each pixel gets a word (32 bits) of memory. Within each word, | |
59 | * the 8 most significant bits are ignored, the next 8 bits are the red | |
60 | * level, the next 8 bits are the green level and the 8 least | |
61 | * significant bits are the blue level. Each row of the LCD uses 1024 | |
62 | * words, but only the first 640 pixels are displayed with the other 384 | |
63 | * words being ignored. There are 480 rows. | |
64 | */ | |
65 | #define BYTES_PER_PIXEL 4 | |
66 | #define BITS_PER_PIXEL (BYTES_PER_PIXEL * 8) | |
67 | #define XRES 640 | |
68 | #define YRES 480 | |
69 | #define XRES_VIRTUAL 1024 | |
70 | #define YRES_VIRTUAL YRES | |
71 | #define LINE_LENGTH (XRES_VIRTUAL * BYTES_PER_PIXEL) | |
72 | #define FB_SIZE (YRES_VIRTUAL * LINE_LENGTH) | |
73 | ||
74 | #define RED_SHIFT 16 | |
75 | #define GREEN_SHIFT 8 | |
76 | #define BLUE_SHIFT 0 | |
77 | ||
78 | #define PALETTE_ENTRIES_NO 16 /* passed to fb_alloc_cmap() */ | |
79 | ||
80 | /* | |
81 | * Here are the default fb_fix_screeninfo and fb_var_screeninfo structures | |
82 | */ | |
3f5b85d1 | 83 | static struct fb_fix_screeninfo xilinx_fb_fix = { |
147394c8 AK |
84 | .id = "Xilinx", |
85 | .type = FB_TYPE_PACKED_PIXELS, | |
86 | .visual = FB_VISUAL_TRUECOLOR, | |
87 | .smem_len = FB_SIZE, | |
88 | .line_length = LINE_LENGTH, | |
89 | .accel = FB_ACCEL_NONE | |
90 | }; | |
91 | ||
3f5b85d1 | 92 | static struct fb_var_screeninfo xilinx_fb_var = { |
147394c8 AK |
93 | .xres = XRES, |
94 | .yres = YRES, | |
95 | .xres_virtual = XRES_VIRTUAL, | |
96 | .yres_virtual = YRES_VIRTUAL, | |
97 | ||
98 | .bits_per_pixel = BITS_PER_PIXEL, | |
99 | ||
100 | .red = { RED_SHIFT, 8, 0 }, | |
101 | .green = { GREEN_SHIFT, 8, 0 }, | |
102 | .blue = { BLUE_SHIFT, 8, 0 }, | |
103 | .transp = { 0, 0, 0 }, | |
104 | ||
105 | .activate = FB_ACTIVATE_NOW | |
106 | }; | |
107 | ||
108 | struct xilinxfb_drvdata { | |
109 | ||
110 | struct fb_info info; /* FB driver info record */ | |
111 | ||
112 | u32 regs_phys; /* phys. address of the control registers */ | |
113 | u32 __iomem *regs; /* virt. address of the control registers */ | |
114 | ||
115 | unsigned char __iomem *fb_virt; /* virt. address of the frame buffer */ | |
116 | dma_addr_t fb_phys; /* phys. address of the frame buffer */ | |
117 | ||
118 | u32 reg_ctrl_default; | |
119 | ||
120 | u32 pseudo_palette[PALETTE_ENTRIES_NO]; | |
121 | /* Fake palette of 16 colors */ | |
122 | }; | |
123 | ||
124 | #define to_xilinxfb_drvdata(_info) \ | |
125 | container_of(_info, struct xilinxfb_drvdata, info) | |
126 | ||
127 | /* | |
128 | * The LCD controller has DCR interface to its registers, but all | |
129 | * the boards and configurations the driver has been tested with | |
130 | * use opb2dcr bridge. So the registers are seen as memory mapped. | |
131 | * This macro is to make it simple to add the direct DCR access | |
132 | * when it's needed. | |
133 | */ | |
134 | #define xilinx_fb_out_be32(driverdata, offset, val) \ | |
135 | out_be32(driverdata->regs + offset, val) | |
136 | ||
137 | static int | |
138 | xilinx_fb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue, | |
139 | unsigned transp, struct fb_info *fbi) | |
140 | { | |
141 | u32 *palette = fbi->pseudo_palette; | |
142 | ||
143 | if (regno >= PALETTE_ENTRIES_NO) | |
144 | return -EINVAL; | |
145 | ||
146 | if (fbi->var.grayscale) { | |
147 | /* Convert color to grayscale. | |
148 | * grayscale = 0.30*R + 0.59*G + 0.11*B */ | |
149 | red = green = blue = | |
150 | (red * 77 + green * 151 + blue * 28 + 127) >> 8; | |
151 | } | |
152 | ||
153 | /* fbi->fix.visual is always FB_VISUAL_TRUECOLOR */ | |
154 | ||
155 | /* We only handle 8 bits of each color. */ | |
156 | red >>= 8; | |
157 | green >>= 8; | |
158 | blue >>= 8; | |
159 | palette[regno] = (red << RED_SHIFT) | (green << GREEN_SHIFT) | | |
160 | (blue << BLUE_SHIFT); | |
161 | ||
162 | return 0; | |
163 | } | |
164 | ||
165 | static int | |
166 | xilinx_fb_blank(int blank_mode, struct fb_info *fbi) | |
167 | { | |
168 | struct xilinxfb_drvdata *drvdata = to_xilinxfb_drvdata(fbi); | |
169 | ||
170 | switch (blank_mode) { | |
171 | case FB_BLANK_UNBLANK: | |
172 | /* turn on panel */ | |
173 | xilinx_fb_out_be32(drvdata, REG_CTRL, drvdata->reg_ctrl_default); | |
174 | break; | |
175 | ||
176 | case FB_BLANK_NORMAL: | |
177 | case FB_BLANK_VSYNC_SUSPEND: | |
178 | case FB_BLANK_HSYNC_SUSPEND: | |
179 | case FB_BLANK_POWERDOWN: | |
180 | /* turn off panel */ | |
181 | xilinx_fb_out_be32(drvdata, REG_CTRL, 0); | |
182 | default: | |
183 | break; | |
184 | ||
185 | } | |
186 | return 0; /* success */ | |
187 | } | |
188 | ||
189 | static struct fb_ops xilinxfb_ops = | |
190 | { | |
191 | .owner = THIS_MODULE, | |
192 | .fb_setcolreg = xilinx_fb_setcolreg, | |
193 | .fb_blank = xilinx_fb_blank, | |
194 | .fb_fillrect = cfb_fillrect, | |
195 | .fb_copyarea = cfb_copyarea, | |
196 | .fb_imageblit = cfb_imageblit, | |
197 | }; | |
198 | ||
199 | /* === The device driver === */ | |
200 | ||
201 | static int | |
202 | xilinxfb_drv_probe(struct device *dev) | |
203 | { | |
204 | struct platform_device *pdev; | |
205 | struct xilinxfb_platform_data *pdata; | |
206 | struct xilinxfb_drvdata *drvdata; | |
207 | struct resource *regs_res; | |
208 | int retval; | |
209 | ||
210 | if (!dev) | |
211 | return -EINVAL; | |
212 | ||
213 | pdev = to_platform_device(dev); | |
214 | pdata = pdev->dev.platform_data; | |
215 | ||
147394c8 AK |
216 | drvdata = kzalloc(sizeof(*drvdata), GFP_KERNEL); |
217 | if (!drvdata) { | |
3cb3ec2c | 218 | dev_err(dev, "Couldn't allocate device private record\n"); |
147394c8 AK |
219 | return -ENOMEM; |
220 | } | |
221 | dev_set_drvdata(dev, drvdata); | |
222 | ||
223 | /* Map the control registers in */ | |
224 | regs_res = platform_get_resource(pdev, IORESOURCE_IO, 0); | |
225 | if (!regs_res || (regs_res->end - regs_res->start + 1 < 8)) { | |
3cb3ec2c | 226 | dev_err(dev, "Couldn't get registers resource\n"); |
147394c8 AK |
227 | retval = -EFAULT; |
228 | goto failed1; | |
229 | } | |
230 | ||
231 | if (!request_mem_region(regs_res->start, 8, DRIVER_NAME)) { | |
3cb3ec2c | 232 | dev_err(dev, "Couldn't lock memory region at 0x%08X\n", |
147394c8 AK |
233 | regs_res->start); |
234 | retval = -EBUSY; | |
235 | goto failed1; | |
236 | } | |
237 | drvdata->regs = (u32 __iomem*) ioremap(regs_res->start, 8); | |
238 | drvdata->regs_phys = regs_res->start; | |
239 | ||
240 | /* Allocate the framebuffer memory */ | |
241 | drvdata->fb_virt = dma_alloc_coherent(dev, PAGE_ALIGN(FB_SIZE), | |
242 | &drvdata->fb_phys, GFP_KERNEL); | |
243 | if (!drvdata->fb_virt) { | |
3cb3ec2c | 244 | dev_err(dev, "Could not allocate frame buffer memory\n"); |
147394c8 AK |
245 | retval = -ENOMEM; |
246 | goto failed2; | |
247 | } | |
248 | ||
249 | /* Clear (turn to black) the framebuffer */ | |
250 | memset_io((void *) drvdata->fb_virt, 0, FB_SIZE); | |
251 | ||
252 | /* Tell the hardware where the frame buffer is */ | |
253 | xilinx_fb_out_be32(drvdata, REG_FB_ADDR, drvdata->fb_phys); | |
254 | ||
255 | /* Turn on the display */ | |
f53161d1 GL |
256 | drvdata->reg_ctrl_default = REG_CTRL_ENABLE; |
257 | if (pdata && pdata->rotate_screen) | |
258 | drvdata->reg_ctrl_default |= REG_CTRL_ROTATE; | |
147394c8 AK |
259 | xilinx_fb_out_be32(drvdata, REG_CTRL, drvdata->reg_ctrl_default); |
260 | ||
261 | /* Fill struct fb_info */ | |
262 | drvdata->info.device = dev; | |
263 | drvdata->info.screen_base = drvdata->fb_virt; | |
264 | drvdata->info.fbops = &xilinxfb_ops; | |
265 | drvdata->info.fix = xilinx_fb_fix; | |
266 | drvdata->info.fix.smem_start = drvdata->fb_phys; | |
267 | drvdata->info.pseudo_palette = drvdata->pseudo_palette; | |
268 | ||
269 | if (fb_alloc_cmap(&drvdata->info.cmap, PALETTE_ENTRIES_NO, 0) < 0) { | |
3cb3ec2c | 270 | dev_err(dev, "Fail to allocate colormap (%d entries)\n", |
147394c8 AK |
271 | PALETTE_ENTRIES_NO); |
272 | retval = -EFAULT; | |
273 | goto failed3; | |
274 | } | |
275 | ||
276 | drvdata->info.flags = FBINFO_DEFAULT; | |
f53161d1 GL |
277 | if (pdata) { |
278 | xilinx_fb_var.height = pdata->screen_height_mm; | |
279 | xilinx_fb_var.width = pdata->screen_width_mm; | |
280 | } | |
147394c8 AK |
281 | drvdata->info.var = xilinx_fb_var; |
282 | ||
283 | /* Register new frame buffer */ | |
284 | if (register_framebuffer(&drvdata->info) < 0) { | |
3cb3ec2c | 285 | dev_err(dev, "Could not register frame buffer\n"); |
147394c8 AK |
286 | retval = -EINVAL; |
287 | goto failed4; | |
288 | } | |
289 | ||
258de4ba GL |
290 | /* Put a banner in the log (for DEBUG) */ |
291 | dev_dbg(dev, "regs: phys=%x, virt=%p\n", | |
292 | drvdata->regs_phys, drvdata->regs); | |
293 | dev_dbg(dev, "fb: phys=%p, virt=%p, size=%x\n", | |
294 | (void*)drvdata->fb_phys, drvdata->fb_virt, FB_SIZE); | |
147394c8 AK |
295 | return 0; /* success */ |
296 | ||
297 | failed4: | |
298 | fb_dealloc_cmap(&drvdata->info.cmap); | |
299 | ||
300 | failed3: | |
301 | dma_free_coherent(dev, PAGE_ALIGN(FB_SIZE), drvdata->fb_virt, | |
302 | drvdata->fb_phys); | |
303 | ||
304 | /* Turn off the display */ | |
305 | xilinx_fb_out_be32(drvdata, REG_CTRL, 0); | |
306 | iounmap(drvdata->regs); | |
307 | ||
308 | failed2: | |
309 | release_mem_region(regs_res->start, 8); | |
310 | ||
311 | failed1: | |
312 | kfree(drvdata); | |
313 | dev_set_drvdata(dev, NULL); | |
314 | ||
315 | return retval; | |
316 | } | |
317 | ||
318 | static int | |
319 | xilinxfb_drv_remove(struct device *dev) | |
320 | { | |
321 | struct xilinxfb_drvdata *drvdata; | |
322 | ||
323 | if (!dev) | |
324 | return -ENODEV; | |
325 | ||
326 | drvdata = (struct xilinxfb_drvdata *) dev_get_drvdata(dev); | |
327 | ||
328 | #if !defined(CONFIG_FRAMEBUFFER_CONSOLE) && defined(CONFIG_LOGO) | |
329 | xilinx_fb_blank(VESA_POWERDOWN, &drvdata->info); | |
330 | #endif | |
331 | ||
332 | unregister_framebuffer(&drvdata->info); | |
333 | ||
334 | fb_dealloc_cmap(&drvdata->info.cmap); | |
335 | ||
336 | dma_free_coherent(dev, PAGE_ALIGN(FB_SIZE), drvdata->fb_virt, | |
337 | drvdata->fb_phys); | |
338 | ||
339 | /* Turn off the display */ | |
340 | xilinx_fb_out_be32(drvdata, REG_CTRL, 0); | |
341 | iounmap(drvdata->regs); | |
342 | ||
343 | release_mem_region(drvdata->regs_phys, 8); | |
344 | ||
345 | kfree(drvdata); | |
346 | dev_set_drvdata(dev, NULL); | |
347 | ||
348 | return 0; | |
349 | } | |
350 | ||
351 | ||
352 | static struct device_driver xilinxfb_driver = { | |
353 | .name = DRIVER_NAME, | |
354 | .bus = &platform_bus_type, | |
355 | ||
356 | .probe = xilinxfb_drv_probe, | |
357 | .remove = xilinxfb_drv_remove | |
358 | }; | |
359 | ||
360 | static int __init | |
361 | xilinxfb_init(void) | |
362 | { | |
363 | /* | |
364 | * No kernel boot options used, | |
365 | * so we just need to register the driver | |
366 | */ | |
367 | return driver_register(&xilinxfb_driver); | |
368 | } | |
369 | ||
370 | static void __exit | |
371 | xilinxfb_cleanup(void) | |
372 | { | |
373 | driver_unregister(&xilinxfb_driver); | |
374 | } | |
375 | ||
376 | module_init(xilinxfb_init); | |
377 | module_exit(xilinxfb_cleanup); | |
378 | ||
379 | MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>"); | |
380 | MODULE_DESCRIPTION(DRIVER_DESCRIPTION); | |
381 | MODULE_LICENSE("GPL"); |