Commit | Line | Data |
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147394c8 AK |
1 | /* |
2 | * xilinxfb.c | |
3 | * | |
4 | * Xilinx TFT LCD frame buffer driver | |
5 | * | |
6 | * Author: MontaVista Software, Inc. | |
7 | * source@mvista.com | |
8 | * | |
31e8d460 GL |
9 | * 2002-2007 (c) MontaVista Software, Inc. |
10 | * 2007 (c) Secret Lab Technologies, Ltd. | |
11 | * | |
12 | * This file is licensed under the terms of the GNU General Public License | |
13 | * version 2. This program is licensed "as is" without any warranty of any | |
14 | * kind, whether express or implied. | |
147394c8 AK |
15 | */ |
16 | ||
17 | /* | |
18 | * This driver was based on au1100fb.c by MontaVista rewritten for 2.6 | |
19 | * by Embedded Alley Solutions <source@embeddedalley.com>, which in turn | |
20 | * was based on skeletonfb.c, Skeleton for a frame buffer device by | |
21 | * Geert Uytterhoeven. | |
22 | */ | |
23 | ||
3cb3ec2c | 24 | #include <linux/device.h> |
147394c8 AK |
25 | #include <linux/module.h> |
26 | #include <linux/kernel.h> | |
27 | #include <linux/version.h> | |
28 | #include <linux/errno.h> | |
29 | #include <linux/string.h> | |
30 | #include <linux/mm.h> | |
31 | #include <linux/fb.h> | |
32 | #include <linux/init.h> | |
33 | #include <linux/dma-mapping.h> | |
34 | #include <linux/platform_device.h> | |
31e8d460 GL |
35 | #if defined(CONFIG_OF) |
36 | #include <linux/of_device.h> | |
37 | #include <linux/of_platform.h> | |
38 | #endif | |
147394c8 | 39 | #include <asm/io.h> |
dc8afdc7 | 40 | #include <linux/xilinxfb.h> |
147394c8 AK |
41 | |
42 | #define DRIVER_NAME "xilinxfb" | |
43 | #define DRIVER_DESCRIPTION "Xilinx TFT LCD frame buffer driver" | |
44 | ||
45 | /* | |
46 | * Xilinx calls it "PLB TFT LCD Controller" though it can also be used for | |
47 | * the VGA port on the Xilinx ML40x board. This is a hardware display controller | |
48 | * for a 640x480 resolution TFT or VGA screen. | |
49 | * | |
50 | * The interface to the framebuffer is nice and simple. There are two | |
51 | * control registers. The first tells the LCD interface where in memory | |
52 | * the frame buffer is (only the 11 most significant bits are used, so | |
53 | * don't start thinking about scrolling). The second allows the LCD to | |
54 | * be turned on or off as well as rotated 180 degrees. | |
55 | */ | |
56 | #define NUM_REGS 2 | |
57 | #define REG_FB_ADDR 0 | |
58 | #define REG_CTRL 1 | |
59 | #define REG_CTRL_ENABLE 0x0001 | |
60 | #define REG_CTRL_ROTATE 0x0002 | |
61 | ||
62 | /* | |
63 | * The hardware only handles a single mode: 640x480 24 bit true | |
64 | * color. Each pixel gets a word (32 bits) of memory. Within each word, | |
65 | * the 8 most significant bits are ignored, the next 8 bits are the red | |
66 | * level, the next 8 bits are the green level and the 8 least | |
67 | * significant bits are the blue level. Each row of the LCD uses 1024 | |
68 | * words, but only the first 640 pixels are displayed with the other 384 | |
69 | * words being ignored. There are 480 rows. | |
70 | */ | |
71 | #define BYTES_PER_PIXEL 4 | |
72 | #define BITS_PER_PIXEL (BYTES_PER_PIXEL * 8) | |
73 | #define XRES 640 | |
74 | #define YRES 480 | |
75 | #define XRES_VIRTUAL 1024 | |
76 | #define YRES_VIRTUAL YRES | |
77 | #define LINE_LENGTH (XRES_VIRTUAL * BYTES_PER_PIXEL) | |
78 | #define FB_SIZE (YRES_VIRTUAL * LINE_LENGTH) | |
79 | ||
80 | #define RED_SHIFT 16 | |
81 | #define GREEN_SHIFT 8 | |
82 | #define BLUE_SHIFT 0 | |
83 | ||
84 | #define PALETTE_ENTRIES_NO 16 /* passed to fb_alloc_cmap() */ | |
85 | ||
86 | /* | |
87 | * Here are the default fb_fix_screeninfo and fb_var_screeninfo structures | |
88 | */ | |
3f5b85d1 | 89 | static struct fb_fix_screeninfo xilinx_fb_fix = { |
147394c8 AK |
90 | .id = "Xilinx", |
91 | .type = FB_TYPE_PACKED_PIXELS, | |
92 | .visual = FB_VISUAL_TRUECOLOR, | |
93 | .smem_len = FB_SIZE, | |
94 | .line_length = LINE_LENGTH, | |
95 | .accel = FB_ACCEL_NONE | |
96 | }; | |
97 | ||
3f5b85d1 | 98 | static struct fb_var_screeninfo xilinx_fb_var = { |
147394c8 AK |
99 | .xres = XRES, |
100 | .yres = YRES, | |
101 | .xres_virtual = XRES_VIRTUAL, | |
102 | .yres_virtual = YRES_VIRTUAL, | |
103 | ||
104 | .bits_per_pixel = BITS_PER_PIXEL, | |
105 | ||
106 | .red = { RED_SHIFT, 8, 0 }, | |
107 | .green = { GREEN_SHIFT, 8, 0 }, | |
108 | .blue = { BLUE_SHIFT, 8, 0 }, | |
109 | .transp = { 0, 0, 0 }, | |
110 | ||
111 | .activate = FB_ACTIVATE_NOW | |
112 | }; | |
113 | ||
114 | struct xilinxfb_drvdata { | |
115 | ||
116 | struct fb_info info; /* FB driver info record */ | |
117 | ||
118 | u32 regs_phys; /* phys. address of the control registers */ | |
119 | u32 __iomem *regs; /* virt. address of the control registers */ | |
120 | ||
b9a22794 | 121 | void *fb_virt; /* virt. address of the frame buffer */ |
147394c8 AK |
122 | dma_addr_t fb_phys; /* phys. address of the frame buffer */ |
123 | ||
124 | u32 reg_ctrl_default; | |
125 | ||
126 | u32 pseudo_palette[PALETTE_ENTRIES_NO]; | |
127 | /* Fake palette of 16 colors */ | |
128 | }; | |
129 | ||
130 | #define to_xilinxfb_drvdata(_info) \ | |
131 | container_of(_info, struct xilinxfb_drvdata, info) | |
132 | ||
133 | /* | |
134 | * The LCD controller has DCR interface to its registers, but all | |
135 | * the boards and configurations the driver has been tested with | |
136 | * use opb2dcr bridge. So the registers are seen as memory mapped. | |
137 | * This macro is to make it simple to add the direct DCR access | |
138 | * when it's needed. | |
139 | */ | |
140 | #define xilinx_fb_out_be32(driverdata, offset, val) \ | |
141 | out_be32(driverdata->regs + offset, val) | |
142 | ||
143 | static int | |
144 | xilinx_fb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue, | |
145 | unsigned transp, struct fb_info *fbi) | |
146 | { | |
147 | u32 *palette = fbi->pseudo_palette; | |
148 | ||
149 | if (regno >= PALETTE_ENTRIES_NO) | |
150 | return -EINVAL; | |
151 | ||
152 | if (fbi->var.grayscale) { | |
153 | /* Convert color to grayscale. | |
154 | * grayscale = 0.30*R + 0.59*G + 0.11*B */ | |
155 | red = green = blue = | |
156 | (red * 77 + green * 151 + blue * 28 + 127) >> 8; | |
157 | } | |
158 | ||
159 | /* fbi->fix.visual is always FB_VISUAL_TRUECOLOR */ | |
160 | ||
161 | /* We only handle 8 bits of each color. */ | |
162 | red >>= 8; | |
163 | green >>= 8; | |
164 | blue >>= 8; | |
165 | palette[regno] = (red << RED_SHIFT) | (green << GREEN_SHIFT) | | |
166 | (blue << BLUE_SHIFT); | |
167 | ||
168 | return 0; | |
169 | } | |
170 | ||
171 | static int | |
172 | xilinx_fb_blank(int blank_mode, struct fb_info *fbi) | |
173 | { | |
174 | struct xilinxfb_drvdata *drvdata = to_xilinxfb_drvdata(fbi); | |
175 | ||
176 | switch (blank_mode) { | |
177 | case FB_BLANK_UNBLANK: | |
178 | /* turn on panel */ | |
179 | xilinx_fb_out_be32(drvdata, REG_CTRL, drvdata->reg_ctrl_default); | |
180 | break; | |
181 | ||
182 | case FB_BLANK_NORMAL: | |
183 | case FB_BLANK_VSYNC_SUSPEND: | |
184 | case FB_BLANK_HSYNC_SUSPEND: | |
185 | case FB_BLANK_POWERDOWN: | |
186 | /* turn off panel */ | |
187 | xilinx_fb_out_be32(drvdata, REG_CTRL, 0); | |
188 | default: | |
189 | break; | |
190 | ||
191 | } | |
192 | return 0; /* success */ | |
193 | } | |
194 | ||
195 | static struct fb_ops xilinxfb_ops = | |
196 | { | |
197 | .owner = THIS_MODULE, | |
198 | .fb_setcolreg = xilinx_fb_setcolreg, | |
199 | .fb_blank = xilinx_fb_blank, | |
200 | .fb_fillrect = cfb_fillrect, | |
201 | .fb_copyarea = cfb_copyarea, | |
202 | .fb_imageblit = cfb_imageblit, | |
203 | }; | |
204 | ||
26477622 GL |
205 | /* --------------------------------------------------------------------- |
206 | * Bus independent setup/teardown | |
207 | */ | |
147394c8 | 208 | |
26477622 GL |
209 | static int xilinxfb_assign(struct device *dev, unsigned long physaddr, |
210 | int width_mm, int height_mm, int rotate) | |
147394c8 | 211 | { |
147394c8 | 212 | struct xilinxfb_drvdata *drvdata; |
26477622 | 213 | int rc; |
147394c8 | 214 | |
26477622 | 215 | /* Allocate the driver data region */ |
147394c8 AK |
216 | drvdata = kzalloc(sizeof(*drvdata), GFP_KERNEL); |
217 | if (!drvdata) { | |
3cb3ec2c | 218 | dev_err(dev, "Couldn't allocate device private record\n"); |
147394c8 AK |
219 | return -ENOMEM; |
220 | } | |
221 | dev_set_drvdata(dev, drvdata); | |
222 | ||
223 | /* Map the control registers in */ | |
26477622 GL |
224 | if (!request_mem_region(physaddr, 8, DRIVER_NAME)) { |
225 | dev_err(dev, "Couldn't lock memory region at 0x%08lX\n", | |
226 | physaddr); | |
227 | rc = -ENODEV; | |
3fb99ce4 | 228 | goto err_region; |
147394c8 | 229 | } |
26477622 GL |
230 | drvdata->regs_phys = physaddr; |
231 | drvdata->regs = ioremap(physaddr, 8); | |
232 | if (!drvdata->regs) { | |
233 | dev_err(dev, "Couldn't lock memory region at 0x%08lX\n", | |
234 | physaddr); | |
235 | rc = -ENODEV; | |
236 | goto err_map; | |
147394c8 | 237 | } |
147394c8 AK |
238 | |
239 | /* Allocate the framebuffer memory */ | |
240 | drvdata->fb_virt = dma_alloc_coherent(dev, PAGE_ALIGN(FB_SIZE), | |
241 | &drvdata->fb_phys, GFP_KERNEL); | |
242 | if (!drvdata->fb_virt) { | |
3cb3ec2c | 243 | dev_err(dev, "Could not allocate frame buffer memory\n"); |
26477622 | 244 | rc = -ENOMEM; |
3fb99ce4 | 245 | goto err_fbmem; |
147394c8 AK |
246 | } |
247 | ||
248 | /* Clear (turn to black) the framebuffer */ | |
b9a22794 | 249 | memset_io((void __iomem *)drvdata->fb_virt, 0, FB_SIZE); |
147394c8 AK |
250 | |
251 | /* Tell the hardware where the frame buffer is */ | |
252 | xilinx_fb_out_be32(drvdata, REG_FB_ADDR, drvdata->fb_phys); | |
253 | ||
254 | /* Turn on the display */ | |
f53161d1 | 255 | drvdata->reg_ctrl_default = REG_CTRL_ENABLE; |
26477622 | 256 | if (rotate) |
f53161d1 | 257 | drvdata->reg_ctrl_default |= REG_CTRL_ROTATE; |
147394c8 AK |
258 | xilinx_fb_out_be32(drvdata, REG_CTRL, drvdata->reg_ctrl_default); |
259 | ||
260 | /* Fill struct fb_info */ | |
261 | drvdata->info.device = dev; | |
b9a22794 | 262 | drvdata->info.screen_base = (void __iomem *)drvdata->fb_virt; |
147394c8 AK |
263 | drvdata->info.fbops = &xilinxfb_ops; |
264 | drvdata->info.fix = xilinx_fb_fix; | |
265 | drvdata->info.fix.smem_start = drvdata->fb_phys; | |
266 | drvdata->info.pseudo_palette = drvdata->pseudo_palette; | |
26477622 GL |
267 | drvdata->info.flags = FBINFO_DEFAULT; |
268 | drvdata->info.var = xilinx_fb_var; | |
269 | ||
270 | xilinx_fb_var.height = height_mm; | |
271 | xilinx_fb_var.width = width_mm; | |
147394c8 | 272 | |
26477622 GL |
273 | /* Allocate a colour map */ |
274 | rc = fb_alloc_cmap(&drvdata->info.cmap, PALETTE_ENTRIES_NO, 0); | |
275 | if (rc) { | |
3cb3ec2c | 276 | dev_err(dev, "Fail to allocate colormap (%d entries)\n", |
147394c8 | 277 | PALETTE_ENTRIES_NO); |
3fb99ce4 | 278 | goto err_cmap; |
147394c8 AK |
279 | } |
280 | ||
147394c8 | 281 | /* Register new frame buffer */ |
26477622 GL |
282 | rc = register_framebuffer(&drvdata->info); |
283 | if (rc) { | |
3cb3ec2c | 284 | dev_err(dev, "Could not register frame buffer\n"); |
3fb99ce4 | 285 | goto err_regfb; |
147394c8 AK |
286 | } |
287 | ||
258de4ba | 288 | /* Put a banner in the log (for DEBUG) */ |
26477622 | 289 | dev_dbg(dev, "regs: phys=%lx, virt=%p\n", physaddr, drvdata->regs); |
258de4ba GL |
290 | dev_dbg(dev, "fb: phys=%p, virt=%p, size=%x\n", |
291 | (void*)drvdata->fb_phys, drvdata->fb_virt, FB_SIZE); | |
147394c8 AK |
292 | return 0; /* success */ |
293 | ||
3fb99ce4 | 294 | err_regfb: |
147394c8 AK |
295 | fb_dealloc_cmap(&drvdata->info.cmap); |
296 | ||
3fb99ce4 | 297 | err_cmap: |
147394c8 AK |
298 | dma_free_coherent(dev, PAGE_ALIGN(FB_SIZE), drvdata->fb_virt, |
299 | drvdata->fb_phys); | |
147394c8 AK |
300 | /* Turn off the display */ |
301 | xilinx_fb_out_be32(drvdata, REG_CTRL, 0); | |
147394c8 | 302 | |
3fb99ce4 | 303 | err_fbmem: |
26477622 GL |
304 | iounmap(drvdata->regs); |
305 | ||
306 | err_map: | |
307 | release_mem_region(physaddr, 8); | |
147394c8 | 308 | |
3fb99ce4 | 309 | err_region: |
147394c8 AK |
310 | kfree(drvdata); |
311 | dev_set_drvdata(dev, NULL); | |
312 | ||
26477622 | 313 | return rc; |
147394c8 AK |
314 | } |
315 | ||
26477622 | 316 | static int xilinxfb_release(struct device *dev) |
147394c8 | 317 | { |
26477622 | 318 | struct xilinxfb_drvdata *drvdata = dev_get_drvdata(dev); |
147394c8 AK |
319 | |
320 | #if !defined(CONFIG_FRAMEBUFFER_CONSOLE) && defined(CONFIG_LOGO) | |
321 | xilinx_fb_blank(VESA_POWERDOWN, &drvdata->info); | |
322 | #endif | |
323 | ||
324 | unregister_framebuffer(&drvdata->info); | |
325 | ||
326 | fb_dealloc_cmap(&drvdata->info.cmap); | |
327 | ||
328 | dma_free_coherent(dev, PAGE_ALIGN(FB_SIZE), drvdata->fb_virt, | |
329 | drvdata->fb_phys); | |
330 | ||
331 | /* Turn off the display */ | |
332 | xilinx_fb_out_be32(drvdata, REG_CTRL, 0); | |
333 | iounmap(drvdata->regs); | |
334 | ||
335 | release_mem_region(drvdata->regs_phys, 8); | |
336 | ||
337 | kfree(drvdata); | |
338 | dev_set_drvdata(dev, NULL); | |
339 | ||
340 | return 0; | |
341 | } | |
342 | ||
26477622 GL |
343 | /* --------------------------------------------------------------------- |
344 | * Platform bus binding | |
345 | */ | |
346 | ||
347 | static int | |
47473e31 | 348 | xilinxfb_platform_probe(struct platform_device *pdev) |
26477622 | 349 | { |
26477622 GL |
350 | struct xilinxfb_platform_data *pdata; |
351 | struct resource *res; | |
e3cec003 GL |
352 | int width_mm = 0; |
353 | int height_mm = 0; | |
354 | int rotate = 0; | |
26477622 GL |
355 | |
356 | /* Find the registers address */ | |
357 | res = platform_get_resource(pdev, IORESOURCE_IO, 0); | |
358 | if (!res) { | |
47473e31 | 359 | dev_err(&pdev->dev, "Couldn't get registers resource\n"); |
26477622 GL |
360 | return -ENODEV; |
361 | } | |
362 | ||
e3cec003 GL |
363 | /* If a pdata structure is provided, then extract the parameters */ |
364 | pdata = pdev->dev.platform_data; | |
365 | if (pdata) { | |
366 | height_mm = pdata->screen_height_mm; | |
367 | width_mm = pdata->screen_width_mm; | |
368 | rotate = pdata->rotate_screen ? 1 : 0; | |
369 | } | |
26477622 | 370 | |
47473e31 GL |
371 | return xilinxfb_assign(&pdev->dev, res->start, width_mm, height_mm, |
372 | rotate); | |
26477622 GL |
373 | } |
374 | ||
375 | static int | |
47473e31 | 376 | xilinxfb_platform_remove(struct platform_device *pdev) |
26477622 | 377 | { |
47473e31 | 378 | return xilinxfb_release(&pdev->dev); |
26477622 GL |
379 | } |
380 | ||
147394c8 | 381 | |
47473e31 GL |
382 | static struct platform_driver xilinxfb_platform_driver = { |
383 | .probe = xilinxfb_platform_probe, | |
384 | .remove = xilinxfb_platform_remove, | |
385 | .driver = { | |
386 | .owner = THIS_MODULE, | |
387 | .name = DRIVER_NAME, | |
388 | }, | |
147394c8 AK |
389 | }; |
390 | ||
31e8d460 GL |
391 | /* --------------------------------------------------------------------- |
392 | * OF bus binding | |
393 | */ | |
394 | ||
395 | #if defined(CONFIG_OF) | |
396 | static int __devinit | |
397 | xilinxfb_of_probe(struct of_device *op, const struct of_device_id *match) | |
398 | { | |
399 | struct resource res; | |
400 | const u32 *prop; | |
401 | int width = 0, height = 0, rotate = 0; | |
402 | int size, rc; | |
403 | ||
404 | dev_dbg(&op->dev, "xilinxfb_of_probe(%p, %p)\n", op, match); | |
405 | ||
406 | rc = of_address_to_resource(op->node, 0, &res); | |
407 | if (rc) { | |
408 | dev_err(&op->dev, "invalid address\n"); | |
409 | return rc; | |
410 | } | |
411 | ||
412 | prop = of_get_property(op->node, "display-number", &size); | |
413 | if ((prop) && (size >= sizeof(u32)*2)) { | |
414 | width = prop[0]; | |
415 | height = prop[1]; | |
416 | } | |
417 | ||
418 | if (of_find_property(op->node, "rotate-display", NULL)) | |
419 | rotate = 1; | |
420 | ||
421 | return xilinxfb_assign(&op->dev, res.start, width, height, rotate); | |
422 | } | |
423 | ||
424 | static int __devexit xilinxfb_of_remove(struct of_device *op) | |
425 | { | |
426 | return xilinxfb_release(&op->dev); | |
427 | } | |
428 | ||
429 | /* Match table for of_platform binding */ | |
430 | static struct of_device_id __devinit xilinxfb_of_match[] = { | |
431 | { .compatible = "xilinx,ml300-fb", }, | |
432 | {}, | |
433 | }; | |
434 | MODULE_DEVICE_TABLE(of, xilinxfb_of_match); | |
435 | ||
436 | static struct of_platform_driver xilinxfb_of_driver = { | |
437 | .owner = THIS_MODULE, | |
438 | .name = DRIVER_NAME, | |
439 | .match_table = xilinxfb_of_match, | |
440 | .probe = xilinxfb_of_probe, | |
441 | .remove = __devexit_p(xilinxfb_of_remove), | |
442 | .driver = { | |
443 | .name = DRIVER_NAME, | |
444 | }, | |
445 | }; | |
446 | ||
447 | /* Registration helpers to keep the number of #ifdefs to a minimum */ | |
448 | static inline int __init xilinxfb_of_register(void) | |
449 | { | |
450 | pr_debug("xilinxfb: calling of_register_platform_driver()\n"); | |
451 | return of_register_platform_driver(&xilinxfb_of_driver); | |
452 | } | |
453 | ||
454 | static inline void __exit xilinxfb_of_unregister(void) | |
455 | { | |
456 | of_unregister_platform_driver(&xilinxfb_of_driver); | |
457 | } | |
458 | #else /* CONFIG_OF */ | |
459 | /* CONFIG_OF not enabled; do nothing helpers */ | |
460 | static inline int __init xilinxfb_of_register(void) { return 0; } | |
461 | static inline void __exit xilinxfb_of_unregister(void) { } | |
462 | #endif /* CONFIG_OF */ | |
463 | ||
464 | /* --------------------------------------------------------------------- | |
465 | * Module setup and teardown | |
466 | */ | |
467 | ||
147394c8 AK |
468 | static int __init |
469 | xilinxfb_init(void) | |
470 | { | |
31e8d460 GL |
471 | int rc; |
472 | rc = xilinxfb_of_register(); | |
473 | if (rc) | |
474 | return rc; | |
475 | ||
476 | rc = platform_driver_register(&xilinxfb_platform_driver); | |
477 | if (rc) | |
478 | xilinxfb_of_unregister(); | |
479 | ||
480 | return rc; | |
147394c8 AK |
481 | } |
482 | ||
483 | static void __exit | |
484 | xilinxfb_cleanup(void) | |
485 | { | |
47473e31 | 486 | platform_driver_unregister(&xilinxfb_platform_driver); |
31e8d460 | 487 | xilinxfb_of_unregister(); |
147394c8 AK |
488 | } |
489 | ||
490 | module_init(xilinxfb_init); | |
491 | module_exit(xilinxfb_cleanup); | |
492 | ||
493 | MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>"); | |
494 | MODULE_DESCRIPTION(DRIVER_DESCRIPTION); | |
495 | MODULE_LICENSE("GPL"); |