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c283cf2c MC |
1 | /* |
2 | * drivers/watchdog/ar7_wdt.c | |
3 | * | |
4 | * Copyright (C) 2007 Nicolas Thill <nico@openwrt.org> | |
5 | * Copyright (c) 2005 Enrik Berkhan <Enrik.Berkhan@akk.org> | |
6 | * | |
7 | * Some code taken from: | |
8 | * National Semiconductor SCx200 Watchdog support | |
9 | * Copyright (c) 2001,2002 Christer Weinigel <wingel@nano-system.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
24 | */ | |
25 | ||
26 | #include <linux/module.h> | |
27 | #include <linux/moduleparam.h> | |
28 | #include <linux/errno.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/miscdevice.h> | |
64d4062a | 31 | #include <linux/platform_device.h> |
c283cf2c | 32 | #include <linux/watchdog.h> |
c283cf2c MC |
33 | #include <linux/fs.h> |
34 | #include <linux/ioport.h> | |
35 | #include <linux/io.h> | |
36 | #include <linux/uaccess.h> | |
780019dd | 37 | #include <linux/clk.h> |
c283cf2c MC |
38 | |
39 | #include <asm/addrspace.h> | |
c5e7f5a3 | 40 | #include <asm/mach-ar7/ar7.h> |
c283cf2c MC |
41 | |
42 | #define DRVNAME "ar7_wdt" | |
43 | #define LONGNAME "TI AR7 Watchdog Timer" | |
44 | ||
45 | MODULE_AUTHOR("Nicolas Thill <nico@openwrt.org>"); | |
46 | MODULE_DESCRIPTION(LONGNAME); | |
47 | MODULE_LICENSE("GPL"); | |
48 | MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); | |
49 | ||
50 | static int margin = 60; | |
51 | module_param(margin, int, 0); | |
52 | MODULE_PARM_DESC(margin, "Watchdog margin in seconds"); | |
53 | ||
54 | static int nowayout = WATCHDOG_NOWAYOUT; | |
55 | module_param(nowayout, int, 0); | |
56 | MODULE_PARM_DESC(nowayout, "Disable watchdog shutdown on close"); | |
57 | ||
58 | #define READ_REG(x) readl((void __iomem *)&(x)) | |
59 | #define WRITE_REG(x, v) writel((v), (void __iomem *)&(x)) | |
60 | ||
61 | struct ar7_wdt { | |
62 | u32 kick_lock; | |
63 | u32 kick; | |
64 | u32 change_lock; | |
65 | u32 change; | |
66 | u32 disable_lock; | |
67 | u32 disable; | |
68 | u32 prescale_lock; | |
69 | u32 prescale; | |
70 | }; | |
71 | ||
670d59c0 AC |
72 | static unsigned long wdt_is_open; |
73 | static spinlock_t wdt_lock; | |
c283cf2c MC |
74 | static unsigned expect_close; |
75 | ||
76 | /* XXX currently fixed, allows max margin ~68.72 secs */ | |
77 | #define prescale_value 0xffff | |
78 | ||
64d4062a FF |
79 | /* Resource of the WDT registers */ |
80 | static struct resource *ar7_regs_wdt; | |
c283cf2c MC |
81 | /* Pointer to the remapped WDT IO space */ |
82 | static struct ar7_wdt *ar7_wdt; | |
c283cf2c | 83 | |
780019dd FF |
84 | static struct clk *vbus_clk; |
85 | ||
c283cf2c MC |
86 | static void ar7_wdt_kick(u32 value) |
87 | { | |
88 | WRITE_REG(ar7_wdt->kick_lock, 0x5555); | |
89 | if ((READ_REG(ar7_wdt->kick_lock) & 3) == 1) { | |
90 | WRITE_REG(ar7_wdt->kick_lock, 0xaaaa); | |
91 | if ((READ_REG(ar7_wdt->kick_lock) & 3) == 3) { | |
92 | WRITE_REG(ar7_wdt->kick, value); | |
93 | return; | |
94 | } | |
95 | } | |
96 | printk(KERN_ERR DRVNAME ": failed to unlock WDT kick reg\n"); | |
97 | } | |
98 | ||
99 | static void ar7_wdt_prescale(u32 value) | |
100 | { | |
101 | WRITE_REG(ar7_wdt->prescale_lock, 0x5a5a); | |
102 | if ((READ_REG(ar7_wdt->prescale_lock) & 3) == 1) { | |
103 | WRITE_REG(ar7_wdt->prescale_lock, 0xa5a5); | |
104 | if ((READ_REG(ar7_wdt->prescale_lock) & 3) == 3) { | |
105 | WRITE_REG(ar7_wdt->prescale, value); | |
106 | return; | |
107 | } | |
108 | } | |
109 | printk(KERN_ERR DRVNAME ": failed to unlock WDT prescale reg\n"); | |
110 | } | |
111 | ||
112 | static void ar7_wdt_change(u32 value) | |
113 | { | |
114 | WRITE_REG(ar7_wdt->change_lock, 0x6666); | |
115 | if ((READ_REG(ar7_wdt->change_lock) & 3) == 1) { | |
116 | WRITE_REG(ar7_wdt->change_lock, 0xbbbb); | |
117 | if ((READ_REG(ar7_wdt->change_lock) & 3) == 3) { | |
118 | WRITE_REG(ar7_wdt->change, value); | |
119 | return; | |
120 | } | |
121 | } | |
122 | printk(KERN_ERR DRVNAME ": failed to unlock WDT change reg\n"); | |
123 | } | |
124 | ||
125 | static void ar7_wdt_disable(u32 value) | |
126 | { | |
127 | WRITE_REG(ar7_wdt->disable_lock, 0x7777); | |
128 | if ((READ_REG(ar7_wdt->disable_lock) & 3) == 1) { | |
129 | WRITE_REG(ar7_wdt->disable_lock, 0xcccc); | |
130 | if ((READ_REG(ar7_wdt->disable_lock) & 3) == 2) { | |
131 | WRITE_REG(ar7_wdt->disable_lock, 0xdddd); | |
132 | if ((READ_REG(ar7_wdt->disable_lock) & 3) == 3) { | |
133 | WRITE_REG(ar7_wdt->disable, value); | |
134 | return; | |
135 | } | |
136 | } | |
137 | } | |
138 | printk(KERN_ERR DRVNAME ": failed to unlock WDT disable reg\n"); | |
139 | } | |
140 | ||
141 | static void ar7_wdt_update_margin(int new_margin) | |
142 | { | |
143 | u32 change; | |
780019dd | 144 | u32 vbus_rate; |
c283cf2c | 145 | |
780019dd FF |
146 | vbus_rate = clk_get_rate(vbus_clk); |
147 | change = new_margin * (vbus_rate / prescale_value); | |
670d59c0 AC |
148 | if (change < 1) |
149 | change = 1; | |
150 | if (change > 0xffff) | |
151 | change = 0xffff; | |
c283cf2c | 152 | ar7_wdt_change(change); |
780019dd | 153 | margin = change * prescale_value / vbus_rate; |
c283cf2c MC |
154 | printk(KERN_INFO DRVNAME |
155 | ": timer margin %d seconds (prescale %d, change %d, freq %d)\n", | |
780019dd | 156 | margin, prescale_value, change, vbus_rate); |
c283cf2c MC |
157 | } |
158 | ||
159 | static void ar7_wdt_enable_wdt(void) | |
160 | { | |
161 | printk(KERN_DEBUG DRVNAME ": enabling watchdog timer\n"); | |
162 | ar7_wdt_disable(1); | |
163 | ar7_wdt_kick(1); | |
164 | } | |
165 | ||
166 | static void ar7_wdt_disable_wdt(void) | |
167 | { | |
168 | printk(KERN_DEBUG DRVNAME ": disabling watchdog timer\n"); | |
169 | ar7_wdt_disable(0); | |
170 | } | |
171 | ||
172 | static int ar7_wdt_open(struct inode *inode, struct file *file) | |
173 | { | |
174 | /* only allow one at a time */ | |
670d59c0 | 175 | if (test_and_set_bit(0, &wdt_is_open)) |
c283cf2c MC |
176 | return -EBUSY; |
177 | ar7_wdt_enable_wdt(); | |
178 | expect_close = 0; | |
179 | ||
180 | return nonseekable_open(inode, file); | |
181 | } | |
182 | ||
183 | static int ar7_wdt_release(struct inode *inode, struct file *file) | |
184 | { | |
185 | if (!expect_close) | |
186 | printk(KERN_WARNING DRVNAME | |
187 | ": watchdog device closed unexpectedly," | |
188 | "will not disable the watchdog timer\n"); | |
189 | else if (!nowayout) | |
190 | ar7_wdt_disable_wdt(); | |
670d59c0 | 191 | clear_bit(0, &wdt_is_open); |
c283cf2c MC |
192 | return 0; |
193 | } | |
194 | ||
c283cf2c MC |
195 | static ssize_t ar7_wdt_write(struct file *file, const char *data, |
196 | size_t len, loff_t *ppos) | |
197 | { | |
198 | /* check for a magic close character */ | |
199 | if (len) { | |
200 | size_t i; | |
201 | ||
670d59c0 | 202 | spin_lock(&wdt_lock); |
c283cf2c | 203 | ar7_wdt_kick(1); |
670d59c0 | 204 | spin_unlock(&wdt_lock); |
c283cf2c MC |
205 | |
206 | expect_close = 0; | |
207 | for (i = 0; i < len; ++i) { | |
208 | char c; | |
7944d3a5 | 209 | if (get_user(c, data + i)) |
c283cf2c MC |
210 | return -EFAULT; |
211 | if (c == 'V') | |
212 | expect_close = 1; | |
213 | } | |
214 | ||
215 | } | |
216 | return len; | |
217 | } | |
218 | ||
670d59c0 AC |
219 | static long ar7_wdt_ioctl(struct file *file, |
220 | unsigned int cmd, unsigned long arg) | |
c283cf2c | 221 | { |
42747d71 | 222 | static const struct watchdog_info ident = { |
c283cf2c MC |
223 | .identity = LONGNAME, |
224 | .firmware_version = 1, | |
e73a7802 WVS |
225 | .options = (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | |
226 | WDIOF_MAGICCLOSE), | |
c283cf2c MC |
227 | }; |
228 | int new_margin; | |
229 | ||
230 | switch (cmd) { | |
c283cf2c MC |
231 | case WDIOC_GETSUPPORT: |
232 | if (copy_to_user((struct watchdog_info *)arg, &ident, | |
233 | sizeof(ident))) | |
234 | return -EFAULT; | |
235 | return 0; | |
236 | case WDIOC_GETSTATUS: | |
237 | case WDIOC_GETBOOTSTATUS: | |
238 | if (put_user(0, (int *)arg)) | |
239 | return -EFAULT; | |
240 | return 0; | |
241 | case WDIOC_KEEPALIVE: | |
242 | ar7_wdt_kick(1); | |
243 | return 0; | |
244 | case WDIOC_SETTIMEOUT: | |
245 | if (get_user(new_margin, (int *)arg)) | |
246 | return -EFAULT; | |
247 | if (new_margin < 1) | |
248 | return -EINVAL; | |
249 | ||
670d59c0 | 250 | spin_lock(&wdt_lock); |
c283cf2c MC |
251 | ar7_wdt_update_margin(new_margin); |
252 | ar7_wdt_kick(1); | |
670d59c0 | 253 | spin_unlock(&wdt_lock); |
c283cf2c MC |
254 | |
255 | case WDIOC_GETTIMEOUT: | |
256 | if (put_user(margin, (int *)arg)) | |
257 | return -EFAULT; | |
258 | return 0; | |
0c06090c WVS |
259 | default: |
260 | return -ENOTTY; | |
c283cf2c MC |
261 | } |
262 | } | |
263 | ||
b47a166e | 264 | static const struct file_operations ar7_wdt_fops = { |
c283cf2c MC |
265 | .owner = THIS_MODULE, |
266 | .write = ar7_wdt_write, | |
670d59c0 | 267 | .unlocked_ioctl = ar7_wdt_ioctl, |
c283cf2c MC |
268 | .open = ar7_wdt_open, |
269 | .release = ar7_wdt_release, | |
6038f373 | 270 | .llseek = no_llseek, |
c283cf2c MC |
271 | }; |
272 | ||
273 | static struct miscdevice ar7_wdt_miscdev = { | |
274 | .minor = WATCHDOG_MINOR, | |
275 | .name = "watchdog", | |
276 | .fops = &ar7_wdt_fops, | |
277 | }; | |
278 | ||
64d4062a | 279 | static int __devinit ar7_wdt_probe(struct platform_device *pdev) |
c283cf2c MC |
280 | { |
281 | int rc; | |
282 | ||
670d59c0 AC |
283 | spin_lock_init(&wdt_lock); |
284 | ||
64d4062a FF |
285 | ar7_regs_wdt = |
286 | platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); | |
287 | if (!ar7_regs_wdt) { | |
288 | printk(KERN_ERR DRVNAME ": could not get registers resource\n"); | |
289 | rc = -ENODEV; | |
290 | goto out; | |
291 | } | |
c283cf2c | 292 | |
64d4062a FF |
293 | if (!request_mem_region(ar7_regs_wdt->start, |
294 | resource_size(ar7_regs_wdt), LONGNAME)) { | |
c283cf2c | 295 | printk(KERN_WARNING DRVNAME ": watchdog I/O region busy\n"); |
64d4062a FF |
296 | rc = -EBUSY; |
297 | goto out; | |
c283cf2c MC |
298 | } |
299 | ||
64d4062a FF |
300 | ar7_wdt = ioremap(ar7_regs_wdt->start, resource_size(ar7_regs_wdt)); |
301 | if (!ar7_wdt) { | |
302 | printk(KERN_ERR DRVNAME ": could not ioremap registers\n"); | |
303 | rc = -ENXIO; | |
d7e9791b | 304 | goto out_mem_region; |
64d4062a | 305 | } |
c283cf2c | 306 | |
780019dd FF |
307 | vbus_clk = clk_get(NULL, "vbus"); |
308 | if (IS_ERR(vbus_clk)) { | |
309 | printk(KERN_ERR DRVNAME ": could not get vbus clock\n"); | |
310 | rc = PTR_ERR(vbus_clk); | |
311 | goto out_mem_region; | |
312 | } | |
313 | ||
c283cf2c MC |
314 | ar7_wdt_disable_wdt(); |
315 | ar7_wdt_prescale(prescale_value); | |
316 | ar7_wdt_update_margin(margin); | |
317 | ||
c283cf2c MC |
318 | rc = misc_register(&ar7_wdt_miscdev); |
319 | if (rc) { | |
320 | printk(KERN_ERR DRVNAME ": unable to register misc device\n"); | |
64d4062a | 321 | goto out_alloc; |
c283cf2c MC |
322 | } |
323 | goto out; | |
324 | ||
c283cf2c MC |
325 | out_alloc: |
326 | iounmap(ar7_wdt); | |
d7e9791b | 327 | out_mem_region: |
64d4062a | 328 | release_mem_region(ar7_regs_wdt->start, resource_size(ar7_regs_wdt)); |
c283cf2c MC |
329 | out: |
330 | return rc; | |
331 | } | |
332 | ||
64d4062a | 333 | static int __devexit ar7_wdt_remove(struct platform_device *pdev) |
c283cf2c MC |
334 | { |
335 | misc_deregister(&ar7_wdt_miscdev); | |
c283cf2c | 336 | iounmap(ar7_wdt); |
64d4062a FF |
337 | release_mem_region(ar7_regs_wdt->start, resource_size(ar7_regs_wdt)); |
338 | ||
339 | return 0; | |
340 | } | |
341 | ||
342 | static void ar7_wdt_shutdown(struct platform_device *pdev) | |
343 | { | |
344 | if (!nowayout) | |
345 | ar7_wdt_disable_wdt(); | |
346 | } | |
347 | ||
348 | static struct platform_driver ar7_wdt_driver = { | |
349 | .probe = ar7_wdt_probe, | |
350 | .remove = __devexit_p(ar7_wdt_remove), | |
351 | .shutdown = ar7_wdt_shutdown, | |
352 | .driver = { | |
353 | .owner = THIS_MODULE, | |
354 | .name = "ar7_wdt", | |
355 | }, | |
356 | }; | |
357 | ||
358 | static int __init ar7_wdt_init(void) | |
359 | { | |
360 | return platform_driver_register(&ar7_wdt_driver); | |
361 | } | |
362 | ||
363 | static void __exit ar7_wdt_cleanup(void) | |
364 | { | |
365 | platform_driver_unregister(&ar7_wdt_driver); | |
c283cf2c MC |
366 | } |
367 | ||
368 | module_init(ar7_wdt_init); | |
369 | module_exit(ar7_wdt_cleanup); |