Commit | Line | Data |
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a2f40ccd | 1 | /* |
a2f40ccd KG |
2 | * Watchdog timer for PowerPC Book-E systems |
3 | * | |
4 | * Author: Matthew McClintock | |
4c8d3d99 | 5 | * Maintainer: Kumar Gala <galak@kernel.crashing.org> |
a2f40ccd | 6 | * |
112e7546 | 7 | * Copyright 2005, 2008, 2010-2011 Freescale Semiconductor Inc. |
a2f40ccd KG |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License as published by the | |
11 | * Free Software Foundation; either version 2 of the License, or (at your | |
12 | * option) any later version. | |
13 | */ | |
14 | ||
27c766aa JP |
15 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
16 | ||
a2f40ccd KG |
17 | #include <linux/module.h> |
18 | #include <linux/fs.h> | |
f172ddc6 | 19 | #include <linux/smp.h> |
a2f40ccd KG |
20 | #include <linux/miscdevice.h> |
21 | #include <linux/notifier.h> | |
22 | #include <linux/watchdog.h> | |
00e9c205 | 23 | #include <linux/uaccess.h> |
a2f40ccd KG |
24 | |
25 | #include <asm/reg_booke.h> | |
39cdc4bf | 26 | #include <asm/system.h> |
dcfb7484 CF |
27 | #include <asm/time.h> |
28 | #include <asm/div64.h> | |
a2f40ccd | 29 | |
40ebbcbf | 30 | /* If the kernel parameter wdt=1, the watchdog will be enabled at boot. |
a2f40ccd KG |
31 | * Also, the wdt_period sets the watchdog timer period timeout. |
32 | * For E500 cpus the wdt_period sets which bit changing from 0->1 will | |
33 | * trigger a watchog timeout. This watchdog timeout will occur 3 times, the | |
34 | * first time nothing will happen, the second time a watchdog exception will | |
35 | * occur, and the final time the board will reset. | |
36 | */ | |
37 | ||
f172ddc6 | 38 | u32 booke_wdt_enabled; |
e0dc09ff | 39 | u32 booke_wdt_period = CONFIG_BOOKE_WDT_DEFAULT_TIMEOUT; |
a2f40ccd KG |
40 | |
41 | #ifdef CONFIG_FSL_BOOKE | |
dcfb7484 | 42 | #define WDTP(x) ((((x)&0x3)<<30)|(((x)&0x3c)<<15)) |
0fb06571 | 43 | #define WDTP_MASK (WDTP(0x3f)) |
a2f40ccd KG |
44 | #else |
45 | #define WDTP(x) (TCR_WP(x)) | |
0a0e9e0c | 46 | #define WDTP_MASK (TCR_WP_MASK) |
a2f40ccd KG |
47 | #endif |
48 | ||
f172ddc6 CG |
49 | static DEFINE_SPINLOCK(booke_wdt_lock); |
50 | ||
dcfb7484 CF |
51 | /* For the specified period, determine the number of seconds |
52 | * corresponding to the reset time. There will be a watchdog | |
53 | * exception at approximately 3/5 of this time. | |
54 | * | |
55 | * The formula to calculate this is given by: | |
56 | * 2.5 * (2^(63-period+1)) / timebase_freq | |
57 | * | |
58 | * In order to simplify things, we assume that period is | |
59 | * at least 1. This will still result in a very long timeout. | |
60 | */ | |
61 | static unsigned long long period_to_sec(unsigned int period) | |
62 | { | |
63 | unsigned long long tmp = 1ULL << (64 - period); | |
64 | unsigned long tmp2 = ppc_tb_freq; | |
65 | ||
66 | /* tmp may be a very large number and we don't want to overflow, | |
67 | * so divide the timebase freq instead of multiplying tmp | |
68 | */ | |
69 | tmp2 = tmp2 / 5 * 2; | |
70 | ||
71 | do_div(tmp, tmp2); | |
72 | return tmp; | |
73 | } | |
74 | ||
75 | /* | |
76 | * This procedure will find the highest period which will give a timeout | |
77 | * greater than the one required. e.g. for a bus speed of 66666666 and | |
78 | * and a parameter of 2 secs, then this procedure will return a value of 38. | |
79 | */ | |
80 | static unsigned int sec_to_period(unsigned int secs) | |
81 | { | |
82 | unsigned int period; | |
83 | for (period = 63; period > 0; period--) { | |
84 | if (period_to_sec(period) >= secs) | |
85 | return period; | |
86 | } | |
87 | return 0; | |
88 | } | |
89 | ||
6ae98ed1 RV |
90 | static void __booke_wdt_set(void *data) |
91 | { | |
92 | u32 val; | |
93 | ||
94 | val = mfspr(SPRN_TCR); | |
95 | val &= ~WDTP_MASK; | |
96 | val |= WDTP(booke_wdt_period); | |
97 | ||
98 | mtspr(SPRN_TCR, val); | |
99 | } | |
100 | ||
101 | static void booke_wdt_set(void) | |
102 | { | |
103 | on_each_cpu(__booke_wdt_set, NULL, 0); | |
104 | } | |
105 | ||
f172ddc6 | 106 | static void __booke_wdt_ping(void *data) |
f31909c0 SR |
107 | { |
108 | mtspr(SPRN_TSR, TSR_ENW|TSR_WIS); | |
109 | } | |
110 | ||
f172ddc6 CG |
111 | static void booke_wdt_ping(void) |
112 | { | |
f6f88e9b | 113 | on_each_cpu(__booke_wdt_ping, NULL, 0); |
f172ddc6 CG |
114 | } |
115 | ||
116 | static void __booke_wdt_enable(void *data) | |
a2f40ccd KG |
117 | { |
118 | u32 val; | |
119 | ||
f31909c0 | 120 | /* clear status before enabling watchdog */ |
f172ddc6 | 121 | __booke_wdt_ping(NULL); |
a2f40ccd | 122 | val = mfspr(SPRN_TCR); |
0a0e9e0c | 123 | val &= ~WDTP_MASK; |
39cdc4bf | 124 | val |= (TCR_WIE|TCR_WRC(WRC_CHIP)|WDTP(booke_wdt_period)); |
a2f40ccd KG |
125 | |
126 | mtspr(SPRN_TCR, val); | |
127 | } | |
128 | ||
fbdd7144 TT |
129 | /** |
130 | * booke_wdt_disable - disable the watchdog on the given CPU | |
131 | * | |
132 | * This function is called on each CPU. It disables the watchdog on that CPU. | |
133 | * | |
134 | * TCR[WRC] cannot be changed once it has been set to non-zero, but we can | |
135 | * effectively disable the watchdog by setting its period to the maximum value. | |
136 | */ | |
137 | static void __booke_wdt_disable(void *data) | |
138 | { | |
139 | u32 val; | |
140 | ||
141 | val = mfspr(SPRN_TCR); | |
142 | val &= ~(TCR_WIE | WDTP_MASK); | |
143 | mtspr(SPRN_TCR, val); | |
144 | ||
145 | /* clear status to make sure nothing is pending */ | |
146 | __booke_wdt_ping(NULL); | |
147 | ||
148 | } | |
149 | ||
f172ddc6 | 150 | static ssize_t booke_wdt_write(struct file *file, const char __user *buf, |
a2f40ccd KG |
151 | size_t count, loff_t *ppos) |
152 | { | |
153 | booke_wdt_ping(); | |
154 | return count; | |
155 | } | |
156 | ||
d8d8b63b | 157 | static struct watchdog_info ident = { |
f172ddc6 CG |
158 | .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, |
159 | .identity = "PowerPC Book-E Watchdog", | |
a2f40ccd KG |
160 | }; |
161 | ||
00e9c205 AC |
162 | static long booke_wdt_ioctl(struct file *file, |
163 | unsigned int cmd, unsigned long arg) | |
a2f40ccd KG |
164 | { |
165 | u32 tmp = 0; | |
538bacf8 | 166 | u32 __user *p = (u32 __user *)arg; |
a2f40ccd KG |
167 | |
168 | switch (cmd) { | |
169 | case WDIOC_GETSUPPORT: | |
dcfb7484 | 170 | if (copy_to_user((void *)arg, &ident, sizeof(ident))) |
a2f40ccd KG |
171 | return -EFAULT; |
172 | case WDIOC_GETSTATUS: | |
8b18085a | 173 | return put_user(0, p); |
a2f40ccd KG |
174 | case WDIOC_GETBOOTSTATUS: |
175 | /* XXX: something is clearing TSR */ | |
176 | tmp = mfspr(SPRN_TSR) & TSR_WRS(3); | |
8b18085a WVS |
177 | /* returns CARDRESET if last reset was caused by the WDT */ |
178 | return (tmp ? WDIOF_CARDRESET : 0); | |
0c06090c WVS |
179 | case WDIOC_SETOPTIONS: |
180 | if (get_user(tmp, p)) | |
181 | return -EINVAL; | |
182 | if (tmp == WDIOS_ENABLECARD) { | |
183 | booke_wdt_ping(); | |
184 | break; | |
185 | } else | |
186 | return -EINVAL; | |
187 | return 0; | |
a2f40ccd KG |
188 | case WDIOC_KEEPALIVE: |
189 | booke_wdt_ping(); | |
190 | return 0; | |
191 | case WDIOC_SETTIMEOUT: | |
dcfb7484 | 192 | if (get_user(tmp, p)) |
a2f40ccd | 193 | return -EFAULT; |
dcfb7484 CF |
194 | #ifdef CONFIG_FSL_BOOKE |
195 | /* period of 1 gives the largest possible timeout */ | |
196 | if (tmp > period_to_sec(1)) | |
197 | return -EINVAL; | |
198 | booke_wdt_period = sec_to_period(tmp); | |
199 | #else | |
200 | booke_wdt_period = tmp; | |
201 | #endif | |
6ae98ed1 | 202 | booke_wdt_set(); |
741b9c7d | 203 | /* Fall */ |
a2f40ccd | 204 | case WDIOC_GETTIMEOUT: |
741b9c7d DA |
205 | #ifdef CONFIG_FSL_BOOKE |
206 | return put_user(period_to_sec(booke_wdt_period), p); | |
207 | #else | |
538bacf8 | 208 | return put_user(booke_wdt_period, p); |
741b9c7d | 209 | #endif |
a2f40ccd | 210 | default: |
795b89d2 | 211 | return -ENOTTY; |
a2f40ccd KG |
212 | } |
213 | ||
214 | return 0; | |
215 | } | |
f172ddc6 | 216 | |
5d63c134 TT |
217 | /* wdt_is_active stores wether or not the /dev/watchdog device is opened */ |
218 | static unsigned long wdt_is_active; | |
219 | ||
f172ddc6 | 220 | static int booke_wdt_open(struct inode *inode, struct file *file) |
a2f40ccd | 221 | { |
5d63c134 TT |
222 | /* /dev/watchdog can only be opened once */ |
223 | if (test_and_set_bit(0, &wdt_is_active)) | |
224 | return -EBUSY; | |
225 | ||
f172ddc6 | 226 | spin_lock(&booke_wdt_lock); |
39cdc4bf KG |
227 | if (booke_wdt_enabled == 0) { |
228 | booke_wdt_enabled = 1; | |
f6f88e9b | 229 | on_each_cpu(__booke_wdt_enable, NULL, 0); |
27c766aa JP |
230 | pr_debug("watchdog enabled (timeout = %llu sec)\n", |
231 | period_to_sec(booke_wdt_period)); | |
a2f40ccd | 232 | } |
f172ddc6 | 233 | spin_unlock(&booke_wdt_lock); |
a2f40ccd | 234 | |
ec9505a7 | 235 | return nonseekable_open(inode, file); |
a2f40ccd KG |
236 | } |
237 | ||
fbdd7144 TT |
238 | static int booke_wdt_release(struct inode *inode, struct file *file) |
239 | { | |
5d63c134 TT |
240 | #ifndef CONFIG_WATCHDOG_NOWAYOUT |
241 | /* Normally, the watchdog is disabled when /dev/watchdog is closed, but | |
242 | * if CONFIG_WATCHDOG_NOWAYOUT is defined, then it means that the | |
243 | * watchdog should remain enabled. So we disable it only if | |
244 | * CONFIG_WATCHDOG_NOWAYOUT is not defined. | |
245 | */ | |
fbdd7144 TT |
246 | on_each_cpu(__booke_wdt_disable, NULL, 0); |
247 | booke_wdt_enabled = 0; | |
27c766aa | 248 | pr_debug("watchdog disabled\n"); |
5d63c134 TT |
249 | #endif |
250 | ||
251 | clear_bit(0, &wdt_is_active); | |
fbdd7144 TT |
252 | |
253 | return 0; | |
254 | } | |
255 | ||
62322d25 | 256 | static const struct file_operations booke_wdt_fops = { |
f172ddc6 CG |
257 | .owner = THIS_MODULE, |
258 | .llseek = no_llseek, | |
259 | .write = booke_wdt_write, | |
00e9c205 | 260 | .unlocked_ioctl = booke_wdt_ioctl, |
f172ddc6 | 261 | .open = booke_wdt_open, |
fbdd7144 | 262 | .release = booke_wdt_release, |
a2f40ccd KG |
263 | }; |
264 | ||
265 | static struct miscdevice booke_wdt_miscdev = { | |
f172ddc6 CG |
266 | .minor = WATCHDOG_MINOR, |
267 | .name = "watchdog", | |
268 | .fops = &booke_wdt_fops, | |
a2f40ccd KG |
269 | }; |
270 | ||
271 | static void __exit booke_wdt_exit(void) | |
272 | { | |
273 | misc_deregister(&booke_wdt_miscdev); | |
274 | } | |
275 | ||
a2f40ccd KG |
276 | static int __init booke_wdt_init(void) |
277 | { | |
278 | int ret = 0; | |
279 | ||
27c766aa | 280 | pr_info("powerpc book-e watchdog driver loaded\n"); |
a78719c3 | 281 | ident.firmware_version = cur_cpu_spec->pvr_value; |
a2f40ccd KG |
282 | |
283 | ret = misc_register(&booke_wdt_miscdev); | |
284 | if (ret) { | |
27c766aa | 285 | pr_err("cannot register device (minor=%u, ret=%i)\n", |
112e7546 | 286 | WATCHDOG_MINOR, ret); |
a2f40ccd KG |
287 | return ret; |
288 | } | |
289 | ||
f172ddc6 | 290 | spin_lock(&booke_wdt_lock); |
39cdc4bf | 291 | if (booke_wdt_enabled == 1) { |
27c766aa | 292 | pr_info("watchdog enabled (timeout = %llu sec)\n", |
112e7546 | 293 | period_to_sec(booke_wdt_period)); |
f6f88e9b | 294 | on_each_cpu(__booke_wdt_enable, NULL, 0); |
a2f40ccd | 295 | } |
f172ddc6 | 296 | spin_unlock(&booke_wdt_lock); |
a2f40ccd KG |
297 | |
298 | return ret; | |
299 | } | |
fbdd7144 TT |
300 | |
301 | module_init(booke_wdt_init); | |
302 | module_exit(booke_wdt_exit); | |
303 | ||
304 | MODULE_DESCRIPTION("PowerPC Book-E watchdog driver"); | |
305 | MODULE_LICENSE("GPL"); |