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7d831bf5 VB |
1 | /* |
2 | * drivers/char/watchdog/davinci_wdt.c | |
3 | * | |
4 | * Watchdog driver for DaVinci DM644x/DM646x processors | |
5 | * | |
f48f3cea | 6 | * Copyright (C) 2006-2013 Texas Instruments. |
7d831bf5 VB |
7 | * |
8 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | |
9 | * the terms of the GNU General Public License version 2. This program | |
10 | * is licensed "as is" without any warranty of any kind, whether express | |
11 | * or implied. | |
12 | */ | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/moduleparam.h> | |
16 | #include <linux/types.h> | |
17 | #include <linux/kernel.h> | |
7d831bf5 VB |
18 | #include <linux/watchdog.h> |
19 | #include <linux/init.h> | |
7d831bf5 | 20 | #include <linux/platform_device.h> |
f78b0a8f | 21 | #include <linux/io.h> |
371d3525 | 22 | #include <linux/device.h> |
9fd868f4 | 23 | #include <linux/clk.h> |
6330c707 | 24 | #include <linux/err.h> |
7d831bf5 VB |
25 | |
26 | #define MODULE_NAME "DAVINCI-WDT: " | |
27 | ||
28 | #define DEFAULT_HEARTBEAT 60 | |
29 | #define MAX_HEARTBEAT 600 /* really the max margin is 264/27MHz*/ | |
30 | ||
31 | /* Timer register set definition */ | |
32 | #define PID12 (0x0) | |
33 | #define EMUMGT (0x4) | |
34 | #define TIM12 (0x10) | |
35 | #define TIM34 (0x14) | |
36 | #define PRD12 (0x18) | |
37 | #define PRD34 (0x1C) | |
38 | #define TCR (0x20) | |
39 | #define TGCR (0x24) | |
40 | #define WDTCR (0x28) | |
41 | ||
42 | /* TCR bit definitions */ | |
43 | #define ENAMODE12_DISABLED (0 << 6) | |
44 | #define ENAMODE12_ONESHOT (1 << 6) | |
45 | #define ENAMODE12_PERIODIC (2 << 6) | |
46 | ||
47 | /* TGCR bit definitions */ | |
48 | #define TIM12RS_UNRESET (1 << 0) | |
49 | #define TIM34RS_UNRESET (1 << 1) | |
50 | #define TIMMODE_64BIT_WDOG (2 << 2) | |
51 | ||
52 | /* WDTCR bit definitions */ | |
53 | #define WDEN (1 << 14) | |
54 | #define WDFLAG (1 << 15) | |
55 | #define WDKEY_SEQ0 (0xa5c6 << 16) | |
56 | #define WDKEY_SEQ1 (0xda7e << 16) | |
57 | ||
f48f3cea | 58 | static int heartbeat; |
6d9a6cf5 IK |
59 | |
60 | /* | |
61 | * struct to hold data for each WDT device | |
62 | * @base - base io address of WD device | |
63 | * @clk - source clock of WDT | |
64 | * @wdd - hold watchdog device as is in WDT core | |
65 | */ | |
66 | struct davinci_wdt_device { | |
67 | void __iomem *base; | |
68 | struct clk *clk; | |
69 | struct watchdog_device wdd; | |
70 | }; | |
7d831bf5 | 71 | |
f48f3cea | 72 | static int davinci_wdt_start(struct watchdog_device *wdd) |
7d831bf5 VB |
73 | { |
74 | u32 tgcr; | |
75 | u32 timer_margin; | |
9fd868f4 | 76 | unsigned long wdt_freq; |
6d9a6cf5 | 77 | struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd); |
9fd868f4 | 78 | |
6d9a6cf5 | 79 | wdt_freq = clk_get_rate(davinci_wdt->clk); |
7d831bf5 | 80 | |
7d831bf5 | 81 | /* disable, internal clock source */ |
6d9a6cf5 | 82 | iowrite32(0, davinci_wdt->base + TCR); |
7d831bf5 | 83 | /* reset timer, set mode to 64-bit watchdog, and unreset */ |
6d9a6cf5 | 84 | iowrite32(0, davinci_wdt->base + TGCR); |
7d831bf5 | 85 | tgcr = TIMMODE_64BIT_WDOG | TIM12RS_UNRESET | TIM34RS_UNRESET; |
6d9a6cf5 | 86 | iowrite32(tgcr, davinci_wdt->base + TGCR); |
7d831bf5 | 87 | /* clear counter regs */ |
6d9a6cf5 IK |
88 | iowrite32(0, davinci_wdt->base + TIM12); |
89 | iowrite32(0, davinci_wdt->base + TIM34); | |
7d831bf5 | 90 | /* set timeout period */ |
f48f3cea | 91 | timer_margin = (((u64)wdd->timeout * wdt_freq) & 0xffffffff); |
6d9a6cf5 | 92 | iowrite32(timer_margin, davinci_wdt->base + PRD12); |
f48f3cea | 93 | timer_margin = (((u64)wdd->timeout * wdt_freq) >> 32); |
6d9a6cf5 | 94 | iowrite32(timer_margin, davinci_wdt->base + PRD34); |
7d831bf5 | 95 | /* enable run continuously */ |
6d9a6cf5 | 96 | iowrite32(ENAMODE12_PERIODIC, davinci_wdt->base + TCR); |
7d831bf5 VB |
97 | /* Once the WDT is in pre-active state write to |
98 | * TIM12, TIM34, PRD12, PRD34, TCR, TGCR, WDTCR are | |
99 | * write protected (except for the WDKEY field) | |
100 | */ | |
101 | /* put watchdog in pre-active state */ | |
6d9a6cf5 | 102 | iowrite32(WDKEY_SEQ0 | WDEN, davinci_wdt->base + WDTCR); |
7d831bf5 | 103 | /* put watchdog in active state */ |
6d9a6cf5 | 104 | iowrite32(WDKEY_SEQ1 | WDEN, davinci_wdt->base + WDTCR); |
f48f3cea | 105 | return 0; |
7d831bf5 VB |
106 | } |
107 | ||
f48f3cea | 108 | static int davinci_wdt_ping(struct watchdog_device *wdd) |
7d831bf5 | 109 | { |
6d9a6cf5 IK |
110 | struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd); |
111 | ||
f48f3cea | 112 | /* put watchdog in service state */ |
6d9a6cf5 | 113 | iowrite32(WDKEY_SEQ0, davinci_wdt->base + WDTCR); |
f48f3cea | 114 | /* put watchdog in active state */ |
6d9a6cf5 | 115 | iowrite32(WDKEY_SEQ1, davinci_wdt->base + WDTCR); |
f48f3cea | 116 | return 0; |
7d831bf5 VB |
117 | } |
118 | ||
f48f3cea | 119 | static const struct watchdog_info davinci_wdt_info = { |
f1a08cc9 | 120 | .options = WDIOF_KEEPALIVEPING, |
7d831bf5 VB |
121 | .identity = "DaVinci Watchdog", |
122 | }; | |
123 | ||
f48f3cea IK |
124 | static const struct watchdog_ops davinci_wdt_ops = { |
125 | .owner = THIS_MODULE, | |
126 | .start = davinci_wdt_start, | |
127 | .stop = davinci_wdt_ping, | |
128 | .ping = davinci_wdt_ping, | |
7d831bf5 VB |
129 | }; |
130 | ||
2d991a16 | 131 | static int davinci_wdt_probe(struct platform_device *pdev) |
7d831bf5 | 132 | { |
e20880e6 | 133 | int ret = 0; |
371d3525 | 134 | struct device *dev = &pdev->dev; |
e20880e6 | 135 | struct resource *wdt_mem; |
f48f3cea | 136 | struct watchdog_device *wdd; |
6d9a6cf5 IK |
137 | struct davinci_wdt_device *davinci_wdt; |
138 | ||
139 | davinci_wdt = devm_kzalloc(dev, sizeof(*davinci_wdt), GFP_KERNEL); | |
140 | if (!davinci_wdt) | |
141 | return -ENOMEM; | |
7d831bf5 | 142 | |
6d9a6cf5 IK |
143 | davinci_wdt->clk = devm_clk_get(dev, NULL); |
144 | if (WARN_ON(IS_ERR(davinci_wdt->clk))) | |
145 | return PTR_ERR(davinci_wdt->clk); | |
9fd868f4 | 146 | |
6d9a6cf5 | 147 | clk_prepare_enable(davinci_wdt->clk); |
9fd868f4 | 148 | |
6d9a6cf5 IK |
149 | platform_set_drvdata(pdev, davinci_wdt); |
150 | ||
151 | wdd = &davinci_wdt->wdd; | |
f48f3cea IK |
152 | wdd->info = &davinci_wdt_info; |
153 | wdd->ops = &davinci_wdt_ops; | |
154 | wdd->min_timeout = 1; | |
155 | wdd->max_timeout = MAX_HEARTBEAT; | |
156 | wdd->timeout = DEFAULT_HEARTBEAT; | |
157 | ||
158 | watchdog_init_timeout(wdd, heartbeat, dev); | |
159 | ||
160 | dev_info(dev, "heartbeat %d sec\n", wdd->timeout); | |
7d831bf5 | 161 | |
6d9a6cf5 | 162 | watchdog_set_drvdata(wdd, davinci_wdt); |
f48f3cea | 163 | watchdog_set_nowayout(wdd, 1); |
7d831bf5 | 164 | |
f712eacf | 165 | wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
6d9a6cf5 IK |
166 | davinci_wdt->base = devm_ioremap_resource(dev, wdt_mem); |
167 | if (IS_ERR(davinci_wdt->base)) | |
168 | return PTR_ERR(davinci_wdt->base); | |
7d831bf5 | 169 | |
f48f3cea IK |
170 | ret = watchdog_register_device(wdd); |
171 | if (ret < 0) | |
172 | dev_err(dev, "cannot register watchdog device\n"); | |
7d831bf5 VB |
173 | |
174 | return ret; | |
175 | } | |
176 | ||
4b12b896 | 177 | static int davinci_wdt_remove(struct platform_device *pdev) |
7d831bf5 | 178 | { |
6d9a6cf5 IK |
179 | struct davinci_wdt_device *davinci_wdt = platform_get_drvdata(pdev); |
180 | ||
181 | watchdog_unregister_device(&davinci_wdt->wdd); | |
182 | clk_disable_unprepare(davinci_wdt->clk); | |
9fd868f4 | 183 | |
7d831bf5 VB |
184 | return 0; |
185 | } | |
186 | ||
902e2e7d MK |
187 | static const struct of_device_id davinci_wdt_of_match[] = { |
188 | { .compatible = "ti,davinci-wdt", }, | |
189 | {}, | |
190 | }; | |
191 | MODULE_DEVICE_TABLE(of, davinci_wdt_of_match); | |
192 | ||
7d831bf5 VB |
193 | static struct platform_driver platform_wdt_driver = { |
194 | .driver = { | |
84374812 | 195 | .name = "davinci-wdt", |
f37d193c | 196 | .owner = THIS_MODULE, |
902e2e7d | 197 | .of_match_table = davinci_wdt_of_match, |
7d831bf5 VB |
198 | }, |
199 | .probe = davinci_wdt_probe, | |
82268714 | 200 | .remove = davinci_wdt_remove, |
7d831bf5 VB |
201 | }; |
202 | ||
b8ec6118 | 203 | module_platform_driver(platform_wdt_driver); |
7d831bf5 VB |
204 | |
205 | MODULE_AUTHOR("Texas Instruments"); | |
206 | MODULE_DESCRIPTION("DaVinci Watchdog Driver"); | |
207 | ||
208 | module_param(heartbeat, int, 0); | |
209 | MODULE_PARM_DESC(heartbeat, | |
210 | "Watchdog heartbeat period in seconds from 1 to " | |
211 | __MODULE_STRING(MAX_HEARTBEAT) ", default " | |
212 | __MODULE_STRING(DEFAULT_HEARTBEAT)); | |
213 | ||
214 | MODULE_LICENSE("GPL"); | |
84374812 | 215 | MODULE_ALIAS("platform:davinci-wdt"); |