Commit | Line | Data |
---|---|---|
c9353ae1 JI |
1 | /* |
2 | * Copyright 2010-2011 Picochip Ltd., Jamie Iles | |
3 | * http://www.picochip.com | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version | |
8 | * 2 of the License, or (at your option) any later version. | |
9 | * | |
10 | * This file implements a driver for the Synopsys DesignWare watchdog device | |
58a251f2 | 11 | * in the many subsystems. The watchdog has 16 different timeout periods |
c9353ae1 JI |
12 | * and these are a function of the input clock frequency. |
13 | * | |
14 | * The DesignWare watchdog cannot be stopped once it has been started so we | |
f29a72c2 GR |
15 | * do not implement a stop function. The watchdog core will continue to send |
16 | * heartbeat requests after the watchdog device has been closed. | |
c9353ae1 | 17 | */ |
27c766aa JP |
18 | |
19 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
c9353ae1 JI |
20 | |
21 | #include <linux/bitops.h> | |
22 | #include <linux/clk.h> | |
31228f43 | 23 | #include <linux/delay.h> |
c9353ae1 | 24 | #include <linux/err.h> |
c9353ae1 JI |
25 | #include <linux/io.h> |
26 | #include <linux/kernel.h> | |
c9353ae1 JI |
27 | #include <linux/module.h> |
28 | #include <linux/moduleparam.h> | |
31228f43 | 29 | #include <linux/notifier.h> |
58e56373 | 30 | #include <linux/of.h> |
c9353ae1 JI |
31 | #include <linux/pm.h> |
32 | #include <linux/platform_device.h> | |
31228f43 | 33 | #include <linux/reboot.h> |
c9353ae1 JI |
34 | #include <linux/watchdog.h> |
35 | ||
36 | #define WDOG_CONTROL_REG_OFFSET 0x00 | |
37 | #define WDOG_CONTROL_REG_WDT_EN_MASK 0x01 | |
38 | #define WDOG_TIMEOUT_RANGE_REG_OFFSET 0x04 | |
dfa07141 | 39 | #define WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT 4 |
c9353ae1 JI |
40 | #define WDOG_CURRENT_COUNT_REG_OFFSET 0x08 |
41 | #define WDOG_COUNTER_RESTART_REG_OFFSET 0x0c | |
42 | #define WDOG_COUNTER_RESTART_KICK_VALUE 0x76 | |
43 | ||
44 | /* The maximum TOP (timeout period) value that can be set in the watchdog. */ | |
45 | #define DW_WDT_MAX_TOP 15 | |
46 | ||
b5ade9bc DA |
47 | #define DW_WDT_DEFAULT_SECONDS 30 |
48 | ||
86a1e189 WVS |
49 | static bool nowayout = WATCHDOG_NOWAYOUT; |
50 | module_param(nowayout, bool, 0); | |
c9353ae1 JI |
51 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started " |
52 | "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
53 | ||
f29a72c2 | 54 | struct dw_wdt { |
c9353ae1 JI |
55 | void __iomem *regs; |
56 | struct clk *clk; | |
31228f43 | 57 | struct notifier_block restart_handler; |
f29a72c2 GR |
58 | struct watchdog_device wdd; |
59 | }; | |
60 | ||
61 | #define to_dw_wdt(wdd) container_of(wdd, struct dw_wdt, wdd) | |
c9353ae1 | 62 | |
f29a72c2 | 63 | static inline int dw_wdt_is_enabled(struct dw_wdt *dw_wdt) |
c9353ae1 | 64 | { |
f29a72c2 | 65 | return readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET) & |
c9353ae1 JI |
66 | WDOG_CONTROL_REG_WDT_EN_MASK; |
67 | } | |
68 | ||
f29a72c2 | 69 | static inline int dw_wdt_top_in_seconds(struct dw_wdt *dw_wdt, unsigned top) |
c9353ae1 JI |
70 | { |
71 | /* | |
72 | * There are 16 possible timeout values in 0..15 where the number of | |
73 | * cycles is 2 ^ (16 + i) and the watchdog counts down. | |
74 | */ | |
f29a72c2 | 75 | return (1U << (16 + top)) / clk_get_rate(dw_wdt->clk); |
c9353ae1 JI |
76 | } |
77 | ||
f29a72c2 | 78 | static int dw_wdt_get_top(struct dw_wdt *dw_wdt) |
c9353ae1 | 79 | { |
f29a72c2 | 80 | int top = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET) & 0xF; |
c9353ae1 | 81 | |
f29a72c2 | 82 | return dw_wdt_top_in_seconds(dw_wdt, top); |
c9353ae1 JI |
83 | } |
84 | ||
f29a72c2 | 85 | static int dw_wdt_ping(struct watchdog_device *wdd) |
c9353ae1 | 86 | { |
f29a72c2 | 87 | struct dw_wdt *dw_wdt = to_dw_wdt(wdd); |
c9353ae1 | 88 | |
f29a72c2 | 89 | writel(WDOG_COUNTER_RESTART_KICK_VALUE, dw_wdt->regs + |
a0085010 | 90 | WDOG_COUNTER_RESTART_REG_OFFSET); |
f29a72c2 GR |
91 | |
92 | return 0; | |
a0085010 DA |
93 | } |
94 | ||
f29a72c2 | 95 | static int dw_wdt_set_timeout(struct watchdog_device *wdd, unsigned int top_s) |
c9353ae1 | 96 | { |
f29a72c2 | 97 | struct dw_wdt *dw_wdt = to_dw_wdt(wdd); |
c9353ae1 JI |
98 | int i, top_val = DW_WDT_MAX_TOP; |
99 | ||
100 | /* | |
101 | * Iterate over the timeout values until we find the closest match. We | |
102 | * always look for >=. | |
103 | */ | |
104 | for (i = 0; i <= DW_WDT_MAX_TOP; ++i) | |
f29a72c2 | 105 | if (dw_wdt_top_in_seconds(dw_wdt, i) >= top_s) { |
c9353ae1 JI |
106 | top_val = i; |
107 | break; | |
108 | } | |
109 | ||
a0085010 DA |
110 | /* |
111 | * Set the new value in the watchdog. Some versions of dw_wdt | |
112 | * have have TOPINIT in the TIMEOUT_RANGE register (as per | |
113 | * CP_WDT_DUAL_TOP in WDT_COMP_PARAMS_1). On those we | |
114 | * effectively get a pat of the watchdog right here. | |
115 | */ | |
dfa07141 | 116 | writel(top_val | top_val << WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT, |
f29a72c2 | 117 | dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET); |
c9353ae1 | 118 | |
f29a72c2 | 119 | wdd->timeout = dw_wdt_top_in_seconds(dw_wdt, top_val); |
a0085010 | 120 | |
f29a72c2 GR |
121 | return 0; |
122 | } | |
123 | ||
124 | static int dw_wdt_start(struct watchdog_device *wdd) | |
125 | { | |
126 | struct dw_wdt *dw_wdt = to_dw_wdt(wdd); | |
127 | ||
128 | dw_wdt_set_timeout(wdd, wdd->timeout); | |
c9353ae1 | 129 | |
f29a72c2 GR |
130 | set_bit(WDOG_HW_RUNNING, &wdd->status); |
131 | ||
132 | writel(WDOG_CONTROL_REG_WDT_EN_MASK, | |
133 | dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); | |
134 | ||
135 | return 0; | |
c9353ae1 JI |
136 | } |
137 | ||
31228f43 | 138 | static int dw_wdt_restart_handle(struct notifier_block *this, |
f29a72c2 | 139 | unsigned long mode, void *cmd) |
31228f43 | 140 | { |
f29a72c2 | 141 | struct dw_wdt *dw_wdt; |
31228f43 JZ |
142 | u32 val; |
143 | ||
f29a72c2 GR |
144 | dw_wdt = container_of(this, struct dw_wdt, restart_handler); |
145 | ||
146 | writel(0, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET); | |
147 | val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); | |
31228f43 | 148 | if (val & WDOG_CONTROL_REG_WDT_EN_MASK) |
f29a72c2 GR |
149 | writel(WDOG_COUNTER_RESTART_KICK_VALUE, |
150 | dw_wdt->regs + WDOG_COUNTER_RESTART_REG_OFFSET); | |
31228f43 JZ |
151 | else |
152 | writel(WDOG_CONTROL_REG_WDT_EN_MASK, | |
f29a72c2 | 153 | dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); |
31228f43 JZ |
154 | |
155 | /* wait for reset to assert... */ | |
156 | mdelay(500); | |
157 | ||
158 | return NOTIFY_DONE; | |
159 | } | |
160 | ||
f29a72c2 | 161 | static unsigned int dw_wdt_get_timeleft(struct watchdog_device *wdd) |
c9353ae1 | 162 | { |
f29a72c2 | 163 | struct dw_wdt *dw_wdt = to_dw_wdt(wdd); |
c9353ae1 | 164 | |
f29a72c2 GR |
165 | return readl(dw_wdt->regs + WDOG_CURRENT_COUNT_REG_OFFSET) / |
166 | clk_get_rate(dw_wdt->clk); | |
c9353ae1 JI |
167 | } |
168 | ||
169 | static const struct watchdog_info dw_wdt_ident = { | |
170 | .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | | |
171 | WDIOF_MAGICCLOSE, | |
172 | .identity = "Synopsys DesignWare Watchdog", | |
173 | }; | |
174 | ||
f29a72c2 GR |
175 | static const struct watchdog_ops dw_wdt_ops = { |
176 | .owner = THIS_MODULE, | |
177 | .start = dw_wdt_start, | |
178 | .ping = dw_wdt_ping, | |
179 | .set_timeout = dw_wdt_set_timeout, | |
180 | .get_timeleft = dw_wdt_get_timeleft, | |
181 | }; | |
c9353ae1 | 182 | |
ad83c6cb | 183 | #ifdef CONFIG_PM_SLEEP |
c9353ae1 JI |
184 | static int dw_wdt_suspend(struct device *dev) |
185 | { | |
f29a72c2 GR |
186 | struct dw_wdt *dw_wdt = dev_get_drvdata(dev); |
187 | ||
188 | clk_disable_unprepare(dw_wdt->clk); | |
c9353ae1 JI |
189 | |
190 | return 0; | |
191 | } | |
192 | ||
193 | static int dw_wdt_resume(struct device *dev) | |
194 | { | |
f29a72c2 GR |
195 | struct dw_wdt *dw_wdt = dev_get_drvdata(dev); |
196 | int err = clk_prepare_enable(dw_wdt->clk); | |
c9353ae1 JI |
197 | |
198 | if (err) | |
199 | return err; | |
200 | ||
f29a72c2 | 201 | dw_wdt_ping(&dw_wdt->wdd); |
c9353ae1 JI |
202 | |
203 | return 0; | |
204 | } | |
ad83c6cb | 205 | #endif /* CONFIG_PM_SLEEP */ |
c9353ae1 | 206 | |
ad83c6cb | 207 | static SIMPLE_DEV_PM_OPS(dw_wdt_pm_ops, dw_wdt_suspend, dw_wdt_resume); |
c9353ae1 | 208 | |
2d991a16 | 209 | static int dw_wdt_drv_probe(struct platform_device *pdev) |
c9353ae1 | 210 | { |
f29a72c2 GR |
211 | struct device *dev = &pdev->dev; |
212 | struct watchdog_device *wdd; | |
213 | struct dw_wdt *dw_wdt; | |
214 | struct resource *mem; | |
c9353ae1 | 215 | int ret; |
c9353ae1 | 216 | |
f29a72c2 GR |
217 | dw_wdt = devm_kzalloc(dev, sizeof(*dw_wdt), GFP_KERNEL); |
218 | if (!dw_wdt) | |
219 | return -ENOMEM; | |
220 | ||
221 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
222 | dw_wdt->regs = devm_ioremap_resource(dev, mem); | |
223 | if (IS_ERR(dw_wdt->regs)) | |
224 | return PTR_ERR(dw_wdt->regs); | |
c9353ae1 | 225 | |
f29a72c2 GR |
226 | dw_wdt->clk = devm_clk_get(dev, NULL); |
227 | if (IS_ERR(dw_wdt->clk)) | |
228 | return PTR_ERR(dw_wdt->clk); | |
c9353ae1 | 229 | |
f29a72c2 | 230 | ret = clk_prepare_enable(dw_wdt->clk); |
c9353ae1 | 231 | if (ret) |
cf3cc8c2 | 232 | return ret; |
c9353ae1 | 233 | |
f29a72c2 GR |
234 | wdd = &dw_wdt->wdd; |
235 | wdd->info = &dw_wdt_ident; | |
236 | wdd->ops = &dw_wdt_ops; | |
237 | wdd->min_timeout = 1; | |
238 | wdd->max_hw_heartbeat_ms = | |
239 | dw_wdt_top_in_seconds(dw_wdt, DW_WDT_MAX_TOP) * 1000; | |
240 | wdd->parent = dev; | |
241 | ||
242 | watchdog_set_drvdata(wdd, dw_wdt); | |
243 | watchdog_set_nowayout(wdd, nowayout); | |
244 | watchdog_init_timeout(wdd, 0, dev); | |
245 | ||
246 | /* | |
247 | * If the watchdog is already running, use its already configured | |
248 | * timeout. Otherwise use the default or the value provided through | |
249 | * devicetree. | |
250 | */ | |
251 | if (dw_wdt_is_enabled(dw_wdt)) { | |
252 | wdd->timeout = dw_wdt_get_top(dw_wdt); | |
253 | set_bit(WDOG_HW_RUNNING, &wdd->status); | |
254 | } else { | |
255 | wdd->timeout = DW_WDT_DEFAULT_SECONDS; | |
256 | watchdog_init_timeout(wdd, 0, dev); | |
257 | } | |
258 | ||
259 | platform_set_drvdata(pdev, dw_wdt); | |
260 | ||
261 | ret = watchdog_register_device(wdd); | |
c9353ae1 JI |
262 | if (ret) |
263 | goto out_disable_clk; | |
264 | ||
f29a72c2 GR |
265 | dw_wdt->restart_handler.notifier_call = dw_wdt_restart_handle; |
266 | dw_wdt->restart_handler.priority = 128; | |
267 | ret = register_restart_handler(&dw_wdt->restart_handler); | |
31228f43 JZ |
268 | if (ret) |
269 | pr_warn("cannot register restart handler\n"); | |
270 | ||
c9353ae1 JI |
271 | return 0; |
272 | ||
273 | out_disable_clk: | |
f29a72c2 | 274 | clk_disable_unprepare(dw_wdt->clk); |
c9353ae1 JI |
275 | return ret; |
276 | } | |
277 | ||
4b12b896 | 278 | static int dw_wdt_drv_remove(struct platform_device *pdev) |
c9353ae1 | 279 | { |
f29a72c2 | 280 | struct dw_wdt *dw_wdt = platform_get_drvdata(pdev); |
c9353ae1 | 281 | |
f29a72c2 GR |
282 | unregister_restart_handler(&dw_wdt->restart_handler); |
283 | watchdog_unregister_device(&dw_wdt->wdd); | |
284 | clk_disable_unprepare(dw_wdt->clk); | |
c9353ae1 JI |
285 | |
286 | return 0; | |
287 | } | |
288 | ||
58e56373 DN |
289 | #ifdef CONFIG_OF |
290 | static const struct of_device_id dw_wdt_of_match[] = { | |
291 | { .compatible = "snps,dw-wdt", }, | |
292 | { /* sentinel */ } | |
293 | }; | |
294 | MODULE_DEVICE_TABLE(of, dw_wdt_of_match); | |
295 | #endif | |
296 | ||
c9353ae1 JI |
297 | static struct platform_driver dw_wdt_driver = { |
298 | .probe = dw_wdt_drv_probe, | |
82268714 | 299 | .remove = dw_wdt_drv_remove, |
c9353ae1 JI |
300 | .driver = { |
301 | .name = "dw_wdt", | |
58e56373 | 302 | .of_match_table = of_match_ptr(dw_wdt_of_match), |
c9353ae1 | 303 | .pm = &dw_wdt_pm_ops, |
c9353ae1 JI |
304 | }, |
305 | }; | |
306 | ||
b8ec6118 | 307 | module_platform_driver(dw_wdt_driver); |
c9353ae1 JI |
308 | |
309 | MODULE_AUTHOR("Jamie Iles"); | |
310 | MODULE_DESCRIPTION("Synopsys DesignWare Watchdog Driver"); | |
311 | MODULE_LICENSE("GPL"); |