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96cb4eb0 GS |
1 | /*************************************************************************** |
2 | * Copyright (C) 2006 by Hans Edgington <hans@edgington.nl> * | |
3 | * Copyright (C) 2007-2009 Hans de Goede <hdegoede@redhat.com> * | |
4 | * Copyright (C) 2010 Giel van Schijndel <me@mortis.eu> * | |
5 | * * | |
6 | * This program is free software; you can redistribute it and/or modify * | |
7 | * it under the terms of the GNU General Public License as published by * | |
8 | * the Free Software Foundation; either version 2 of the License, or * | |
9 | * (at your option) any later version. * | |
10 | * * | |
11 | * This program is distributed in the hope that it will be useful, * | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * | |
14 | * GNU General Public License for more details. * | |
15 | * * | |
16 | * You should have received a copy of the GNU General Public License * | |
17 | * along with this program; if not, write to the * | |
18 | * Free Software Foundation, Inc., * | |
19 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * | |
20 | ***************************************************************************/ | |
21 | ||
27c766aa JP |
22 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
23 | ||
96cb4eb0 GS |
24 | #include <linux/err.h> |
25 | #include <linux/fs.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/ioport.h> | |
29 | #include <linux/miscdevice.h> | |
30 | #include <linux/module.h> | |
31 | #include <linux/mutex.h> | |
32 | #include <linux/notifier.h> | |
33 | #include <linux/reboot.h> | |
34 | #include <linux/uaccess.h> | |
35 | #include <linux/watchdog.h> | |
36 | ||
37 | #define DRVNAME "f71808e_wdt" | |
38 | ||
39 | #define SIO_F71808FG_LD_WDT 0x07 /* Watchdog timer logical device */ | |
40 | #define SIO_UNLOCK_KEY 0x87 /* Key to enable Super-I/O */ | |
85c130a8 | 41 | #define SIO_LOCK_KEY 0xAA /* Key to disable Super-I/O */ |
96cb4eb0 GS |
42 | |
43 | #define SIO_REG_LDSEL 0x07 /* Logical device select */ | |
44 | #define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */ | |
45 | #define SIO_REG_DEVREV 0x22 /* Device revision */ | |
46 | #define SIO_REG_MANID 0x23 /* Fintek ID (2 bytes) */ | |
7977ff6e | 47 | #define SIO_REG_ROM_ADDR_SEL 0x27 /* ROM address select */ |
f9a9f096 LB |
48 | #define SIO_REG_MFUNCT1 0x29 /* Multi function select 1 */ |
49 | #define SIO_REG_MFUNCT2 0x2a /* Multi function select 2 */ | |
50 | #define SIO_REG_MFUNCT3 0x2b /* Multi function select 3 */ | |
96cb4eb0 GS |
51 | #define SIO_REG_ENABLE 0x30 /* Logical device enable */ |
52 | #define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */ | |
53 | ||
54 | #define SIO_FINTEK_ID 0x1934 /* Manufacturers ID */ | |
f9a9f096 LB |
55 | #define SIO_F71808_ID 0x0901 /* Chipset ID */ |
56 | #define SIO_F71858_ID 0x0507 /* Chipset ID */ | |
96cb4eb0 | 57 | #define SIO_F71862_ID 0x0601 /* Chipset ID */ |
df278dac | 58 | #define SIO_F71869_ID 0x0814 /* Chipset ID */ |
3017020d | 59 | #define SIO_F71869A_ID 0x1007 /* Chipset ID */ |
96cb4eb0 GS |
60 | #define SIO_F71882_ID 0x0541 /* Chipset ID */ |
61 | #define SIO_F71889_ID 0x0723 /* Chipset ID */ | |
ea0c03e8 | 62 | #define SIO_F81865_ID 0x0704 /* Chipset ID */ |
96cb4eb0 | 63 | |
96cb4eb0 GS |
64 | #define F71808FG_REG_WDO_CONF 0xf0 |
65 | #define F71808FG_REG_WDT_CONF 0xf5 | |
66 | #define F71808FG_REG_WD_TIME 0xf6 | |
67 | ||
68 | #define F71808FG_FLAG_WDOUT_EN 7 | |
69 | ||
b97cb21a | 70 | #define F71808FG_FLAG_WDTMOUT_STS 6 |
96cb4eb0 GS |
71 | #define F71808FG_FLAG_WD_EN 5 |
72 | #define F71808FG_FLAG_WD_PULSE 4 | |
73 | #define F71808FG_FLAG_WD_UNIT 3 | |
74 | ||
ea0c03e8 KP |
75 | #define F81865_REG_WDO_CONF 0xfa |
76 | #define F81865_FLAG_WDOUT_EN 0 | |
77 | ||
96cb4eb0 GS |
78 | /* Default values */ |
79 | #define WATCHDOG_TIMEOUT 60 /* 1 minute default timeout */ | |
80 | #define WATCHDOG_MAX_TIMEOUT (60 * 255) | |
81 | #define WATCHDOG_PULSE_WIDTH 125 /* 125 ms, default pulse width for | |
82 | watchdog signal */ | |
7977ff6e LB |
83 | #define WATCHDOG_F71862FG_PIN 63 /* default watchdog reset output |
84 | pin number 63 */ | |
96cb4eb0 GS |
85 | |
86 | static unsigned short force_id; | |
87 | module_param(force_id, ushort, 0); | |
88 | MODULE_PARM_DESC(force_id, "Override the detected device ID"); | |
89 | ||
90 | static const int max_timeout = WATCHDOG_MAX_TIMEOUT; | |
f9a9f096 | 91 | static int timeout = WATCHDOG_TIMEOUT; /* default timeout in seconds */ |
96cb4eb0 GS |
92 | module_param(timeout, int, 0); |
93 | MODULE_PARM_DESC(timeout, | |
94 | "Watchdog timeout in seconds. 1<= timeout <=" | |
95 | __MODULE_STRING(WATCHDOG_MAX_TIMEOUT) " (default=" | |
96 | __MODULE_STRING(WATCHDOG_TIMEOUT) ")"); | |
97 | ||
98 | static unsigned int pulse_width = WATCHDOG_PULSE_WIDTH; | |
99 | module_param(pulse_width, uint, 0); | |
100 | MODULE_PARM_DESC(pulse_width, | |
101 | "Watchdog signal pulse width. 0(=level), 1 ms, 25 ms, 125 ms or 5000 ms" | |
102 | " (default=" __MODULE_STRING(WATCHDOG_PULSE_WIDTH) ")"); | |
103 | ||
7977ff6e LB |
104 | static unsigned int f71862fg_pin = WATCHDOG_F71862FG_PIN; |
105 | module_param(f71862fg_pin, uint, 0); | |
106 | MODULE_PARM_DESC(f71862fg_pin, | |
107 | "Watchdog f71862fg reset output pin configuration. Choose pin 56 or 63" | |
108 | " (default=" __MODULE_STRING(WATCHDOG_F71862FG_PIN)")"); | |
109 | ||
90ab5ee9 | 110 | static bool nowayout = WATCHDOG_NOWAYOUT; |
96cb4eb0 GS |
111 | module_param(nowayout, bool, 0444); |
112 | MODULE_PARM_DESC(nowayout, "Disable watchdog shutdown on close"); | |
113 | ||
114 | static unsigned int start_withtimeout; | |
115 | module_param(start_withtimeout, uint, 0); | |
116 | MODULE_PARM_DESC(start_withtimeout, "Start watchdog timer on module load with" | |
117 | " given initial timeout. Zero (default) disables this feature."); | |
118 | ||
ea0c03e8 | 119 | enum chips { f71808fg, f71858fg, f71862fg, f71869, f71882fg, f71889fg, f81865 }; |
96cb4eb0 GS |
120 | |
121 | static const char *f71808e_names[] = { | |
122 | "f71808fg", | |
123 | "f71858fg", | |
124 | "f71862fg", | |
df278dac | 125 | "f71869", |
96cb4eb0 GS |
126 | "f71882fg", |
127 | "f71889fg", | |
ea0c03e8 | 128 | "f81865", |
96cb4eb0 GS |
129 | }; |
130 | ||
131 | /* Super-I/O Function prototypes */ | |
132 | static inline int superio_inb(int base, int reg); | |
133 | static inline int superio_inw(int base, int reg); | |
134 | static inline void superio_outb(int base, int reg, u8 val); | |
135 | static inline void superio_set_bit(int base, int reg, int bit); | |
136 | static inline void superio_clear_bit(int base, int reg, int bit); | |
137 | static inline int superio_enter(int base); | |
138 | static inline void superio_select(int base, int ld); | |
139 | static inline void superio_exit(int base); | |
140 | ||
141 | struct watchdog_data { | |
142 | unsigned short sioaddr; | |
143 | enum chips type; | |
144 | unsigned long opened; | |
145 | struct mutex lock; | |
146 | char expect_close; | |
147 | struct watchdog_info ident; | |
148 | ||
149 | unsigned short timeout; | |
150 | u8 timer_val; /* content for the wd_time register */ | |
151 | char minutes_mode; | |
152 | u8 pulse_val; /* pulse width flag */ | |
153 | char pulse_mode; /* enable pulse output mode? */ | |
154 | char caused_reboot; /* last reboot was by the watchdog */ | |
155 | }; | |
156 | ||
157 | static struct watchdog_data watchdog = { | |
158 | .lock = __MUTEX_INITIALIZER(watchdog.lock), | |
159 | }; | |
160 | ||
161 | /* Super I/O functions */ | |
162 | static inline int superio_inb(int base, int reg) | |
163 | { | |
164 | outb(reg, base); | |
165 | return inb(base + 1); | |
166 | } | |
167 | ||
168 | static int superio_inw(int base, int reg) | |
169 | { | |
170 | int val; | |
171 | val = superio_inb(base, reg) << 8; | |
172 | val |= superio_inb(base, reg + 1); | |
173 | return val; | |
174 | } | |
175 | ||
176 | static inline void superio_outb(int base, int reg, u8 val) | |
177 | { | |
178 | outb(reg, base); | |
179 | outb(val, base + 1); | |
180 | } | |
181 | ||
182 | static inline void superio_set_bit(int base, int reg, int bit) | |
183 | { | |
184 | unsigned long val = superio_inb(base, reg); | |
185 | __set_bit(bit, &val); | |
186 | superio_outb(base, reg, val); | |
187 | } | |
188 | ||
189 | static inline void superio_clear_bit(int base, int reg, int bit) | |
190 | { | |
191 | unsigned long val = superio_inb(base, reg); | |
192 | __clear_bit(bit, &val); | |
193 | superio_outb(base, reg, val); | |
194 | } | |
195 | ||
196 | static inline int superio_enter(int base) | |
197 | { | |
198 | /* Don't step on other drivers' I/O space by accident */ | |
199 | if (!request_muxed_region(base, 2, DRVNAME)) { | |
27c766aa | 200 | pr_err("I/O address 0x%04x already in use\n", (int)base); |
96cb4eb0 GS |
201 | return -EBUSY; |
202 | } | |
203 | ||
3017020d | 204 | /* according to the datasheet the key must be sent twice! */ |
96cb4eb0 GS |
205 | outb(SIO_UNLOCK_KEY, base); |
206 | outb(SIO_UNLOCK_KEY, base); | |
207 | ||
208 | return 0; | |
209 | } | |
210 | ||
211 | static inline void superio_select(int base, int ld) | |
212 | { | |
213 | outb(SIO_REG_LDSEL, base); | |
214 | outb(ld, base + 1); | |
215 | } | |
216 | ||
217 | static inline void superio_exit(int base) | |
218 | { | |
219 | outb(SIO_LOCK_KEY, base); | |
220 | release_region(base, 2); | |
221 | } | |
222 | ||
223 | static int watchdog_set_timeout(int timeout) | |
224 | { | |
225 | if (timeout <= 0 | |
226 | || timeout > max_timeout) { | |
27c766aa | 227 | pr_err("watchdog timeout out of range\n"); |
96cb4eb0 GS |
228 | return -EINVAL; |
229 | } | |
230 | ||
231 | mutex_lock(&watchdog.lock); | |
232 | ||
233 | watchdog.timeout = timeout; | |
234 | if (timeout > 0xff) { | |
235 | watchdog.timer_val = DIV_ROUND_UP(timeout, 60); | |
236 | watchdog.minutes_mode = true; | |
237 | } else { | |
238 | watchdog.timer_val = timeout; | |
239 | watchdog.minutes_mode = false; | |
240 | } | |
241 | ||
242 | mutex_unlock(&watchdog.lock); | |
243 | ||
244 | return 0; | |
245 | } | |
246 | ||
247 | static int watchdog_set_pulse_width(unsigned int pw) | |
248 | { | |
249 | int err = 0; | |
250 | ||
251 | mutex_lock(&watchdog.lock); | |
252 | ||
253 | if (pw <= 1) { | |
254 | watchdog.pulse_val = 0; | |
255 | } else if (pw <= 25) { | |
256 | watchdog.pulse_val = 1; | |
257 | } else if (pw <= 125) { | |
258 | watchdog.pulse_val = 2; | |
259 | } else if (pw <= 5000) { | |
260 | watchdog.pulse_val = 3; | |
261 | } else { | |
27c766aa | 262 | pr_err("pulse width out of range\n"); |
96cb4eb0 GS |
263 | err = -EINVAL; |
264 | goto exit_unlock; | |
265 | } | |
266 | ||
267 | watchdog.pulse_mode = pw; | |
268 | ||
269 | exit_unlock: | |
270 | mutex_unlock(&watchdog.lock); | |
271 | return err; | |
272 | } | |
273 | ||
274 | static int watchdog_keepalive(void) | |
275 | { | |
276 | int err = 0; | |
277 | ||
278 | mutex_lock(&watchdog.lock); | |
279 | err = superio_enter(watchdog.sioaddr); | |
280 | if (err) | |
281 | goto exit_unlock; | |
282 | superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT); | |
283 | ||
284 | if (watchdog.minutes_mode) | |
285 | /* select minutes for timer units */ | |
286 | superio_set_bit(watchdog.sioaddr, F71808FG_REG_WDT_CONF, | |
287 | F71808FG_FLAG_WD_UNIT); | |
288 | else | |
289 | /* select seconds for timer units */ | |
290 | superio_clear_bit(watchdog.sioaddr, F71808FG_REG_WDT_CONF, | |
291 | F71808FG_FLAG_WD_UNIT); | |
292 | ||
293 | /* Set timer value */ | |
294 | superio_outb(watchdog.sioaddr, F71808FG_REG_WD_TIME, | |
295 | watchdog.timer_val); | |
296 | ||
297 | superio_exit(watchdog.sioaddr); | |
298 | ||
299 | exit_unlock: | |
300 | mutex_unlock(&watchdog.lock); | |
301 | return err; | |
302 | } | |
303 | ||
7977ff6e LB |
304 | static int f71862fg_pin_configure(unsigned short ioaddr) |
305 | { | |
306 | /* When ioaddr is non-zero the calling function has to take care of | |
307 | mutex handling and superio preparation! */ | |
308 | ||
309 | if (f71862fg_pin == 63) { | |
310 | if (ioaddr) { | |
311 | /* SPI must be disabled first to use this pin! */ | |
312 | superio_clear_bit(ioaddr, SIO_REG_ROM_ADDR_SEL, 6); | |
313 | superio_set_bit(ioaddr, SIO_REG_MFUNCT3, 4); | |
314 | } | |
315 | } else if (f71862fg_pin == 56) { | |
316 | if (ioaddr) | |
317 | superio_set_bit(ioaddr, SIO_REG_MFUNCT1, 1); | |
318 | } else { | |
27c766aa | 319 | pr_err("Invalid argument f71862fg_pin=%d\n", f71862fg_pin); |
7977ff6e LB |
320 | return -EINVAL; |
321 | } | |
322 | return 0; | |
323 | } | |
324 | ||
96cb4eb0 GS |
325 | static int watchdog_start(void) |
326 | { | |
327 | /* Make sure we don't die as soon as the watchdog is enabled below */ | |
328 | int err = watchdog_keepalive(); | |
329 | if (err) | |
330 | return err; | |
331 | ||
332 | mutex_lock(&watchdog.lock); | |
333 | err = superio_enter(watchdog.sioaddr); | |
334 | if (err) | |
335 | goto exit_unlock; | |
336 | superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT); | |
337 | ||
338 | /* Watchdog pin configuration */ | |
339 | switch (watchdog.type) { | |
340 | case f71808fg: | |
341 | /* Set pin 21 to GPIO23/WDTRST#, then to WDTRST# */ | |
f9a9f096 LB |
342 | superio_clear_bit(watchdog.sioaddr, SIO_REG_MFUNCT2, 3); |
343 | superio_clear_bit(watchdog.sioaddr, SIO_REG_MFUNCT3, 3); | |
96cb4eb0 GS |
344 | break; |
345 | ||
7977ff6e LB |
346 | case f71862fg: |
347 | err = f71862fg_pin_configure(watchdog.sioaddr); | |
348 | if (err) | |
349 | goto exit_superio; | |
350 | break; | |
351 | ||
df278dac MA |
352 | case f71869: |
353 | /* GPIO14 --> WDTRST# */ | |
354 | superio_clear_bit(watchdog.sioaddr, SIO_REG_MFUNCT1, 4); | |
355 | break; | |
356 | ||
96cb4eb0 GS |
357 | case f71882fg: |
358 | /* Set pin 56 to WDTRST# */ | |
f9a9f096 | 359 | superio_set_bit(watchdog.sioaddr, SIO_REG_MFUNCT1, 1); |
96cb4eb0 GS |
360 | break; |
361 | ||
dee00abb GS |
362 | case f71889fg: |
363 | /* set pin 40 to WDTRST# */ | |
f9a9f096 LB |
364 | superio_outb(watchdog.sioaddr, SIO_REG_MFUNCT3, |
365 | superio_inb(watchdog.sioaddr, SIO_REG_MFUNCT3) & 0xcf); | |
dee00abb GS |
366 | break; |
367 | ||
ea0c03e8 KP |
368 | case f81865: |
369 | /* Set pin 70 to WDTRST# */ | |
370 | superio_clear_bit(watchdog.sioaddr, SIO_REG_MFUNCT3, 5); | |
371 | break; | |
372 | ||
96cb4eb0 GS |
373 | default: |
374 | /* | |
375 | * 'default' label to shut up the compiler and catch | |
376 | * programmer errors | |
377 | */ | |
378 | err = -ENODEV; | |
379 | goto exit_superio; | |
380 | } | |
381 | ||
382 | superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT); | |
383 | superio_set_bit(watchdog.sioaddr, SIO_REG_ENABLE, 0); | |
ea0c03e8 KP |
384 | |
385 | if (watchdog.type == f81865) | |
386 | superio_set_bit(watchdog.sioaddr, F81865_REG_WDO_CONF, | |
387 | F81865_FLAG_WDOUT_EN); | |
388 | else | |
389 | superio_set_bit(watchdog.sioaddr, F71808FG_REG_WDO_CONF, | |
390 | F71808FG_FLAG_WDOUT_EN); | |
96cb4eb0 GS |
391 | |
392 | superio_set_bit(watchdog.sioaddr, F71808FG_REG_WDT_CONF, | |
393 | F71808FG_FLAG_WD_EN); | |
394 | ||
395 | if (watchdog.pulse_mode) { | |
396 | /* Select "pulse" output mode with given duration */ | |
397 | u8 wdt_conf = superio_inb(watchdog.sioaddr, | |
398 | F71808FG_REG_WDT_CONF); | |
399 | ||
400 | /* Set WD_PSWIDTH bits (1:0) */ | |
401 | wdt_conf = (wdt_conf & 0xfc) | (watchdog.pulse_val & 0x03); | |
402 | /* Set WD_PULSE to "pulse" mode */ | |
403 | wdt_conf |= BIT(F71808FG_FLAG_WD_PULSE); | |
404 | ||
405 | superio_outb(watchdog.sioaddr, F71808FG_REG_WDT_CONF, | |
406 | wdt_conf); | |
407 | } else { | |
408 | /* Select "level" output mode */ | |
409 | superio_clear_bit(watchdog.sioaddr, F71808FG_REG_WDT_CONF, | |
410 | F71808FG_FLAG_WD_PULSE); | |
411 | } | |
412 | ||
413 | exit_superio: | |
414 | superio_exit(watchdog.sioaddr); | |
415 | exit_unlock: | |
416 | mutex_unlock(&watchdog.lock); | |
417 | ||
418 | return err; | |
419 | } | |
420 | ||
421 | static int watchdog_stop(void) | |
422 | { | |
423 | int err = 0; | |
424 | ||
425 | mutex_lock(&watchdog.lock); | |
426 | err = superio_enter(watchdog.sioaddr); | |
427 | if (err) | |
428 | goto exit_unlock; | |
429 | superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT); | |
430 | ||
431 | superio_clear_bit(watchdog.sioaddr, F71808FG_REG_WDT_CONF, | |
432 | F71808FG_FLAG_WD_EN); | |
433 | ||
434 | superio_exit(watchdog.sioaddr); | |
435 | ||
436 | exit_unlock: | |
437 | mutex_unlock(&watchdog.lock); | |
438 | ||
439 | return err; | |
440 | } | |
441 | ||
442 | static int watchdog_get_status(void) | |
443 | { | |
444 | int status = 0; | |
445 | ||
446 | mutex_lock(&watchdog.lock); | |
447 | status = (watchdog.caused_reboot) ? WDIOF_CARDRESET : 0; | |
448 | mutex_unlock(&watchdog.lock); | |
449 | ||
450 | return status; | |
451 | } | |
452 | ||
453 | static bool watchdog_is_running(void) | |
454 | { | |
455 | /* | |
456 | * if we fail to determine the watchdog's status assume it to be | |
457 | * running to be on the safe side | |
458 | */ | |
459 | bool is_running = true; | |
460 | ||
461 | mutex_lock(&watchdog.lock); | |
462 | if (superio_enter(watchdog.sioaddr)) | |
463 | goto exit_unlock; | |
464 | superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT); | |
465 | ||
466 | is_running = (superio_inb(watchdog.sioaddr, SIO_REG_ENABLE) & BIT(0)) | |
467 | && (superio_inb(watchdog.sioaddr, F71808FG_REG_WDT_CONF) | |
468 | & F71808FG_FLAG_WD_EN); | |
469 | ||
470 | superio_exit(watchdog.sioaddr); | |
471 | ||
472 | exit_unlock: | |
473 | mutex_unlock(&watchdog.lock); | |
474 | return is_running; | |
475 | } | |
476 | ||
477 | /* /dev/watchdog api */ | |
478 | ||
479 | static int watchdog_open(struct inode *inode, struct file *file) | |
480 | { | |
481 | int err; | |
482 | ||
483 | /* If the watchdog is alive we don't need to start it again */ | |
484 | if (test_and_set_bit(0, &watchdog.opened)) | |
485 | return -EBUSY; | |
486 | ||
487 | err = watchdog_start(); | |
488 | if (err) { | |
489 | clear_bit(0, &watchdog.opened); | |
490 | return err; | |
491 | } | |
492 | ||
493 | if (nowayout) | |
494 | __module_get(THIS_MODULE); | |
495 | ||
496 | watchdog.expect_close = 0; | |
497 | return nonseekable_open(inode, file); | |
498 | } | |
499 | ||
500 | static int watchdog_release(struct inode *inode, struct file *file) | |
501 | { | |
502 | clear_bit(0, &watchdog.opened); | |
503 | ||
504 | if (!watchdog.expect_close) { | |
505 | watchdog_keepalive(); | |
27c766aa | 506 | pr_crit("Unexpected close, not stopping watchdog!\n"); |
96cb4eb0 GS |
507 | } else if (!nowayout) { |
508 | watchdog_stop(); | |
509 | } | |
510 | return 0; | |
511 | } | |
512 | ||
513 | /* | |
514 | * watchdog_write: | |
515 | * @file: file handle to the watchdog | |
516 | * @buf: buffer to write | |
517 | * @count: count of bytes | |
518 | * @ppos: pointer to the position to write. No seeks allowed | |
519 | * | |
520 | * A write to a watchdog device is defined as a keepalive signal. Any | |
521 | * write of data will do, as we we don't define content meaning. | |
522 | */ | |
523 | ||
524 | static ssize_t watchdog_write(struct file *file, const char __user *buf, | |
525 | size_t count, loff_t *ppos) | |
526 | { | |
527 | if (count) { | |
528 | if (!nowayout) { | |
529 | size_t i; | |
530 | ||
531 | /* In case it was set long ago */ | |
532 | bool expect_close = false; | |
533 | ||
534 | for (i = 0; i != count; i++) { | |
535 | char c; | |
536 | if (get_user(c, buf + i)) | |
537 | return -EFAULT; | |
538 | expect_close = (c == 'V'); | |
539 | } | |
540 | ||
541 | /* Properly order writes across fork()ed processes */ | |
542 | mutex_lock(&watchdog.lock); | |
543 | watchdog.expect_close = expect_close; | |
544 | mutex_unlock(&watchdog.lock); | |
545 | } | |
546 | ||
547 | /* someone wrote to us, we should restart timer */ | |
548 | watchdog_keepalive(); | |
549 | } | |
550 | return count; | |
551 | } | |
552 | ||
553 | /* | |
554 | * watchdog_ioctl: | |
555 | * @inode: inode of the device | |
556 | * @file: file handle to the device | |
557 | * @cmd: watchdog command | |
558 | * @arg: argument pointer | |
559 | * | |
560 | * The watchdog API defines a common set of functions for all watchdogs | |
561 | * according to their available features. | |
562 | */ | |
563 | static long watchdog_ioctl(struct file *file, unsigned int cmd, | |
564 | unsigned long arg) | |
565 | { | |
566 | int status; | |
567 | int new_options; | |
568 | int new_timeout; | |
569 | union { | |
570 | struct watchdog_info __user *ident; | |
571 | int __user *i; | |
572 | } uarg; | |
573 | ||
574 | uarg.i = (int __user *)arg; | |
575 | ||
576 | switch (cmd) { | |
577 | case WDIOC_GETSUPPORT: | |
578 | return copy_to_user(uarg.ident, &watchdog.ident, | |
579 | sizeof(watchdog.ident)) ? -EFAULT : 0; | |
580 | ||
581 | case WDIOC_GETSTATUS: | |
582 | status = watchdog_get_status(); | |
583 | if (status < 0) | |
584 | return status; | |
585 | return put_user(status, uarg.i); | |
586 | ||
587 | case WDIOC_GETBOOTSTATUS: | |
588 | return put_user(0, uarg.i); | |
589 | ||
590 | case WDIOC_SETOPTIONS: | |
591 | if (get_user(new_options, uarg.i)) | |
592 | return -EFAULT; | |
593 | ||
594 | if (new_options & WDIOS_DISABLECARD) | |
595 | watchdog_stop(); | |
596 | ||
597 | if (new_options & WDIOS_ENABLECARD) | |
598 | return watchdog_start(); | |
599 | ||
600 | ||
601 | case WDIOC_KEEPALIVE: | |
602 | watchdog_keepalive(); | |
603 | return 0; | |
604 | ||
605 | case WDIOC_SETTIMEOUT: | |
606 | if (get_user(new_timeout, uarg.i)) | |
607 | return -EFAULT; | |
608 | ||
609 | if (watchdog_set_timeout(new_timeout)) | |
610 | return -EINVAL; | |
611 | ||
612 | watchdog_keepalive(); | |
613 | /* Fall */ | |
614 | ||
615 | case WDIOC_GETTIMEOUT: | |
616 | return put_user(watchdog.timeout, uarg.i); | |
617 | ||
618 | default: | |
619 | return -ENOTTY; | |
620 | ||
621 | } | |
622 | } | |
623 | ||
624 | static int watchdog_notify_sys(struct notifier_block *this, unsigned long code, | |
625 | void *unused) | |
626 | { | |
627 | if (code == SYS_DOWN || code == SYS_HALT) | |
628 | watchdog_stop(); | |
629 | return NOTIFY_DONE; | |
630 | } | |
631 | ||
632 | static const struct file_operations watchdog_fops = { | |
633 | .owner = THIS_MODULE, | |
634 | .llseek = no_llseek, | |
635 | .open = watchdog_open, | |
636 | .release = watchdog_release, | |
637 | .write = watchdog_write, | |
638 | .unlocked_ioctl = watchdog_ioctl, | |
639 | }; | |
640 | ||
641 | static struct miscdevice watchdog_miscdev = { | |
642 | .minor = WATCHDOG_MINOR, | |
643 | .name = "watchdog", | |
644 | .fops = &watchdog_fops, | |
645 | }; | |
646 | ||
647 | static struct notifier_block watchdog_notifier = { | |
648 | .notifier_call = watchdog_notify_sys, | |
649 | }; | |
650 | ||
651 | static int __init watchdog_init(int sioaddr) | |
652 | { | |
653 | int wdt_conf, err = 0; | |
654 | ||
655 | /* No need to lock watchdog.lock here because no entry points | |
656 | * into the module have been registered yet. | |
657 | */ | |
658 | watchdog.sioaddr = sioaddr; | |
659 | watchdog.ident.options = WDIOC_SETTIMEOUT | |
660 | | WDIOF_MAGICCLOSE | |
661 | | WDIOF_KEEPALIVEPING; | |
662 | ||
663 | snprintf(watchdog.ident.identity, | |
664 | sizeof(watchdog.ident.identity), "%s watchdog", | |
665 | f71808e_names[watchdog.type]); | |
666 | ||
667 | err = superio_enter(sioaddr); | |
668 | if (err) | |
669 | return err; | |
670 | superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT); | |
671 | ||
672 | wdt_conf = superio_inb(sioaddr, F71808FG_REG_WDT_CONF); | |
b97cb21a | 673 | watchdog.caused_reboot = wdt_conf & BIT(F71808FG_FLAG_WDTMOUT_STS); |
96cb4eb0 GS |
674 | |
675 | superio_exit(sioaddr); | |
676 | ||
677 | err = watchdog_set_timeout(timeout); | |
678 | if (err) | |
679 | return err; | |
680 | err = watchdog_set_pulse_width(pulse_width); | |
681 | if (err) | |
682 | return err; | |
683 | ||
684 | err = register_reboot_notifier(&watchdog_notifier); | |
685 | if (err) | |
686 | return err; | |
687 | ||
688 | err = misc_register(&watchdog_miscdev); | |
689 | if (err) { | |
27c766aa JP |
690 | pr_err("cannot register miscdev on minor=%d\n", |
691 | watchdog_miscdev.minor); | |
96cb4eb0 GS |
692 | goto exit_reboot; |
693 | } | |
694 | ||
695 | if (start_withtimeout) { | |
696 | if (start_withtimeout <= 0 | |
697 | || start_withtimeout > max_timeout) { | |
27c766aa | 698 | pr_err("starting timeout out of range\n"); |
96cb4eb0 GS |
699 | err = -EINVAL; |
700 | goto exit_miscdev; | |
701 | } | |
702 | ||
703 | err = watchdog_start(); | |
704 | if (err) { | |
27c766aa | 705 | pr_err("cannot start watchdog timer\n"); |
96cb4eb0 GS |
706 | goto exit_miscdev; |
707 | } | |
708 | ||
709 | mutex_lock(&watchdog.lock); | |
710 | err = superio_enter(sioaddr); | |
711 | if (err) | |
712 | goto exit_unlock; | |
713 | superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT); | |
714 | ||
715 | if (start_withtimeout > 0xff) { | |
716 | /* select minutes for timer units */ | |
717 | superio_set_bit(sioaddr, F71808FG_REG_WDT_CONF, | |
718 | F71808FG_FLAG_WD_UNIT); | |
719 | superio_outb(sioaddr, F71808FG_REG_WD_TIME, | |
720 | DIV_ROUND_UP(start_withtimeout, 60)); | |
721 | } else { | |
722 | /* select seconds for timer units */ | |
723 | superio_clear_bit(sioaddr, F71808FG_REG_WDT_CONF, | |
724 | F71808FG_FLAG_WD_UNIT); | |
725 | superio_outb(sioaddr, F71808FG_REG_WD_TIME, | |
726 | start_withtimeout); | |
727 | } | |
728 | ||
729 | superio_exit(sioaddr); | |
730 | mutex_unlock(&watchdog.lock); | |
731 | ||
732 | if (nowayout) | |
733 | __module_get(THIS_MODULE); | |
734 | ||
27c766aa | 735 | pr_info("watchdog started with initial timeout of %u sec\n", |
96cb4eb0 GS |
736 | start_withtimeout); |
737 | } | |
738 | ||
739 | return 0; | |
740 | ||
741 | exit_unlock: | |
742 | mutex_unlock(&watchdog.lock); | |
743 | exit_miscdev: | |
744 | misc_deregister(&watchdog_miscdev); | |
745 | exit_reboot: | |
746 | unregister_reboot_notifier(&watchdog_notifier); | |
747 | ||
748 | return err; | |
749 | } | |
750 | ||
751 | static int __init f71808e_find(int sioaddr) | |
752 | { | |
753 | u16 devid; | |
754 | int err = superio_enter(sioaddr); | |
755 | if (err) | |
756 | return err; | |
757 | ||
758 | devid = superio_inw(sioaddr, SIO_REG_MANID); | |
759 | if (devid != SIO_FINTEK_ID) { | |
27c766aa | 760 | pr_debug("Not a Fintek device\n"); |
96cb4eb0 GS |
761 | err = -ENODEV; |
762 | goto exit; | |
763 | } | |
764 | ||
765 | devid = force_id ? force_id : superio_inw(sioaddr, SIO_REG_DEVID); | |
766 | switch (devid) { | |
767 | case SIO_F71808_ID: | |
768 | watchdog.type = f71808fg; | |
769 | break; | |
7977ff6e LB |
770 | case SIO_F71862_ID: |
771 | watchdog.type = f71862fg; | |
772 | err = f71862fg_pin_configure(0); /* validate module parameter */ | |
773 | break; | |
df278dac | 774 | case SIO_F71869_ID: |
3017020d | 775 | case SIO_F71869A_ID: |
df278dac MA |
776 | watchdog.type = f71869; |
777 | break; | |
96cb4eb0 GS |
778 | case SIO_F71882_ID: |
779 | watchdog.type = f71882fg; | |
780 | break; | |
96cb4eb0 | 781 | case SIO_F71889_ID: |
dee00abb GS |
782 | watchdog.type = f71889fg; |
783 | break; | |
96cb4eb0 GS |
784 | case SIO_F71858_ID: |
785 | /* Confirmed (by datasheet) not to have a watchdog. */ | |
786 | err = -ENODEV; | |
787 | goto exit; | |
ea0c03e8 KP |
788 | case SIO_F81865_ID: |
789 | watchdog.type = f81865; | |
790 | break; | |
96cb4eb0 | 791 | default: |
27c766aa JP |
792 | pr_info("Unrecognized Fintek device: %04x\n", |
793 | (unsigned int)devid); | |
96cb4eb0 GS |
794 | err = -ENODEV; |
795 | goto exit; | |
796 | } | |
797 | ||
27c766aa | 798 | pr_info("Found %s watchdog chip, revision %d\n", |
96cb4eb0 GS |
799 | f71808e_names[watchdog.type], |
800 | (int)superio_inb(sioaddr, SIO_REG_DEVREV)); | |
801 | exit: | |
802 | superio_exit(sioaddr); | |
803 | return err; | |
804 | } | |
805 | ||
806 | static int __init f71808e_init(void) | |
807 | { | |
808 | static const unsigned short addrs[] = { 0x2e, 0x4e }; | |
809 | int err = -ENODEV; | |
810 | int i; | |
811 | ||
812 | for (i = 0; i < ARRAY_SIZE(addrs); i++) { | |
813 | err = f71808e_find(addrs[i]); | |
814 | if (err == 0) | |
815 | break; | |
816 | } | |
817 | if (i == ARRAY_SIZE(addrs)) | |
818 | return err; | |
819 | ||
820 | return watchdog_init(addrs[i]); | |
821 | } | |
822 | ||
823 | static void __exit f71808e_exit(void) | |
824 | { | |
825 | if (watchdog_is_running()) { | |
27c766aa | 826 | pr_warn("Watchdog timer still running, stopping it\n"); |
96cb4eb0 GS |
827 | watchdog_stop(); |
828 | } | |
829 | misc_deregister(&watchdog_miscdev); | |
830 | unregister_reboot_notifier(&watchdog_notifier); | |
831 | } | |
832 | ||
833 | MODULE_DESCRIPTION("F71808E Watchdog Driver"); | |
834 | MODULE_AUTHOR("Giel van Schijndel <me@mortis.eu>"); | |
835 | MODULE_LICENSE("GPL"); | |
836 | ||
837 | module_init(f71808e_init); | |
838 | module_exit(f71808e_exit); |