[deliverable/linux.git] / drivers / watchdog / i6300esb.c

/*
 *	i6300esb:	Watchdog timer driver for Intel 6300ESB chipset
 *
 *	(c) Copyright 2004 Google Inc.
 *	(c) Copyright 2005 David Härdeman <david@2gen.com>
 *
 *	This program is free software; you can redistribute it and/or
 *	modify it under the terms of the GNU General Public License
 *	as published by the Free Software Foundation; either version
 *	2 of the License, or (at your option) any later version.
 *
 *	based on i810-tco.c which is in turn based on softdog.c
 *
 *	The timer is implemented in the following I/O controller hubs:
 *	(See the intel documentation on http://developer.intel.com.)
 *	6300ESB chip : document number 300641-003
 *
 *  2004YYZZ Ross Biro
 *	Initial version 0.01
 *  2004YYZZ Ross Biro
 *	Version 0.02
 *  20050210 David Härdeman <david@2gen.com>
 *	Ported driver to kernel 2.6
 */

/*
 *      Includes, defines, variables, module parameters, ...
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/fs.h>
#include <linux/mm.h>
#include <linux/miscdevice.h>
#include <linux/watchdog.h>
#include <linux/reboot.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/ioport.h>
#include <linux/uaccess.h>
#include <linux/io.h>

/* Module and version information */
#define ESB_VERSION "0.03"
#define ESB_MODULE_NAME "i6300ESB timer"
#define ESB_DRIVER_NAME ESB_MODULE_NAME ", v" ESB_VERSION
#define PFX ESB_MODULE_NAME ": "

/* PCI configuration registers */
#define ESB_CONFIG_REG  0x60            /* Config register                   */
#define ESB_LOCK_REG    0x68            /* WDT lock register                 */

/* Memory mapped registers */
#define ESB_TIMER1_REG  BASEADDR + 0x00 /* Timer1 value after each reset     */
#define ESB_TIMER2_REG  BASEADDR + 0x04 /* Timer2 value after each reset     */
#define ESB_GINTSR_REG  BASEADDR + 0x08 /* General Interrupt Status Register */
#define ESB_RELOAD_REG  BASEADDR + 0x0c /* Reload register                   */

/* Lock register bits */
#define ESB_WDT_FUNC    (0x01 << 2)   /* Watchdog functionality            */
#define ESB_WDT_ENABLE  (0x01 << 1)   /* Enable WDT                        */
#define ESB_WDT_LOCK    (0x01 << 0)   /* Lock (nowayout)                   */

/* Config register bits */
#define ESB_WDT_REBOOT  (0x01 << 5)   /* Enable reboot on timeout          */
#define ESB_WDT_FREQ    (0x01 << 2)   /* Decrement frequency               */
#define ESB_WDT_INTTYPE (0x11 << 0)   /* Interrupt type on timer1 timeout  */

/* Reload register bits */
#define ESB_WDT_RELOAD  (0x01 << 8)    /* prevent timeout                   */

/* Magic constants */
#define ESB_UNLOCK1     0x80            /* Step 1 to unlock reset registers  */
#define ESB_UNLOCK2     0x86            /* Step 2 to unlock reset registers  */

/* internal variables */
static void __iomem *BASEADDR;
static DEFINE_SPINLOCK(esb_lock); /* Guards the hardware */
static unsigned long timer_alive;
static struct pci_dev *esb_pci;
static unsigned short triggered; /* The status of the watchdog upon boot */
static char esb_expect_close;

/* module parameters */
/* 30 sec default heartbeat (1 < heartbeat < 2*1023) */
#define WATCHDOG_HEARTBEAT 30
static int heartbeat = WATCHDOG_HEARTBEAT;  /* in seconds */

module_param(heartbeat, int, 0);
MODULE_PARM_DESC(heartbeat,
		"Watchdog heartbeat in seconds. (1<heartbeat<2046, default="
				__MODULE_STRING(WATCHDOG_HEARTBEAT) ")");

static int nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, int, 0);
MODULE_PARM_DESC(nowayout,
		"Watchdog cannot be stopped once started (default="
				__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

/*
 * Some i6300ESB specific functions
 */

/*
 * Prepare for reloading the timer by unlocking the proper registers.
 * This is performed by first writing 0x80 followed by 0x86 to the
 * reload register. After this the appropriate registers can be written
 * to once before they need to be unlocked again.
 */
static inline void esb_unlock_registers(void)
{
	writeb(ESB_UNLOCK1, ESB_RELOAD_REG);
	writeb(ESB_UNLOCK2, ESB_RELOAD_REG);
}

static void esb_timer_start(void)
{
	u8 val;

	/* Enable or Enable + Lock? */
	val = 0x02 | (nowayout ? 0x01 : 0x00);
	pci_write_config_byte(esb_pci, ESB_LOCK_REG, val);
}

static int esb_timer_stop(void)
{
	u8 val;

	spin_lock(&esb_lock);
	/* First, reset timers as suggested by the docs */
	esb_unlock_registers();
	writew(ESB_WDT_RELOAD, ESB_RELOAD_REG);
	/* Then disable the WDT */
	pci_write_config_byte(esb_pci, ESB_LOCK_REG, 0x0);
	pci_read_config_byte(esb_pci, ESB_LOCK_REG, &val);
	spin_unlock(&esb_lock);

	/* Returns 0 if the timer was disabled, non-zero otherwise */
	return (val & 0x01);
}

static void esb_timer_keepalive(void)
{
	spin_lock(&esb_lock);
	esb_unlock_registers();
	writew(ESB_WDT_RELOAD, ESB_RELOAD_REG);
	/* FIXME: Do we need to flush anything here? */
	spin_unlock(&esb_lock);
}

static int esb_timer_set_heartbeat(int time)
{
	u32 val;

	if (time < 0x1 || time > (2 * 0x03ff))
		return -EINVAL;

	spin_lock(&esb_lock);

	/* We shift by 9, so if we are passed a value of 1 sec,
	 * val will be 1 << 9 = 512, then write that to two
	 * timers => 2 * 512 = 1024 (which is decremented at 1KHz)
	 */
	val = time << 9;

	/* Write timer 1 */
	esb_unlock_registers();
	writel(val, ESB_TIMER1_REG);

	/* Write timer 2 */
	esb_unlock_registers();
	writel(val, ESB_TIMER2_REG);

	/* Reload */
	esb_unlock_registers();
	writew(ESB_WDT_RELOAD, ESB_RELOAD_REG);

	/* FIXME: Do we need to flush everything out? */

	/* Done */
	heartbeat = time;
	spin_unlock(&esb_lock);
	return 0;
}

static int esb_timer_read(void)
{
	u32 count;

	/* This isn't documented, and doesn't take into
	 * acount which stage is running, but it looks
	 * like a 20 bit count down, so we might as well report it.
	 */
	pci_read_config_dword(esb_pci, 0x64, &count);
	return (int)count;
}

/*
 *	/dev/watchdog handling
 */

static int esb_open(struct inode *inode, struct file *file)
{
	/* /dev/watchdog can only be opened once */
	if (test_and_set_bit(0, &timer_alive))
		return -EBUSY;

	/* Reload and activate timer */
	esb_timer_keepalive();
	esb_timer_start();

	return nonseekable_open(inode, file);
}

static int esb_release(struct inode *inode, struct file *file)
{
	/* Shut off the timer. */
	if (esb_expect_close == 42)
		esb_timer_stop();
	else {
		printk(KERN_CRIT PFX
				"Unexpected close, not stopping watchdog!\n");
		esb_timer_keepalive();
	}
	clear_bit(0, &timer_alive);
	esb_expect_close = 0;
	return 0;
}

static ssize_t esb_write(struct file *file, const char __user *data,
			  size_t len, loff_t *ppos)
{
	/* See if we got the magic character 'V' and reload the timer */
	if (len) {
		if (!nowayout) {
			size_t i;

			/* note: just in case someone wrote the magic character
			 * five months ago... */
			esb_expect_close = 0;

			/* scan to see whether or not we got the magic character */
			for (i = 0; i != len; i++) {
				char c;
				if (get_user(c, data + i))
					return -EFAULT;
				if (c == 'V')
					esb_expect_close = 42;
			}
		}

		/* someone wrote to us, we should reload the timer */
		esb_timer_keepalive();
	}
	return len;
}

static long esb_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
{
	int new_options, retval = -EINVAL;
	int new_heartbeat;
	void __user *argp = (void __user *)arg;
	int __user *p = argp;
	static struct watchdog_info ident = {
		.options =		WDIOF_SETTIMEOUT |
					WDIOF_KEEPALIVEPING |
					WDIOF_MAGICCLOSE,
		.firmware_version =	0,
		.identity =		ESB_MODULE_NAME,
	};

	switch (cmd) {
	case WDIOC_GETSUPPORT:
		return copy_to_user(argp, &ident,
					sizeof(ident)) ? -EFAULT : 0;

	case WDIOC_GETSTATUS:
		return put_user(esb_timer_read(), p);

	case WDIOC_GETBOOTSTATUS:
		return put_user(triggered, p);

	case WDIOC_SETOPTIONS:
	{
		if (get_user(new_options, p))
			return -EFAULT;

		if (new_options & WDIOS_DISABLECARD) {
			esb_timer_stop();
			retval = 0;
		}

		if (new_options & WDIOS_ENABLECARD) {
			esb_timer_keepalive();
			esb_timer_start();
			retval = 0;
		}
		return retval;
	}
	case WDIOC_KEEPALIVE:
		esb_timer_keepalive();
		return 0;

	case WDIOC_SETTIMEOUT:
	{
		if (get_user(new_heartbeat, p))
			return -EFAULT;
		if (esb_timer_set_heartbeat(new_heartbeat))
			return -EINVAL;
		esb_timer_keepalive();
		/* Fall */
	}
	case WDIOC_GETTIMEOUT:
		return put_user(heartbeat, p);
	default:
		return -ENOTTY;
	}
}

/*
 *      Notify system
 */

static int esb_notify_sys(struct notifier_block *this,
					unsigned long code, void *unused)
{
	if (code == SYS_DOWN || code == SYS_HALT)
		esb_timer_stop();	/* Turn the WDT off */

	return NOTIFY_DONE;
}

/*
 *      Kernel Interfaces
 */

static const struct file_operations esb_fops = {
	.owner = THIS_MODULE,
	.llseek = no_llseek,
	.write = esb_write,
	.unlocked_ioctl = esb_ioctl,
	.open = esb_open,
	.release = esb_release,
};

static struct miscdevice esb_miscdev = {
	.minor = WATCHDOG_MINOR,
	.name = "watchdog",
	.fops = &esb_fops,
};

static struct notifier_block esb_notifier = {
	.notifier_call = esb_notify_sys,
};

/*
 * Data for PCI driver interface
 *
 * This data only exists for exporting the supported
 * PCI ids via MODULE_DEVICE_TABLE.  We do not actually
 * register a pci_driver, because someone else might one day
 * want to register another driver on the same PCI id.
 */
static struct pci_device_id esb_pci_tbl[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_9), },
	{ 0, },                 /* End of list */
};
MODULE_DEVICE_TABLE(pci, esb_pci_tbl);

/*
 *      Init & exit routines
 */

static unsigned char __init esb_getdevice(void)
{
	u8 val1;
	unsigned short val2;
	/*
	 *      Find the PCI device
	 */

	esb_pci = pci_get_device(PCI_VENDOR_ID_INTEL,
					PCI_DEVICE_ID_INTEL_ESB_9, NULL);

	if (esb_pci) {
		if (pci_enable_device(esb_pci)) {
			printk(KERN_ERR PFX "failed to enable device\n");
			goto err_devput;
		}

		if (pci_request_region(esb_pci, 0, ESB_MODULE_NAME)) {
			printk(KERN_ERR PFX "failed to request region\n");
			goto err_disable;
		}

		BASEADDR = pci_ioremap_bar(esb_pci, 0);
		if (BASEADDR == NULL) {
			/* Something's wrong here, BASEADDR has to be set */
			printk(KERN_ERR PFX "failed to get BASEADDR\n");
			goto err_release;
		}

		/*
		 * The watchdog has two timers, it can be setup so that the
		 * expiry of timer1 results in an interrupt and the expiry of
		 * timer2 results in a reboot. We set it to not generate
		 * any interrupts as there is not much we can do with it
		 * right now.
		 *
		 * We also enable reboots and set the timer frequency to
		 * the PCI clock divided by 2^15 (approx 1KHz).
		 */
		pci_write_config_word(esb_pci, ESB_CONFIG_REG, 0x0003);

		/* Check that the WDT isn't already locked */
		pci_read_config_byte(esb_pci, ESB_LOCK_REG, &val1);
		if (val1 & ESB_WDT_LOCK)
			printk(KERN_WARNING PFX "nowayout already set\n");

		/* Set the timer to watchdog mode and disable it for now */
		pci_write_config_byte(esb_pci, ESB_LOCK_REG, 0x00);

		/* Check if the watchdog was previously triggered */
		esb_unlock_registers();
		val2 = readw(ESB_RELOAD_REG);
		triggered = (val2 & (0x01 << 9) >> 9);

		/* Reset trigger flag and timers */
		esb_unlock_registers();
		writew((0x11 << 8), ESB_RELOAD_REG);

		/* Done */
		return 1;

err_release:
		pci_release_region(esb_pci, 0);
err_disable:
		pci_disable_device(esb_pci);
err_devput:
		pci_dev_put(esb_pci);
	}
	return 0;
}

static int __init watchdog_init(void)
{
	int ret;

	/* Check whether or not the hardware watchdog is there */
	if (!esb_getdevice() || esb_pci == NULL)
		return -ENODEV;

	/* Check that the heartbeat value is within it's range;
	   if not reset to the default */
	if (esb_timer_set_heartbeat(heartbeat)) {
		esb_timer_set_heartbeat(WATCHDOG_HEARTBEAT);
		printk(KERN_INFO PFX
			"heartbeat value must be 1<heartbeat<2046, using %d\n",
								heartbeat);
	}
	ret = register_reboot_notifier(&esb_notifier);
	if (ret != 0) {
		printk(KERN_ERR PFX
			"cannot register reboot notifier (err=%d)\n", ret);
		goto err_unmap;
	}

	ret = misc_register(&esb_miscdev);
	if (ret != 0) {
		printk(KERN_ERR PFX
			"cannot register miscdev on minor=%d (err=%d)\n",
							WATCHDOG_MINOR, ret);
		goto err_notifier;
	}
	esb_timer_stop();
	printk(KERN_INFO PFX
		"initialized (0x%p). heartbeat=%d sec (nowayout=%d)\n",
						BASEADDR, heartbeat, nowayout);
	return 0;

err_notifier:
	unregister_reboot_notifier(&esb_notifier);
err_unmap:
	iounmap(BASEADDR);
/* err_release: */
	pci_release_region(esb_pci, 0);
/* err_disable: */
	pci_disable_device(esb_pci);
/* err_devput: */
	pci_dev_put(esb_pci);
	return ret;
}

static void __exit watchdog_cleanup(void)
{
	/* Stop the timer before we leave */
	if (!nowayout)
		esb_timer_stop();

	/* Deregister */
	misc_deregister(&esb_miscdev);
	unregister_reboot_notifier(&esb_notifier);
	iounmap(BASEADDR);
	pci_release_region(esb_pci, 0);
	pci_disable_device(esb_pci);
	pci_dev_put(esb_pci);
}

module_init(watchdog_init);
module_exit(watchdog_cleanup);

MODULE_AUTHOR("Ross Biro and David Härdeman");
MODULE_DESCRIPTION("Watchdog driver for Intel 6300ESB chipsets");
MODULE_LICENSE("GPL");
MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
Commit	Line	Data
cc90ef0f	1	/*
abda5c8b	2	* i6300esb: Watchdog timer driver for Intel 6300ESB chipset
cc90ef0f DH	3	*
cc90ef0f DH	4	* (c) Copyright 2004 Google Inc.
96de0e25	5	* (c) Copyright 2005 David Härdeman <david@2gen.com>
cc90ef0f DH	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License
	9	* as published by the Free Software Foundation; either version
	10	* 2 of the License, or (at your option) any later version.
	11	*
7944d3a5	12	* based on i810-tco.c which is in turn based on softdog.c
cc90ef0f	13	*
7944d3a5 WVS	14	* The timer is implemented in the following I/O controller hubs:
	15	* (See the intel documentation on http://developer.intel.com.)
	16	* 6300ESB chip : document number 300641-003
cc90ef0f DH	17	*
	18	* 2004YYZZ Ross Biro
	19	* Initial version 0.01
	20	* 2004YYZZ Ross Biro
7944d3a5	21	* Version 0.02
96de0e25	22	* 20050210 David Härdeman <david@2gen.com>
7944d3a5	23	* Ported driver to kernel 2.6
cc90ef0f DH	24	*/
	25
	26	/*
	27	* Includes, defines, variables, module parameters, ...
	28	*/
	29
	30	#include <linux/module.h>
	31	#include <linux/types.h>
	32	#include <linux/kernel.h>
	33	#include <linux/fs.h>
	34	#include <linux/mm.h>
	35	#include <linux/miscdevice.h>
	36	#include <linux/watchdog.h>
	37	#include <linux/reboot.h>
	38	#include <linux/init.h>
	39	#include <linux/pci.h>
	40	#include <linux/ioport.h>
0829291e AC	41	#include <linux/uaccess.h>
0829291e AC	42	#include <linux/io.h>
cc90ef0f	43
cc90ef0f DH	44	/* Module and version information */
	45	#define ESB_VERSION "0.03"
	46	#define ESB_MODULE_NAME "i6300ESB timer"
	47	#define ESB_DRIVER_NAME ESB_MODULE_NAME ", v" ESB_VERSION
	48	#define PFX ESB_MODULE_NAME ": "
	49
abda5c8b DH	50	/* PCI configuration registers */
	51	#define ESB_CONFIG_REG 0x60 /* Config register */
	52	#define ESB_LOCK_REG 0x68 /* WDT lock register */
	53
	54	/* Memory mapped registers */
	55	#define ESB_TIMER1_REG BASEADDR + 0x00 /* Timer1 value after each reset */
	56	#define ESB_TIMER2_REG BASEADDR + 0x04 /* Timer2 value after each reset */
	57	#define ESB_GINTSR_REG BASEADDR + 0x08 /* General Interrupt Status Register */
	58	#define ESB_RELOAD_REG BASEADDR + 0x0c /* Reload register */
	59
	60	/* Lock register bits */
0829291e AC	61	#define ESB_WDT_FUNC (0x01 << 2) /* Watchdog functionality */
	62	#define ESB_WDT_ENABLE (0x01 << 1) /* Enable WDT */
	63	#define ESB_WDT_LOCK (0x01 << 0) /* Lock (nowayout) */
abda5c8b DH	64
abda5c8b DH	65	/* Config register bits */
0829291e AC	66	#define ESB_WDT_REBOOT (0x01 << 5) /* Enable reboot on timeout */
	67	#define ESB_WDT_FREQ (0x01 << 2) /* Decrement frequency */
	68	#define ESB_WDT_INTTYPE (0x11 << 0) /* Interrupt type on timer1 timeout */
abda5c8b DH	69
abda5c8b DH	70	/* Reload register bits */
0829291e	71	#define ESB_WDT_RELOAD (0x01 << 8) /* prevent timeout */
abda5c8b DH	72
	73	/* Magic constants */
	74	#define ESB_UNLOCK1 0x80 /* Step 1 to unlock reset registers */
	75	#define ESB_UNLOCK2 0x86 /* Step 2 to unlock reset registers */
	76
cc90ef0f DH	77	/* internal variables */
cc90ef0f DH	78	static void __iomem *BASEADDR;
c7dfd0cc	79	static DEFINE_SPINLOCK(esb_lock); /* Guards the hardware */
cc90ef0f DH	80	static unsigned long timer_alive;
	81	static struct pci_dev *esb_pci;
	82	static unsigned short triggered; /* The status of the watchdog upon boot */
	83	static char esb_expect_close;
	84
	85	/* module parameters */
0829291e AC	86	/* 30 sec default heartbeat (1 < heartbeat < 21023) /
0829291e AC	87	#define WATCHDOG_HEARTBEAT 30
cc90ef0f	88	static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
0829291e	89
cc90ef0f	90	module_param(heartbeat, int, 0);
0829291e AC	91	MODULE_PARM_DESC(heartbeat,
	92	"Watchdog heartbeat in seconds. (1<heartbeat<2046, default="
	93	__MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
cc90ef0f	94
811f9991	95	static int nowayout = WATCHDOG_NOWAYOUT;
cc90ef0f	96	module_param(nowayout, int, 0);
0829291e AC	97	MODULE_PARM_DESC(nowayout,
	98	"Watchdog cannot be stopped once started (default="
	99	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
cc90ef0f DH	100
	101	/*
	102	* Some i6300ESB specific functions
	103	*/
	104
	105	/*
	106	* Prepare for reloading the timer by unlocking the proper registers.
	107	* This is performed by first writing 0x80 followed by 0x86 to the
	108	* reload register. After this the appropriate registers can be written
	109	* to once before they need to be unlocked again.
	110	*/
7944d3a5 WVS	111	static inline void esb_unlock_registers(void)
7944d3a5 WVS	112	{
0829291e AC	113	writeb(ESB_UNLOCK1, ESB_RELOAD_REG);
0829291e AC	114	writeb(ESB_UNLOCK2, ESB_RELOAD_REG);
cc90ef0f DH	115	}
	116
	117	static void esb_timer_start(void)
	118	{
	119	u8 val;
	120
	121	/* Enable or Enable + Lock? */
28562af3	122	val = 0x02 \| (nowayout ? 0x01 : 0x00);
0829291e	123	pci_write_config_byte(esb_pci, ESB_LOCK_REG, val);
cc90ef0f DH	124	}
	125
	126	static int esb_timer_stop(void)
	127	{
	128	u8 val;
	129
	130	spin_lock(&esb_lock);
	131	/* First, reset timers as suggested by the docs */
	132	esb_unlock_registers();
ce2f50b4	133	writew(ESB_WDT_RELOAD, ESB_RELOAD_REG);
cc90ef0f DH	134	/* Then disable the WDT */
	135	pci_write_config_byte(esb_pci, ESB_LOCK_REG, 0x0);
	136	pci_read_config_byte(esb_pci, ESB_LOCK_REG, &val);
	137	spin_unlock(&esb_lock);
	138
	139	/* Returns 0 if the timer was disabled, non-zero otherwise */
	140	return (val & 0x01);
	141	}
	142
	143	static void esb_timer_keepalive(void)
	144	{
	145	spin_lock(&esb_lock);
	146	esb_unlock_registers();
ce2f50b4	147	writew(ESB_WDT_RELOAD, ESB_RELOAD_REG);
0829291e	148	/* FIXME: Do we need to flush anything here? */
cc90ef0f DH	149	spin_unlock(&esb_lock);
	150	}
	151
	152	static int esb_timer_set_heartbeat(int time)
	153	{
	154	u32 val;
	155
	156	if (time < 0x1 \|\| time > (2 * 0x03ff))
	157	return -EINVAL;
	158
	159	spin_lock(&esb_lock);
	160
	161	/* We shift by 9, so if we are passed a value of 1 sec,
	162	* val will be 1 << 9 = 512, then write that to two
	163	* timers => 2 * 512 = 1024 (which is decremented at 1KHz)
	164	*/
	165	val = time << 9;
	166
	167	/* Write timer 1 */
	168	esb_unlock_registers();
	169	writel(val, ESB_TIMER1_REG);
	170
	171	/* Write timer 2 */
	172	esb_unlock_registers();
7944d3a5	173	writel(val, ESB_TIMER2_REG);
cc90ef0f	174
0829291e	175	/* Reload */
cc90ef0f	176	esb_unlock_registers();
ce2f50b4	177	writew(ESB_WDT_RELOAD, ESB_RELOAD_REG);
cc90ef0f DH	178
	179	/* FIXME: Do we need to flush everything out? */
	180
	181	/* Done */
	182	heartbeat = time;
	183	spin_unlock(&esb_lock);
	184	return 0;
	185	}
	186
0829291e	187	static int esb_timer_read(void)
cc90ef0f	188	{
0829291e	189	u32 count;
cc90ef0f DH	190
cc90ef0f DH	191	/* This isn't documented, and doesn't take into
0829291e AC	192	* acount which stage is running, but it looks
	193	* like a 20 bit count down, so we might as well report it.
	194	*/
	195	pci_read_config_dword(esb_pci, 0x64, &count);
	196	return (int)count;
cc90ef0f DH	197	}
	198
	199	/*
7944d3a5	200	* /dev/watchdog handling
cc90ef0f DH	201	*/
cc90ef0f DH	202
0829291e	203	static int esb_open(struct inode inode, struct file file)
cc90ef0f	204	{
0829291e AC	205	/* /dev/watchdog can only be opened once */
	206	if (test_and_set_bit(0, &timer_alive))
	207	return -EBUSY;
cc90ef0f	208
0829291e AC	209	/* Reload and activate timer */
	210	esb_timer_keepalive();
	211	esb_timer_start();
cc90ef0f DH	212
	213	return nonseekable_open(inode, file);
	214	}
	215
0829291e	216	static int esb_release(struct inode inode, struct file file)
cc90ef0f	217	{
0829291e AC	218	/* Shut off the timer. */
	219	if (esb_expect_close == 42)
	220	esb_timer_stop();
	221	else {
	222	printk(KERN_CRIT PFX
	223	"Unexpected close, not stopping watchdog!\n");
	224	esb_timer_keepalive();
	225	}
	226	clear_bit(0, &timer_alive);
	227	esb_expect_close = 0;
	228	return 0;
cc90ef0f DH	229	}
cc90ef0f DH	230
0829291e AC	231	static ssize_t esb_write(struct file file, const char __user data,
0829291e AC	232	size_t len, loff_t *ppos)
cc90ef0f DH	233	{
cc90ef0f DH	234	/* See if we got the magic character 'V' and reload the timer */
0829291e	235	if (len) {
cc90ef0f DH	236	if (!nowayout) {
	237	size_t i;
	238
	239	/* note: just in case someone wrote the magic character
	240	* five months ago... */
	241	esb_expect_close = 0;
	242
	243	/* scan to see whether or not we got the magic character */
	244	for (i = 0; i != len; i++) {
	245	char c;
7944d3a5	246	if (get_user(c, data + i))
cc90ef0f DH	247	return -EFAULT;
	248	if (c == 'V')
	249	esb_expect_close = 42;
	250	}
	251	}
	252
	253	/* someone wrote to us, we should reload the timer */
0829291e	254	esb_timer_keepalive();
cc90ef0f DH	255	}
	256	return len;
	257	}
	258
0829291e	259	static long esb_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
cc90ef0f DH	260	{
	261	int new_options, retval = -EINVAL;
	262	int new_heartbeat;
	263	void __user argp = (void __user )arg;
	264	int __user *p = argp;
	265	static struct watchdog_info ident = {
7944d3a5	266	.options = WDIOF_SETTIMEOUT \|
cc90ef0f DH	267	WDIOF_KEEPALIVEPING \|
cc90ef0f DH	268	WDIOF_MAGICCLOSE,
7944d3a5 WVS	269	.firmware_version = 0,
7944d3a5 WVS	270	.identity = ESB_MODULE_NAME,
cc90ef0f DH	271	};
	272
	273	switch (cmd) {
0829291e AC	274	case WDIOC_GETSUPPORT:
	275	return copy_to_user(argp, &ident,
	276	sizeof(ident)) ? -EFAULT : 0;
cc90ef0f	277
0829291e AC	278	case WDIOC_GETSTATUS:
0829291e AC	279	return put_user(esb_timer_read(), p);
cc90ef0f	280
0829291e AC	281	case WDIOC_GETBOOTSTATUS:
0829291e AC	282	return put_user(triggered, p);
cc90ef0f	283
0829291e AC	284	case WDIOC_SETOPTIONS:
	285	{
	286	if (get_user(new_options, p))
	287	return -EFAULT;
cc90ef0f	288
0829291e AC	289	if (new_options & WDIOS_DISABLECARD) {
	290	esb_timer_stop();
	291	retval = 0;
	292	}
cc90ef0f	293
0829291e AC	294	if (new_options & WDIOS_ENABLECARD) {
	295	esb_timer_keepalive();
	296	esb_timer_start();
	297	retval = 0;
	298	}
	299	return retval;
	300	}
0c06090c WVS	301	case WDIOC_KEEPALIVE:
	302	esb_timer_keepalive();
	303	return 0;
	304
0829291e AC	305	case WDIOC_SETTIMEOUT:
	306	{
	307	if (get_user(new_heartbeat, p))
	308	return -EFAULT;
	309	if (esb_timer_set_heartbeat(new_heartbeat))
	310	return -EINVAL;
	311	esb_timer_keepalive();
	312	/* Fall */
	313	}
	314	case WDIOC_GETTIMEOUT:
	315	return put_user(heartbeat, p);
	316	default:
	317	return -ENOTTY;
	318	}
cc90ef0f DH	319	}
	320
	321	/*
	322	* Notify system
	323	*/
	324
0829291e AC	325	static int esb_notify_sys(struct notifier_block *this,
0829291e AC	326	unsigned long code, void *unused)
cc90ef0f	327	{
7944d3a5 WVS	328	if (code == SYS_DOWN \|\| code == SYS_HALT)
	329	esb_timer_stop(); /* Turn the WDT off */
	330
0829291e	331	return NOTIFY_DONE;
cc90ef0f DH	332	}
	333
	334	/*
	335	* Kernel Interfaces
	336	*/
	337
62322d25	338	static const struct file_operations esb_fops = {
0829291e AC	339	.owner = THIS_MODULE,
	340	.llseek = no_llseek,
	341	.write = esb_write,
	342	.unlocked_ioctl = esb_ioctl,
	343	.open = esb_open,
	344	.release = esb_release,
cc90ef0f DH	345	};
	346
	347	static struct miscdevice esb_miscdev = {
0829291e AC	348	.minor = WATCHDOG_MINOR,
	349	.name = "watchdog",
	350	.fops = &esb_fops,
cc90ef0f DH	351	};
	352
	353	static struct notifier_block esb_notifier = {
0829291e	354	.notifier_call = esb_notify_sys,
cc90ef0f DH	355	};
	356
	357	/*
	358	* Data for PCI driver interface
	359	*
	360	* This data only exists for exporting the supported
	361	* PCI ids via MODULE_DEVICE_TABLE. We do not actually
	362	* register a pci_driver, because someone else might one day
	363	* want to register another driver on the same PCI id.
	364	*/
	365	static struct pci_device_id esb_pci_tbl[] = {
0829291e AC	366	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_9), },
0829291e AC	367	{ 0, }, /* End of list */
cc90ef0f	368	};
0829291e	369	MODULE_DEVICE_TABLE(pci, esb_pci_tbl);
cc90ef0f DH	370
	371	/*
	372	* Init & exit routines
	373	*/
	374
0829291e	375	static unsigned char __init esb_getdevice(void)
cc90ef0f DH	376	{
	377	u8 val1;
	378	unsigned short val2;
0829291e AC	379	/*
	380	* Find the PCI device
	381	*/
cc90ef0f	382
0829291e AC	383	esb_pci = pci_get_device(PCI_VENDOR_ID_INTEL,
0829291e AC	384	PCI_DEVICE_ID_INTEL_ESB_9, NULL);
cc90ef0f	385
0829291e AC	386	if (esb_pci) {
	387	if (pci_enable_device(esb_pci)) {
	388	printk(KERN_ERR PFX "failed to enable device\n");
811f9991	389	goto err_devput;
cc90ef0f DH	390	}
	391
	392	if (pci_request_region(esb_pci, 0, ESB_MODULE_NAME)) {
0829291e	393	printk(KERN_ERR PFX "failed to request region\n");
cc90ef0f DH	394	goto err_disable;
	395	}
	396
af4c293f	397	BASEADDR = pci_ioremap_bar(esb_pci, 0);
cc90ef0f	398	if (BASEADDR == NULL) {
0829291e AC	399	/* Something's wrong here, BASEADDR has to be set */
	400	printk(KERN_ERR PFX "failed to get BASEADDR\n");
	401	goto err_release;
	402	}
cc90ef0f DH	403
	404	/*
	405	* The watchdog has two timers, it can be setup so that the
	406	* expiry of timer1 results in an interrupt and the expiry of
	407	* timer2 results in a reboot. We set it to not generate
	408	* any interrupts as there is not much we can do with it
	409	* right now.
	410	*
	411	* We also enable reboots and set the timer frequency to
	412	* the PCI clock divided by 2^15 (approx 1KHz).
	413	*/
	414	pci_write_config_word(esb_pci, ESB_CONFIG_REG, 0x0003);
	415
	416	/* Check that the WDT isn't already locked */
	417	pci_read_config_byte(esb_pci, ESB_LOCK_REG, &val1);
	418	if (val1 & ESB_WDT_LOCK)
0829291e	419	printk(KERN_WARNING PFX "nowayout already set\n");
cc90ef0f DH	420
	421	/* Set the timer to watchdog mode and disable it for now */
	422	pci_write_config_byte(esb_pci, ESB_LOCK_REG, 0x00);
	423
	424	/* Check if the watchdog was previously triggered */
	425	esb_unlock_registers();
	426	val2 = readw(ESB_RELOAD_REG);
	427	triggered = (val2 & (0x01 << 9) >> 9);
	428
	429	/* Reset trigger flag and timers */
	430	esb_unlock_registers();
	431	writew((0x11 << 8), ESB_RELOAD_REG);
	432
	433	/* Done */
	434	return 1;
	435
	436	err_release:
	437	pci_release_region(esb_pci, 0);
	438	err_disable:
	439	pci_disable_device(esb_pci);
811f9991	440	err_devput:
c69af038	441	pci_dev_put(esb_pci);
cc90ef0f	442	}
cc90ef0f DH	443	return 0;
	444	}
	445
0829291e	446	static int __init watchdog_init(void)
cc90ef0f	447	{
0829291e AC	448	int ret;
	449
	450	/* Check whether or not the hardware watchdog is there */
	451	if (!esb_getdevice() \|\| esb_pci == NULL)
	452	return -ENODEV;
	453
	454	/* Check that the heartbeat value is within it's range;
	455	if not reset to the default */
	456	if (esb_timer_set_heartbeat(heartbeat)) {
	457	esb_timer_set_heartbeat(WATCHDOG_HEARTBEAT);
	458	printk(KERN_INFO PFX
	459	"heartbeat value must be 1<heartbeat<2046, using %d\n",
	460	heartbeat);
	461	}
	462	ret = register_reboot_notifier(&esb_notifier);
	463	if (ret != 0) {
	464	printk(KERN_ERR PFX
	465	"cannot register reboot notifier (err=%d)\n", ret);
	466	goto err_unmap;
	467	}
cc90ef0f	468
0829291e AC	469	ret = misc_register(&esb_miscdev);
	470	if (ret != 0) {
	471	printk(KERN_ERR PFX
	472	"cannot register miscdev on minor=%d (err=%d)\n",
	473	WATCHDOG_MINOR, ret);
	474	goto err_notifier;
	475	}
	476	esb_timer_stop();
	477	printk(KERN_INFO PFX
	478	"initialized (0x%p). heartbeat=%d sec (nowayout=%d)\n",
	479	BASEADDR, heartbeat, nowayout);
	480	return 0;
cc90ef0f DH	481
cc90ef0f DH	482	err_notifier:
0829291e	483	unregister_reboot_notifier(&esb_notifier);
cc90ef0f DH	484	err_unmap:
	485	iounmap(BASEADDR);
	486	/* err_release: */
	487	pci_release_region(esb_pci, 0);
	488	/* err_disable: */
	489	pci_disable_device(esb_pci);
811f9991	490	/* err_devput: */
c69af038	491	pci_dev_put(esb_pci);
0829291e	492	return ret;
cc90ef0f DH	493	}
cc90ef0f DH	494
0829291e	495	static void __exit watchdog_cleanup(void)
cc90ef0f DH	496	{
	497	/* Stop the timer before we leave */
	498	if (!nowayout)
0829291e	499	esb_timer_stop();
cc90ef0f DH	500
	501	/* Deregister */
	502	misc_deregister(&esb_miscdev);
0829291e	503	unregister_reboot_notifier(&esb_notifier);
cc90ef0f DH	504	iounmap(BASEADDR);
	505	pci_release_region(esb_pci, 0);
	506	pci_disable_device(esb_pci);
c69af038	507	pci_dev_put(esb_pci);
cc90ef0f DH	508	}
	509
	510	module_init(watchdog_init);
	511	module_exit(watchdog_cleanup);
	512
96de0e25	513	MODULE_AUTHOR("Ross Biro and David Härdeman");
cc90ef0f DH	514	MODULE_DESCRIPTION("Watchdog driver for Intel 6300ESB chipsets");
	515	MODULE_LICENSE("GPL");
	516	MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);