Commit | Line | Data |
---|---|---|
cc90ef0f | 1 | /* |
abda5c8b | 2 | * i6300esb: Watchdog timer driver for Intel 6300ESB chipset |
cc90ef0f DH |
3 | * |
4 | * (c) Copyright 2004 Google Inc. | |
96de0e25 | 5 | * (c) Copyright 2005 David Härdeman <david@2gen.com> |
cc90ef0f DH |
6 | * |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version | |
10 | * 2 of the License, or (at your option) any later version. | |
11 | * | |
7944d3a5 | 12 | * based on i810-tco.c which is in turn based on softdog.c |
cc90ef0f | 13 | * |
7944d3a5 WVS |
14 | * The timer is implemented in the following I/O controller hubs: |
15 | * (See the intel documentation on http://developer.intel.com.) | |
0426fd0d | 16 | * 6300ESB chip : document number 300641-004 |
cc90ef0f DH |
17 | * |
18 | * 2004YYZZ Ross Biro | |
19 | * Initial version 0.01 | |
20 | * 2004YYZZ Ross Biro | |
7944d3a5 | 21 | * Version 0.02 |
96de0e25 | 22 | * 20050210 David Härdeman <david@2gen.com> |
7944d3a5 | 23 | * Ported driver to kernel 2.6 |
cc90ef0f DH |
24 | */ |
25 | ||
26 | /* | |
27 | * Includes, defines, variables, module parameters, ... | |
28 | */ | |
29 | ||
30 | #include <linux/module.h> | |
31 | #include <linux/types.h> | |
32 | #include <linux/kernel.h> | |
33 | #include <linux/fs.h> | |
34 | #include <linux/mm.h> | |
35 | #include <linux/miscdevice.h> | |
36 | #include <linux/watchdog.h> | |
cc90ef0f DH |
37 | #include <linux/init.h> |
38 | #include <linux/pci.h> | |
39 | #include <linux/ioport.h> | |
0829291e AC |
40 | #include <linux/uaccess.h> |
41 | #include <linux/io.h> | |
cc90ef0f | 42 | |
cc90ef0f | 43 | /* Module and version information */ |
2786095a | 44 | #define ESB_VERSION "0.05" |
cc90ef0f DH |
45 | #define ESB_MODULE_NAME "i6300ESB timer" |
46 | #define ESB_DRIVER_NAME ESB_MODULE_NAME ", v" ESB_VERSION | |
47 | #define PFX ESB_MODULE_NAME ": " | |
48 | ||
abda5c8b DH |
49 | /* PCI configuration registers */ |
50 | #define ESB_CONFIG_REG 0x60 /* Config register */ | |
51 | #define ESB_LOCK_REG 0x68 /* WDT lock register */ | |
52 | ||
53 | /* Memory mapped registers */ | |
bd4e6c18 WVS |
54 | #define ESB_TIMER1_REG (BASEADDR + 0x00)/* Timer1 value after each reset */ |
55 | #define ESB_TIMER2_REG (BASEADDR + 0x04)/* Timer2 value after each reset */ | |
56 | #define ESB_GINTSR_REG (BASEADDR + 0x08)/* General Interrupt Status Register */ | |
57 | #define ESB_RELOAD_REG (BASEADDR + 0x0c)/* Reload register */ | |
abda5c8b DH |
58 | |
59 | /* Lock register bits */ | |
0829291e AC |
60 | #define ESB_WDT_FUNC (0x01 << 2) /* Watchdog functionality */ |
61 | #define ESB_WDT_ENABLE (0x01 << 1) /* Enable WDT */ | |
62 | #define ESB_WDT_LOCK (0x01 << 0) /* Lock (nowayout) */ | |
abda5c8b DH |
63 | |
64 | /* Config register bits */ | |
0829291e AC |
65 | #define ESB_WDT_REBOOT (0x01 << 5) /* Enable reboot on timeout */ |
66 | #define ESB_WDT_FREQ (0x01 << 2) /* Decrement frequency */ | |
39f3be72 | 67 | #define ESB_WDT_INTTYPE (0x03 << 0) /* Interrupt type on timer1 timeout */ |
abda5c8b DH |
68 | |
69 | /* Reload register bits */ | |
31838d9d | 70 | #define ESB_WDT_TIMEOUT (0x01 << 9) /* Watchdog timed out */ |
0829291e | 71 | #define ESB_WDT_RELOAD (0x01 << 8) /* prevent timeout */ |
abda5c8b DH |
72 | |
73 | /* Magic constants */ | |
74 | #define ESB_UNLOCK1 0x80 /* Step 1 to unlock reset registers */ | |
75 | #define ESB_UNLOCK2 0x86 /* Step 2 to unlock reset registers */ | |
76 | ||
cc90ef0f DH |
77 | /* internal variables */ |
78 | static void __iomem *BASEADDR; | |
c7dfd0cc | 79 | static DEFINE_SPINLOCK(esb_lock); /* Guards the hardware */ |
cc90ef0f DH |
80 | static unsigned long timer_alive; |
81 | static struct pci_dev *esb_pci; | |
82 | static unsigned short triggered; /* The status of the watchdog upon boot */ | |
83 | static char esb_expect_close; | |
2786095a WVS |
84 | |
85 | /* We can only use 1 card due to the /dev/watchdog restriction */ | |
86 | static int cards_found; | |
0426fd0d | 87 | |
cc90ef0f | 88 | /* module parameters */ |
0829291e AC |
89 | /* 30 sec default heartbeat (1 < heartbeat < 2*1023) */ |
90 | #define WATCHDOG_HEARTBEAT 30 | |
cc90ef0f DH |
91 | static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */ |
92 | module_param(heartbeat, int, 0); | |
0829291e AC |
93 | MODULE_PARM_DESC(heartbeat, |
94 | "Watchdog heartbeat in seconds. (1<heartbeat<2046, default=" | |
95 | __MODULE_STRING(WATCHDOG_HEARTBEAT) ")"); | |
cc90ef0f | 96 | |
811f9991 | 97 | static int nowayout = WATCHDOG_NOWAYOUT; |
cc90ef0f | 98 | module_param(nowayout, int, 0); |
0829291e AC |
99 | MODULE_PARM_DESC(nowayout, |
100 | "Watchdog cannot be stopped once started (default=" | |
101 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
cc90ef0f DH |
102 | |
103 | /* | |
104 | * Some i6300ESB specific functions | |
105 | */ | |
106 | ||
107 | /* | |
108 | * Prepare for reloading the timer by unlocking the proper registers. | |
109 | * This is performed by first writing 0x80 followed by 0x86 to the | |
110 | * reload register. After this the appropriate registers can be written | |
111 | * to once before they need to be unlocked again. | |
112 | */ | |
7944d3a5 WVS |
113 | static inline void esb_unlock_registers(void) |
114 | { | |
39f3be72 WVS |
115 | writew(ESB_UNLOCK1, ESB_RELOAD_REG); |
116 | writew(ESB_UNLOCK2, ESB_RELOAD_REG); | |
cc90ef0f DH |
117 | } |
118 | ||
3b9d49ee | 119 | static int esb_timer_start(void) |
cc90ef0f DH |
120 | { |
121 | u8 val; | |
122 | ||
3b9d49ee WVS |
123 | spin_lock(&esb_lock); |
124 | esb_unlock_registers(); | |
125 | writew(ESB_WDT_RELOAD, ESB_RELOAD_REG); | |
cc90ef0f | 126 | /* Enable or Enable + Lock? */ |
fc8a9d83 | 127 | val = ESB_WDT_ENABLE | (nowayout ? ESB_WDT_LOCK : 0x00); |
0829291e | 128 | pci_write_config_byte(esb_pci, ESB_LOCK_REG, val); |
3b9d49ee WVS |
129 | spin_unlock(&esb_lock); |
130 | return 0; | |
cc90ef0f DH |
131 | } |
132 | ||
133 | static int esb_timer_stop(void) | |
134 | { | |
135 | u8 val; | |
136 | ||
137 | spin_lock(&esb_lock); | |
138 | /* First, reset timers as suggested by the docs */ | |
139 | esb_unlock_registers(); | |
ce2f50b4 | 140 | writew(ESB_WDT_RELOAD, ESB_RELOAD_REG); |
cc90ef0f DH |
141 | /* Then disable the WDT */ |
142 | pci_write_config_byte(esb_pci, ESB_LOCK_REG, 0x0); | |
143 | pci_read_config_byte(esb_pci, ESB_LOCK_REG, &val); | |
144 | spin_unlock(&esb_lock); | |
145 | ||
146 | /* Returns 0 if the timer was disabled, non-zero otherwise */ | |
fc8a9d83 | 147 | return val & ESB_WDT_ENABLE; |
cc90ef0f DH |
148 | } |
149 | ||
150 | static void esb_timer_keepalive(void) | |
151 | { | |
152 | spin_lock(&esb_lock); | |
153 | esb_unlock_registers(); | |
ce2f50b4 | 154 | writew(ESB_WDT_RELOAD, ESB_RELOAD_REG); |
0829291e | 155 | /* FIXME: Do we need to flush anything here? */ |
cc90ef0f DH |
156 | spin_unlock(&esb_lock); |
157 | } | |
158 | ||
159 | static int esb_timer_set_heartbeat(int time) | |
160 | { | |
161 | u32 val; | |
162 | ||
163 | if (time < 0x1 || time > (2 * 0x03ff)) | |
164 | return -EINVAL; | |
165 | ||
166 | spin_lock(&esb_lock); | |
167 | ||
168 | /* We shift by 9, so if we are passed a value of 1 sec, | |
169 | * val will be 1 << 9 = 512, then write that to two | |
170 | * timers => 2 * 512 = 1024 (which is decremented at 1KHz) | |
171 | */ | |
172 | val = time << 9; | |
173 | ||
174 | /* Write timer 1 */ | |
175 | esb_unlock_registers(); | |
176 | writel(val, ESB_TIMER1_REG); | |
177 | ||
178 | /* Write timer 2 */ | |
179 | esb_unlock_registers(); | |
7944d3a5 | 180 | writel(val, ESB_TIMER2_REG); |
cc90ef0f | 181 | |
0829291e | 182 | /* Reload */ |
cc90ef0f | 183 | esb_unlock_registers(); |
ce2f50b4 | 184 | writew(ESB_WDT_RELOAD, ESB_RELOAD_REG); |
cc90ef0f DH |
185 | |
186 | /* FIXME: Do we need to flush everything out? */ | |
187 | ||
188 | /* Done */ | |
189 | heartbeat = time; | |
190 | spin_unlock(&esb_lock); | |
191 | return 0; | |
192 | } | |
193 | ||
cc90ef0f | 194 | /* |
7944d3a5 | 195 | * /dev/watchdog handling |
cc90ef0f DH |
196 | */ |
197 | ||
0829291e | 198 | static int esb_open(struct inode *inode, struct file *file) |
cc90ef0f | 199 | { |
0829291e AC |
200 | /* /dev/watchdog can only be opened once */ |
201 | if (test_and_set_bit(0, &timer_alive)) | |
202 | return -EBUSY; | |
cc90ef0f | 203 | |
0829291e | 204 | /* Reload and activate timer */ |
0829291e | 205 | esb_timer_start(); |
cc90ef0f DH |
206 | |
207 | return nonseekable_open(inode, file); | |
208 | } | |
209 | ||
0829291e | 210 | static int esb_release(struct inode *inode, struct file *file) |
cc90ef0f | 211 | { |
0829291e AC |
212 | /* Shut off the timer. */ |
213 | if (esb_expect_close == 42) | |
214 | esb_timer_stop(); | |
215 | else { | |
216 | printk(KERN_CRIT PFX | |
217 | "Unexpected close, not stopping watchdog!\n"); | |
218 | esb_timer_keepalive(); | |
219 | } | |
220 | clear_bit(0, &timer_alive); | |
221 | esb_expect_close = 0; | |
222 | return 0; | |
cc90ef0f DH |
223 | } |
224 | ||
0829291e AC |
225 | static ssize_t esb_write(struct file *file, const char __user *data, |
226 | size_t len, loff_t *ppos) | |
cc90ef0f DH |
227 | { |
228 | /* See if we got the magic character 'V' and reload the timer */ | |
0829291e | 229 | if (len) { |
cc90ef0f DH |
230 | if (!nowayout) { |
231 | size_t i; | |
232 | ||
233 | /* note: just in case someone wrote the magic character | |
234 | * five months ago... */ | |
235 | esb_expect_close = 0; | |
236 | ||
143a2e54 WVS |
237 | /* scan to see whether or not we got the |
238 | * magic character */ | |
cc90ef0f DH |
239 | for (i = 0; i != len; i++) { |
240 | char c; | |
7944d3a5 | 241 | if (get_user(c, data + i)) |
cc90ef0f DH |
242 | return -EFAULT; |
243 | if (c == 'V') | |
244 | esb_expect_close = 42; | |
245 | } | |
246 | } | |
247 | ||
248 | /* someone wrote to us, we should reload the timer */ | |
0829291e | 249 | esb_timer_keepalive(); |
cc90ef0f DH |
250 | } |
251 | return len; | |
252 | } | |
253 | ||
0829291e | 254 | static long esb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) |
cc90ef0f DH |
255 | { |
256 | int new_options, retval = -EINVAL; | |
257 | int new_heartbeat; | |
258 | void __user *argp = (void __user *)arg; | |
259 | int __user *p = argp; | |
42747d71 | 260 | static const struct watchdog_info ident = { |
7944d3a5 | 261 | .options = WDIOF_SETTIMEOUT | |
cc90ef0f DH |
262 | WDIOF_KEEPALIVEPING | |
263 | WDIOF_MAGICCLOSE, | |
7944d3a5 WVS |
264 | .firmware_version = 0, |
265 | .identity = ESB_MODULE_NAME, | |
cc90ef0f DH |
266 | }; |
267 | ||
268 | switch (cmd) { | |
0829291e AC |
269 | case WDIOC_GETSUPPORT: |
270 | return copy_to_user(argp, &ident, | |
271 | sizeof(ident)) ? -EFAULT : 0; | |
cc90ef0f | 272 | |
0829291e | 273 | case WDIOC_GETSTATUS: |
31838d9d | 274 | return put_user(0, p); |
cc90ef0f | 275 | |
0829291e AC |
276 | case WDIOC_GETBOOTSTATUS: |
277 | return put_user(triggered, p); | |
cc90ef0f | 278 | |
0829291e AC |
279 | case WDIOC_SETOPTIONS: |
280 | { | |
281 | if (get_user(new_options, p)) | |
282 | return -EFAULT; | |
cc90ef0f | 283 | |
0829291e AC |
284 | if (new_options & WDIOS_DISABLECARD) { |
285 | esb_timer_stop(); | |
286 | retval = 0; | |
287 | } | |
cc90ef0f | 288 | |
0829291e | 289 | if (new_options & WDIOS_ENABLECARD) { |
0829291e AC |
290 | esb_timer_start(); |
291 | retval = 0; | |
292 | } | |
293 | return retval; | |
294 | } | |
0c06090c WVS |
295 | case WDIOC_KEEPALIVE: |
296 | esb_timer_keepalive(); | |
297 | return 0; | |
298 | ||
0829291e AC |
299 | case WDIOC_SETTIMEOUT: |
300 | { | |
301 | if (get_user(new_heartbeat, p)) | |
302 | return -EFAULT; | |
303 | if (esb_timer_set_heartbeat(new_heartbeat)) | |
304 | return -EINVAL; | |
305 | esb_timer_keepalive(); | |
306 | /* Fall */ | |
307 | } | |
308 | case WDIOC_GETTIMEOUT: | |
309 | return put_user(heartbeat, p); | |
310 | default: | |
311 | return -ENOTTY; | |
312 | } | |
cc90ef0f DH |
313 | } |
314 | ||
cc90ef0f DH |
315 | /* |
316 | * Kernel Interfaces | |
317 | */ | |
318 | ||
62322d25 | 319 | static const struct file_operations esb_fops = { |
0829291e AC |
320 | .owner = THIS_MODULE, |
321 | .llseek = no_llseek, | |
322 | .write = esb_write, | |
323 | .unlocked_ioctl = esb_ioctl, | |
324 | .open = esb_open, | |
325 | .release = esb_release, | |
cc90ef0f DH |
326 | }; |
327 | ||
328 | static struct miscdevice esb_miscdev = { | |
0829291e AC |
329 | .minor = WATCHDOG_MINOR, |
330 | .name = "watchdog", | |
331 | .fops = &esb_fops, | |
cc90ef0f DH |
332 | }; |
333 | ||
cc90ef0f DH |
334 | /* |
335 | * Data for PCI driver interface | |
cc90ef0f | 336 | */ |
4562f539 | 337 | static DEFINE_PCI_DEVICE_TABLE(esb_pci_tbl) = { |
0829291e AC |
338 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_9), }, |
339 | { 0, }, /* End of list */ | |
cc90ef0f | 340 | }; |
0829291e | 341 | MODULE_DEVICE_TABLE(pci, esb_pci_tbl); |
cc90ef0f DH |
342 | |
343 | /* | |
344 | * Init & exit routines | |
345 | */ | |
346 | ||
2786095a | 347 | static unsigned char __devinit esb_getdevice(struct pci_dev *pdev) |
cc90ef0f | 348 | { |
2786095a | 349 | if (pci_enable_device(pdev)) { |
fc8a9d83 WVS |
350 | printk(KERN_ERR PFX "failed to enable device\n"); |
351 | goto err_devput; | |
352 | } | |
cc90ef0f | 353 | |
2786095a | 354 | if (pci_request_region(pdev, 0, ESB_MODULE_NAME)) { |
fc8a9d83 WVS |
355 | printk(KERN_ERR PFX "failed to request region\n"); |
356 | goto err_disable; | |
357 | } | |
cc90ef0f | 358 | |
2786095a | 359 | BASEADDR = pci_ioremap_bar(pdev, 0); |
fc8a9d83 WVS |
360 | if (BASEADDR == NULL) { |
361 | /* Something's wrong here, BASEADDR has to be set */ | |
362 | printk(KERN_ERR PFX "failed to get BASEADDR\n"); | |
363 | goto err_release; | |
364 | } | |
365 | ||
366 | /* Done */ | |
2786095a | 367 | esb_pci = pdev; |
fc8a9d83 | 368 | return 1; |
cc90ef0f DH |
369 | |
370 | err_release: | |
2786095a | 371 | pci_release_region(pdev, 0); |
cc90ef0f | 372 | err_disable: |
2786095a | 373 | pci_disable_device(pdev); |
811f9991 | 374 | err_devput: |
cc90ef0f DH |
375 | return 0; |
376 | } | |
377 | ||
fc8a9d83 WVS |
378 | static void __devinit esb_initdevice(void) |
379 | { | |
380 | u8 val1; | |
381 | u16 val2; | |
382 | ||
383 | /* | |
384 | * Config register: | |
385 | * Bit 5 : 0 = Enable WDT_OUTPUT | |
386 | * Bit 2 : 0 = set the timer frequency to the PCI clock | |
387 | * divided by 2^15 (approx 1KHz). | |
388 | * Bits 1:0 : 11 = WDT_INT_TYPE Disabled. | |
389 | * The watchdog has two timers, it can be setup so that the | |
390 | * expiry of timer1 results in an interrupt and the expiry of | |
391 | * timer2 results in a reboot. We set it to not generate | |
392 | * any interrupts as there is not much we can do with it | |
393 | * right now. | |
394 | */ | |
395 | pci_write_config_word(esb_pci, ESB_CONFIG_REG, 0x0003); | |
396 | ||
397 | /* Check that the WDT isn't already locked */ | |
398 | pci_read_config_byte(esb_pci, ESB_LOCK_REG, &val1); | |
399 | if (val1 & ESB_WDT_LOCK) | |
400 | printk(KERN_WARNING PFX "nowayout already set\n"); | |
401 | ||
402 | /* Set the timer to watchdog mode and disable it for now */ | |
403 | pci_write_config_byte(esb_pci, ESB_LOCK_REG, 0x00); | |
404 | ||
405 | /* Check if the watchdog was previously triggered */ | |
406 | esb_unlock_registers(); | |
407 | val2 = readw(ESB_RELOAD_REG); | |
408 | if (val2 & ESB_WDT_TIMEOUT) | |
409 | triggered = WDIOF_CARDRESET; | |
410 | ||
411 | /* Reset WDT_TIMEOUT flag and timers */ | |
412 | esb_unlock_registers(); | |
413 | writew((ESB_WDT_TIMEOUT | ESB_WDT_RELOAD), ESB_RELOAD_REG); | |
414 | ||
415 | /* And set the correct timeout value */ | |
416 | esb_timer_set_heartbeat(heartbeat); | |
417 | } | |
418 | ||
2786095a WVS |
419 | static int __devinit esb_probe(struct pci_dev *pdev, |
420 | const struct pci_device_id *ent) | |
cc90ef0f | 421 | { |
0829291e AC |
422 | int ret; |
423 | ||
2786095a WVS |
424 | cards_found++; |
425 | if (cards_found == 1) | |
426 | printk(KERN_INFO PFX "Intel 6300ESB WatchDog Timer Driver v%s\n", | |
427 | ESB_VERSION); | |
428 | ||
429 | if (cards_found > 1) { | |
430 | printk(KERN_ERR PFX "This driver only supports 1 device\n"); | |
431 | return -ENODEV; | |
432 | } | |
433 | ||
0829291e | 434 | /* Check whether or not the hardware watchdog is there */ |
2786095a | 435 | if (!esb_getdevice(pdev) || esb_pci == NULL) |
0829291e AC |
436 | return -ENODEV; |
437 | ||
438 | /* Check that the heartbeat value is within it's range; | |
439 | if not reset to the default */ | |
fc8a9d83 WVS |
440 | if (heartbeat < 0x1 || heartbeat > 2 * 0x03ff) { |
441 | heartbeat = WATCHDOG_HEARTBEAT; | |
0829291e AC |
442 | printk(KERN_INFO PFX |
443 | "heartbeat value must be 1<heartbeat<2046, using %d\n", | |
444 | heartbeat); | |
445 | } | |
cc90ef0f | 446 | |
fc8a9d83 WVS |
447 | /* Initialize the watchdog and make sure it does not run */ |
448 | esb_initdevice(); | |
449 | ||
450 | /* Register the watchdog so that userspace has access to it */ | |
0829291e AC |
451 | ret = misc_register(&esb_miscdev); |
452 | if (ret != 0) { | |
453 | printk(KERN_ERR PFX | |
454 | "cannot register miscdev on minor=%d (err=%d)\n", | |
455 | WATCHDOG_MINOR, ret); | |
0426fd0d | 456 | goto err_unmap; |
0829291e | 457 | } |
0829291e AC |
458 | printk(KERN_INFO PFX |
459 | "initialized (0x%p). heartbeat=%d sec (nowayout=%d)\n", | |
460 | BASEADDR, heartbeat, nowayout); | |
461 | return 0; | |
cc90ef0f | 462 | |
cc90ef0f DH |
463 | err_unmap: |
464 | iounmap(BASEADDR); | |
cc90ef0f | 465 | pci_release_region(esb_pci, 0); |
cc90ef0f | 466 | pci_disable_device(esb_pci); |
2786095a | 467 | esb_pci = NULL; |
0829291e | 468 | return ret; |
cc90ef0f DH |
469 | } |
470 | ||
2786095a | 471 | static void __devexit esb_remove(struct pci_dev *pdev) |
cc90ef0f DH |
472 | { |
473 | /* Stop the timer before we leave */ | |
474 | if (!nowayout) | |
0829291e | 475 | esb_timer_stop(); |
cc90ef0f DH |
476 | |
477 | /* Deregister */ | |
478 | misc_deregister(&esb_miscdev); | |
cc90ef0f DH |
479 | iounmap(BASEADDR); |
480 | pci_release_region(esb_pci, 0); | |
481 | pci_disable_device(esb_pci); | |
2786095a | 482 | esb_pci = NULL; |
0426fd0d WVS |
483 | } |
484 | ||
2786095a | 485 | static void esb_shutdown(struct pci_dev *pdev) |
0426fd0d WVS |
486 | { |
487 | esb_timer_stop(); | |
488 | } | |
489 | ||
2786095a WVS |
490 | static struct pci_driver esb_driver = { |
491 | .name = ESB_MODULE_NAME, | |
492 | .id_table = esb_pci_tbl, | |
0426fd0d WVS |
493 | .probe = esb_probe, |
494 | .remove = __devexit_p(esb_remove), | |
495 | .shutdown = esb_shutdown, | |
0426fd0d WVS |
496 | }; |
497 | ||
498 | static int __init watchdog_init(void) | |
499 | { | |
2786095a | 500 | return pci_register_driver(&esb_driver); |
0426fd0d WVS |
501 | } |
502 | ||
503 | static void __exit watchdog_cleanup(void) | |
504 | { | |
2786095a | 505 | pci_unregister_driver(&esb_driver); |
0426fd0d | 506 | printk(KERN_INFO PFX "Watchdog Module Unloaded.\n"); |
cc90ef0f DH |
507 | } |
508 | ||
509 | module_init(watchdog_init); | |
510 | module_exit(watchdog_cleanup); | |
511 | ||
96de0e25 | 512 | MODULE_AUTHOR("Ross Biro and David Härdeman"); |
cc90ef0f DH |
513 | MODULE_DESCRIPTION("Watchdog driver for Intel 6300ESB chipsets"); |
514 | MODULE_LICENSE("GPL"); | |
515 | MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); |