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e033351d WVS |
1 | /* |
2 | * intel TCO vendor specific watchdog driver support | |
3 | * | |
12d60e28 | 4 | * (c) Copyright 2006-2009 Wim Van Sebroeck <wim@iguana.be>. |
e033351d WVS |
5 | * |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor | |
12 | * provide warranty for any of this software. This material is | |
13 | * provided "AS-IS" and at no charge. | |
14 | */ | |
15 | ||
16 | /* | |
17 | * Includes, defines, variables, module parameters, ... | |
18 | */ | |
19 | ||
27c766aa JP |
20 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
21 | ||
e033351d | 22 | /* Module and version information */ |
7944d3a5 | 23 | #define DRV_NAME "iTCO_vendor_support" |
55e8ddec | 24 | #define DRV_VERSION "1.04" |
e033351d WVS |
25 | |
26 | /* Includes */ | |
27 | #include <linux/module.h> /* For module specific items */ | |
28 | #include <linux/moduleparam.h> /* For new moduleparam's */ | |
29 | #include <linux/types.h> /* For standard types (like size_t) */ | |
30 | #include <linux/errno.h> /* For the -ENODEV/... values */ | |
31 | #include <linux/kernel.h> /* For printk/panic/... */ | |
32 | #include <linux/init.h> /* For __init/__exit/... */ | |
33 | #include <linux/ioport.h> /* For io-port access */ | |
0e6fa3fb AC |
34 | #include <linux/io.h> /* For inb/outb/... */ |
35 | ||
36 | #include "iTCO_vendor.h" | |
e033351d | 37 | |
e033351d | 38 | /* List of vendor support modes */ |
0e6fa3fb AC |
39 | /* SuperMicro Pentium 3 Era 370SSE+-OEM1/P3TSSE */ |
40 | #define SUPERMICRO_OLD_BOARD 1 | |
41 | /* SuperMicro Pentium 4 / Xeon 4 / EMT64T Era Systems */ | |
42 | #define SUPERMICRO_NEW_BOARD 2 | |
55e8ddec WVS |
43 | /* Broken BIOS */ |
44 | #define BROKEN_BIOS 911 | |
e033351d | 45 | |
0e6fa3fb | 46 | static int vendorsupport; |
e033351d | 47 | module_param(vendorsupport, int, 0); |
143a2e54 | 48 | MODULE_PARM_DESC(vendorsupport, "iTCO vendor specific support mode, default=" |
55e8ddec WVS |
49 | "0 (none), 1=SuperMicro Pent3, 2=SuperMicro Pent4+, " |
50 | "911=Broken SMI BIOS"); | |
e033351d WVS |
51 | |
52 | /* | |
53 | * Vendor Specific Support | |
54 | */ | |
55 | ||
56 | /* | |
57 | * Vendor Support: 1 | |
58 | * Board: Super Micro Computer Inc. 370SSE+-OEM1/P3TSSE | |
59 | * iTCO chipset: ICH2 | |
60 | * | |
61 | * Code contributed by: R. Seretny <lkpatches@paypc.com> | |
62 | * Documentation obtained by R. Seretny from SuperMicro Technical Support | |
63 | * | |
64 | * To enable Watchdog function: | |
65 | * BIOS setup -> Power -> TCO Logic SMI Enable -> Within5Minutes | |
66 | * This setting enables SMI to clear the watchdog expired flag. | |
67 | * If BIOS or CPU fail which may cause SMI hang, then system will | |
68 | * reboot. When application starts to use watchdog function, | |
69 | * application has to take over the control from SMI. | |
70 | * | |
71 | * For P3TSSE, J36 jumper needs to be removed to enable the Watchdog | |
72 | * function. | |
73 | * | |
74 | * Note: The system will reboot when Expire Flag is set TWICE. | |
75 | * So, if the watchdog timer is 20 seconds, then the maximum hang | |
76 | * time is about 40 seconds, and the minimum hang time is about | |
77 | * 20.6 seconds. | |
78 | */ | |
79 | ||
887c8ec7 | 80 | static void supermicro_old_pre_start(struct resource *smires) |
12d60e28 WVS |
81 | { |
82 | unsigned long val32; | |
83 | ||
84 | /* Bit 13: TCO_EN -> 0 = Disables TCO logic generating an SMI# */ | |
887c8ec7 | 85 | val32 = inl(smires->start); |
12d60e28 | 86 | val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */ |
887c8ec7 | 87 | outl(val32, smires->start); /* Needed to activate watchdog */ |
12d60e28 WVS |
88 | } |
89 | ||
887c8ec7 | 90 | static void supermicro_old_pre_stop(struct resource *smires) |
12d60e28 WVS |
91 | { |
92 | unsigned long val32; | |
93 | ||
94 | /* Bit 13: TCO_EN -> 1 = Enables the TCO logic to generate SMI# */ | |
887c8ec7 | 95 | val32 = inl(smires->start); |
12d60e28 | 96 | val32 |= 0x00002000; /* Turn on SMI clearing watchdog */ |
887c8ec7 | 97 | outl(val32, smires->start); /* Needed to deactivate watchdog */ |
12d60e28 WVS |
98 | } |
99 | ||
e033351d WVS |
100 | /* |
101 | * Vendor Support: 2 | |
102 | * Board: Super Micro Computer Inc. P4SBx, P4DPx | |
103 | * iTCO chipset: ICH4 | |
104 | * | |
105 | * Code contributed by: R. Seretny <lkpatches@paypc.com> | |
106 | * Documentation obtained by R. Seretny from SuperMicro Technical Support | |
107 | * | |
108 | * To enable Watchdog function: | |
109 | * 1. BIOS | |
110 | * For P4SBx: | |
111 | * BIOS setup -> Advanced -> Integrated Peripherals -> Watch Dog Feature | |
112 | * For P4DPx: | |
113 | * BIOS setup -> Advanced -> I/O Device Configuration -> Watch Dog | |
114 | * This setting enables or disables Watchdog function. When enabled, the | |
96de0e25 | 115 | * default watchdog timer is set to be 5 minutes (about 4m35s). It is |
e033351d WVS |
116 | * enough to load and run the OS. The application (service or driver) has |
117 | * to take over the control once OS is running up and before watchdog | |
118 | * expires. | |
119 | * | |
120 | * 2. JUMPER | |
121 | * For P4SBx: JP39 | |
122 | * For P4DPx: JP37 | |
123 | * This jumper is used for safety. Closed is enabled. This jumper | |
124 | * prevents user enables watchdog in BIOS by accident. | |
125 | * | |
126 | * To enable Watch Dog function, both BIOS and JUMPER must be enabled. | |
127 | * | |
128 | * The documentation lists motherboards P4SBx and P4DPx series as of | |
129 | * 20-March-2002. However, this code works flawlessly with much newer | |
130 | * motherboards, such as my X6DHR-8G2 (SuperServer 6014H-82). | |
131 | * | |
132 | * The original iTCO driver as written does not actually reset the | |
133 | * watchdog timer on these machines, as a result they reboot after five | |
134 | * minutes. | |
135 | * | |
136 | * NOTE: You may leave the Watchdog function disabled in the SuperMicro | |
137 | * BIOS to avoid a "boot-race"... This driver will enable watchdog | |
138 | * functionality even if it's disabled in the BIOS once the /dev/watchdog | |
139 | * file is opened. | |
140 | */ | |
141 | ||
142 | /* I/O Port's */ | |
0e6fa3fb AC |
143 | #define SM_REGINDEX 0x2e /* SuperMicro ICH4+ Register Index */ |
144 | #define SM_DATAIO 0x2f /* SuperMicro ICH4+ Register Data I/O */ | |
e033351d WVS |
145 | |
146 | /* Control Register's */ | |
0e6fa3fb AC |
147 | #define SM_CTLPAGESW 0x07 /* SuperMicro ICH4+ Control Page Switch */ |
148 | #define SM_CTLPAGE 0x08 /* SuperMicro ICH4+ Control Page Num */ | |
e033351d | 149 | |
0e6fa3fb | 150 | #define SM_WATCHENABLE 0x30 /* Watchdog enable: Bit 0: 0=off, 1=on */ |
e033351d | 151 | |
0e6fa3fb | 152 | #define SM_WATCHPAGE 0x87 /* Watchdog unlock control page */ |
e033351d | 153 | |
0e6fa3fb | 154 | #define SM_ENDWATCH 0xAA /* Watchdog lock control page */ |
e033351d | 155 | |
0e6fa3fb AC |
156 | #define SM_COUNTMODE 0xf5 /* Watchdog count mode select */ |
157 | /* (Bit 3: 0 = seconds, 1 = minutes */ | |
e033351d | 158 | |
0e6fa3fb | 159 | #define SM_WATCHTIMER 0xf6 /* 8-bits, Watchdog timer counter (RW) */ |
e033351d | 160 | |
0e6fa3fb AC |
161 | #define SM_RESETCONTROL 0xf7 /* Watchdog reset control */ |
162 | /* Bit 6: timer is reset by kbd interrupt */ | |
163 | /* Bit 7: timer is reset by mouse interrupt */ | |
e033351d WVS |
164 | |
165 | static void supermicro_new_unlock_watchdog(void) | |
166 | { | |
0e6fa3fb | 167 | /* Write 0x87 to port 0x2e twice */ |
e033351d | 168 | outb(SM_WATCHPAGE, SM_REGINDEX); |
0e6fa3fb AC |
169 | outb(SM_WATCHPAGE, SM_REGINDEX); |
170 | /* Switch to watchdog control page */ | |
171 | outb(SM_CTLPAGESW, SM_REGINDEX); | |
e033351d WVS |
172 | outb(SM_CTLPAGE, SM_DATAIO); |
173 | } | |
174 | ||
175 | static void supermicro_new_lock_watchdog(void) | |
176 | { | |
177 | outb(SM_ENDWATCH, SM_REGINDEX); | |
178 | } | |
179 | ||
180 | static void supermicro_new_pre_start(unsigned int heartbeat) | |
181 | { | |
182 | unsigned int val; | |
183 | ||
184 | supermicro_new_unlock_watchdog(); | |
185 | ||
186 | /* Watchdog timer setting needs to be in seconds*/ | |
187 | outb(SM_COUNTMODE, SM_REGINDEX); | |
188 | val = inb(SM_DATAIO); | |
189 | val &= 0xF7; | |
190 | outb(val, SM_DATAIO); | |
191 | ||
192 | /* Write heartbeat interval to WDOG */ | |
0e6fa3fb | 193 | outb(SM_WATCHTIMER, SM_REGINDEX); |
e033351d WVS |
194 | outb((heartbeat & 255), SM_DATAIO); |
195 | ||
196 | /* Make sure keyboard/mouse interrupts don't interfere */ | |
197 | outb(SM_RESETCONTROL, SM_REGINDEX); | |
198 | val = inb(SM_DATAIO); | |
199 | val &= 0x3f; | |
200 | outb(val, SM_DATAIO); | |
201 | ||
202 | /* enable watchdog by setting bit 0 of Watchdog Enable to 1 */ | |
203 | outb(SM_WATCHENABLE, SM_REGINDEX); | |
204 | val = inb(SM_DATAIO); | |
205 | val |= 0x01; | |
206 | outb(val, SM_DATAIO); | |
207 | ||
208 | supermicro_new_lock_watchdog(); | |
209 | } | |
210 | ||
211 | static void supermicro_new_pre_stop(void) | |
212 | { | |
213 | unsigned int val; | |
214 | ||
215 | supermicro_new_unlock_watchdog(); | |
216 | ||
217 | /* disable watchdog by setting bit 0 of Watchdog Enable to 0 */ | |
218 | outb(SM_WATCHENABLE, SM_REGINDEX); | |
219 | val = inb(SM_DATAIO); | |
220 | val &= 0xFE; | |
221 | outb(val, SM_DATAIO); | |
222 | ||
223 | supermicro_new_lock_watchdog(); | |
224 | } | |
225 | ||
226 | static void supermicro_new_pre_set_heartbeat(unsigned int heartbeat) | |
227 | { | |
228 | supermicro_new_unlock_watchdog(); | |
229 | ||
230 | /* reset watchdog timeout to heartveat value */ | |
231 | outb(SM_WATCHTIMER, SM_REGINDEX); | |
232 | outb((heartbeat & 255), SM_DATAIO); | |
233 | ||
234 | supermicro_new_lock_watchdog(); | |
235 | } | |
236 | ||
55e8ddec WVS |
237 | /* |
238 | * Vendor Support: 911 | |
239 | * Board: Some Intel ICHx based motherboards | |
240 | * iTCO chipset: ICH7+ | |
241 | * | |
242 | * Some Intel motherboards have a broken BIOS implementation: i.e. | |
243 | * the SMI handler clear's the TIMEOUT bit in the TC01_STS register | |
244 | * and does not reload the time. Thus the TCO watchdog does not reboot | |
245 | * the system. | |
246 | * | |
247 | * These are the conclusions of Andriy Gapon <avg@icyb.net.ua> after | |
248 | * debugging: the SMI handler is quite simple - it tests value in | |
249 | * TCO1_CNT against 0x800, i.e. checks TCO_TMR_HLT. If the bit is set | |
250 | * the handler goes into an infinite loop, apparently to allow the | |
251 | * second timeout and reboot. Otherwise it simply clears TIMEOUT bit | |
252 | * in TCO1_STS and that's it. | |
253 | * So the logic seems to be reversed, because it is hard to see how | |
254 | * TIMEOUT can get set to 1 and SMI generated when TCO_TMR_HLT is set | |
255 | * (other than a transitional effect). | |
256 | * | |
257 | * The only fix found to get the motherboard(s) to reboot is to put | |
258 | * the glb_smi_en bit to 0. This is a dirty hack that bypasses the | |
259 | * broken code by disabling Global SMI. | |
260 | * | |
261 | * WARNING: globally disabling SMI could possibly lead to dramatic | |
262 | * problems, especially on laptops! I.e. various ACPI things where | |
263 | * SMI is used for communication between OS and firmware. | |
264 | * | |
265 | * Don't use this fix if you don't need to!!! | |
266 | */ | |
267 | ||
887c8ec7 | 268 | static void broken_bios_start(struct resource *smires) |
55e8ddec WVS |
269 | { |
270 | unsigned long val32; | |
271 | ||
887c8ec7 | 272 | val32 = inl(smires->start); |
55e8ddec WVS |
273 | /* Bit 13: TCO_EN -> 0 = Disables TCO logic generating an SMI# |
274 | Bit 0: GBL_SMI_EN -> 0 = No SMI# will be generated by ICH. */ | |
275 | val32 &= 0xffffdffe; | |
887c8ec7 | 276 | outl(val32, smires->start); |
55e8ddec WVS |
277 | } |
278 | ||
887c8ec7 | 279 | static void broken_bios_stop(struct resource *smires) |
55e8ddec WVS |
280 | { |
281 | unsigned long val32; | |
282 | ||
887c8ec7 | 283 | val32 = inl(smires->start); |
55e8ddec WVS |
284 | /* Bit 13: TCO_EN -> 1 = Enables TCO logic generating an SMI# |
285 | Bit 0: GBL_SMI_EN -> 1 = Turn global SMI on again. */ | |
286 | val32 |= 0x00002001; | |
887c8ec7 | 287 | outl(val32, smires->start); |
55e8ddec WVS |
288 | } |
289 | ||
e033351d WVS |
290 | /* |
291 | * Generic Support Functions | |
292 | */ | |
293 | ||
887c8ec7 | 294 | void iTCO_vendor_pre_start(struct resource *smires, |
e033351d WVS |
295 | unsigned int heartbeat) |
296 | { | |
55e8ddec WVS |
297 | switch (vendorsupport) { |
298 | case SUPERMICRO_OLD_BOARD: | |
887c8ec7 | 299 | supermicro_old_pre_start(smires); |
55e8ddec WVS |
300 | break; |
301 | case SUPERMICRO_NEW_BOARD: | |
e033351d | 302 | supermicro_new_pre_start(heartbeat); |
55e8ddec WVS |
303 | break; |
304 | case BROKEN_BIOS: | |
887c8ec7 | 305 | broken_bios_start(smires); |
55e8ddec WVS |
306 | break; |
307 | } | |
e033351d WVS |
308 | } |
309 | EXPORT_SYMBOL(iTCO_vendor_pre_start); | |
310 | ||
887c8ec7 | 311 | void iTCO_vendor_pre_stop(struct resource *smires) |
e033351d | 312 | { |
55e8ddec WVS |
313 | switch (vendorsupport) { |
314 | case SUPERMICRO_OLD_BOARD: | |
887c8ec7 | 315 | supermicro_old_pre_stop(smires); |
55e8ddec WVS |
316 | break; |
317 | case SUPERMICRO_NEW_BOARD: | |
e033351d | 318 | supermicro_new_pre_stop(); |
55e8ddec WVS |
319 | break; |
320 | case BROKEN_BIOS: | |
887c8ec7 | 321 | broken_bios_stop(smires); |
55e8ddec WVS |
322 | break; |
323 | } | |
e033351d WVS |
324 | } |
325 | EXPORT_SYMBOL(iTCO_vendor_pre_stop); | |
326 | ||
887c8ec7 | 327 | void iTCO_vendor_pre_keepalive(struct resource *smires, unsigned int heartbeat) |
e033351d | 328 | { |
7e6811da | 329 | if (vendorsupport == SUPERMICRO_NEW_BOARD) |
e033351d WVS |
330 | supermicro_new_pre_set_heartbeat(heartbeat); |
331 | } | |
332 | EXPORT_SYMBOL(iTCO_vendor_pre_keepalive); | |
333 | ||
334 | void iTCO_vendor_pre_set_heartbeat(unsigned int heartbeat) | |
335 | { | |
336 | if (vendorsupport == SUPERMICRO_NEW_BOARD) | |
337 | supermicro_new_pre_set_heartbeat(heartbeat); | |
338 | } | |
339 | EXPORT_SYMBOL(iTCO_vendor_pre_set_heartbeat); | |
340 | ||
341 | int iTCO_vendor_check_noreboot_on(void) | |
342 | { | |
0e6fa3fb | 343 | switch (vendorsupport) { |
e033351d WVS |
344 | case SUPERMICRO_OLD_BOARD: |
345 | return 0; | |
346 | default: | |
347 | return 1; | |
348 | } | |
349 | } | |
350 | EXPORT_SYMBOL(iTCO_vendor_check_noreboot_on); | |
351 | ||
352 | static int __init iTCO_vendor_init_module(void) | |
353 | { | |
27c766aa | 354 | pr_info("vendor-support=%d\n", vendorsupport); |
e033351d WVS |
355 | return 0; |
356 | } | |
357 | ||
358 | static void __exit iTCO_vendor_exit_module(void) | |
359 | { | |
27c766aa | 360 | pr_info("Module Unloaded\n"); |
e033351d WVS |
361 | } |
362 | ||
363 | module_init(iTCO_vendor_init_module); | |
364 | module_exit(iTCO_vendor_exit_module); | |
365 | ||
143a2e54 WVS |
366 | MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>, " |
367 | "R. Seretny <lkpatches@paypc.com>"); | |
e033351d WVS |
368 | MODULE_DESCRIPTION("Intel TCO Vendor Specific WatchDog Timer Driver Support"); |
369 | MODULE_VERSION(DRV_VERSION); | |
370 | MODULE_LICENSE("GPL"); | |
371 |