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watchdog: pnx4008: don't use __raw_-accessors
[deliverable/linux.git] / drivers / watchdog / iTCO_wdt.c
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9e0ea345 1/*
cb711a19 2 * intel TCO Watchdog Driver
9e0ea345 3 *
deb9197b 4 * (c) Copyright 2006-2011 Wim Van Sebroeck <wim@iguana.be>.
9e0ea345
WVS		 5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
12 * provide warranty for any of this software. This material is
13 * provided "AS-IS" and at no charge.
14 *
15 * The TCO watchdog is implemented in the following I/O controller hubs:
16 * (See the intel documentation on http://developer.intel.com.)
cb711a19
WVS		 17 * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
18 * document number 290687-002, 298242-027: 82801BA (ICH2)
19 * document number 290733-003, 290739-013: 82801CA (ICH3-S)
20 * document number 290716-001, 290718-007: 82801CAM (ICH3-M)
21 * document number 290744-001, 290745-025: 82801DB (ICH4)
22 * document number 252337-001, 252663-008: 82801DBM (ICH4-M)
23 * document number 273599-001, 273645-002: 82801E (C-ICH)
24 * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
25 * document number 300641-004, 300884-013: 6300ESB
26 * document number 301473-002, 301474-026: 82801F (ICH6)
27 * document number 313082-001, 313075-006: 631xESB, 632xESB
28 * document number 307013-003, 307014-024: 82801G (ICH7)
d38bd479 29 * document number 322896-001, 322897-001: NM10
cb711a19
WVS		 30 * document number 313056-003, 313057-017: 82801H (ICH8)
31 * document number 316972-004, 316973-012: 82801I (ICH9)
32 * document number 319973-002, 319974-002: 82801J (ICH10)
3c9d8ecc 33 * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
4946f835 34 * document number 320066-003, 320257-008: EP80597 (IICH)
203f8d89 35 * document number 324645-001, 324646-001: Cougar Point (CPT)
c54fb811 36 * document number TBD : Patsburg (PBG)
203f8d89 37 * document number TBD : DH89xxCC
aa1f4652 38 * document number TBD : Panther Point
84e83c28 39 * document number TBD : Lynx Point
9e0ea345
WVS		 40 */
41
42/*
43 * Includes, defines, variables, module parameters, ...
44 */
45
46/* Module and version information */
7944d3a5 47#define DRV_NAME "iTCO_wdt"
deb9197b 48#define DRV_VERSION "1.07"
9e0ea345
WVS		 49#define PFX DRV_NAME ": "
50
51/* Includes */
3836cc0f
WVS		 52#include <linux/module.h> /* For module specific items */
53#include <linux/moduleparam.h> /* For new moduleparam's */
54#include <linux/types.h> /* For standard types (like size_t) */
55#include <linux/errno.h> /* For the -ENODEV/... values */
56#include <linux/kernel.h> /* For printk/panic/... */
0e6fa3fb
AC		 57#include <linux/miscdevice.h> /* For MODULE_ALIAS_MISCDEV
58 (WATCHDOG_MINOR) */
3836cc0f 59#include <linux/watchdog.h> /* For the watchdog specific items */
3836cc0f
WVS		 60#include <linux/init.h> /* For __init/__exit/... */
61#include <linux/fs.h> /* For file operations */
62#include <linux/platform_device.h> /* For platform_driver framework */
63#include <linux/pci.h> /* For pci functions */
64#include <linux/ioport.h> /* For io-port access */
65#include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */
0e6fa3fb
AC		 66#include <linux/uaccess.h> /* For copy_to_user/put_user/... */
67#include <linux/io.h> /* For inb/outb/... */
3836cc0f 68
0e6fa3fb 69#include "iTCO_vendor.h"
9e0ea345
WVS		 70
71/* TCO related info */
72enum iTCO_chipsets {
73 TCO_ICH = 0, /* ICH */
74 TCO_ICH0, /* ICH0 */
75 TCO_ICH2, /* ICH2 */
76 TCO_ICH2M, /* ICH2-M */
77 TCO_ICH3, /* ICH3-S */
78 TCO_ICH3M, /* ICH3-M */
79 TCO_ICH4, /* ICH4 */
80 TCO_ICH4M, /* ICH4-M */
81 TCO_CICH, /* C-ICH */
82 TCO_ICH5, /* ICH5 & ICH5R */
83 TCO_6300ESB, /* 6300ESB */
84 TCO_ICH6, /* ICH6 & ICH6R */
85 TCO_ICH6M, /* ICH6-M */
86 TCO_ICH6W, /* ICH6W & ICH6RW */
28d41f53 87 TCO_631XESB, /* 631xESB/632xESB */
9e0ea345 88 TCO_ICH7, /* ICH7 & ICH7R */
28d41f53
WVS		 89 TCO_ICH7DH, /* ICH7DH */
90 TCO_ICH7M, /* ICH7-M & ICH7-U */
9e0ea345 91 TCO_ICH7MDH, /* ICH7-M DH */
d38bd479 92 TCO_NM10, /* NM10 */
a8edd74e
WVS		 93 TCO_ICH8, /* ICH8 & ICH8R */
94 TCO_ICH8DH, /* ICH8DH */
95 TCO_ICH8DO, /* ICH8DO */
acf60351 96 TCO_ICH8M, /* ICH8M */
28d41f53 97 TCO_ICH8ME, /* ICH8M-E */
286201dc
WVS		 98 TCO_ICH9, /* ICH9 */
99 TCO_ICH9R, /* ICH9R */
100 TCO_ICH9DH, /* ICH9DH */
7944d3a5 101 TCO_ICH9DO, /* ICH9DO */
28d41f53
WVS		 102 TCO_ICH9M, /* ICH9M */
103 TCO_ICH9ME, /* ICH9M-E */
104 TCO_ICH10, /* ICH10 */
105 TCO_ICH10R, /* ICH10R */
106 TCO_ICH10D, /* ICH10D */
107 TCO_ICH10DO, /* ICH10DO */
79e8941d
SH		 108 TCO_PCH, /* PCH Desktop Full Featured */
109 TCO_PCHM, /* PCH Mobile Full Featured */
3c9d8ecc
SH		 110 TCO_P55, /* P55 */
111 TCO_PM55, /* PM55 */
112 TCO_H55, /* H55 */
113 TCO_QM57, /* QM57 */
114 TCO_H57, /* H57 */
115 TCO_HM55, /* HM55 */
116 TCO_Q57, /* Q57 */
117 TCO_HM57, /* HM57 */
79e8941d 118 TCO_PCHMSFF, /* PCH Mobile SFF Full Featured */
3c9d8ecc
SH		 119 TCO_QS57, /* QS57 */
120 TCO_3400, /* 3400 */
121 TCO_3420, /* 3420 */
122 TCO_3450, /* 3450 */
4946f835 123 TCO_EP80579, /* EP80579 */
97b08a62
WVS		 124 TCO_CPT, /* Cougar Point */
125 TCO_CPTD, /* Cougar Point Desktop */
126 TCO_CPTM, /* Cougar Point Mobile */
127 TCO_PBG, /* Patsburg */
203f8d89 128 TCO_DH89XXCC, /* DH89xxCC */
97b08a62 129 TCO_PPT, /* Panther Point */
84e83c28 130 TCO_LPT, /* Lynx Point */
9e0ea345
WVS		 131};
132
133static struct {
134 char *name;
135 unsigned int iTCO_version;
136} iTCO_chipset_info[] __devinitdata = {
137 {"ICH", 1},
138 {"ICH0", 1},
139 {"ICH2", 1},
140 {"ICH2-M", 1},
141 {"ICH3-S", 1},
142 {"ICH3-M", 1},
143 {"ICH4", 1},
144 {"ICH4-M", 1},
145 {"C-ICH", 1},
146 {"ICH5 or ICH5R", 1},
147 {"6300ESB", 1},
148 {"ICH6 or ICH6R", 2},
149 {"ICH6-M", 2},
150 {"ICH6W or ICH6RW", 2},
28d41f53 151 {"631xESB/632xESB", 2},
9e0ea345 152 {"ICH7 or ICH7R", 2},
28d41f53
WVS		 153 {"ICH7DH", 2},
154 {"ICH7-M or ICH7-U", 2},
9e0ea345 155 {"ICH7-M DH", 2},
d38bd479 156 {"NM10", 2},
bcbf25bd 157 {"ICH8 or ICH8R", 2},
a8edd74e
WVS		 158 {"ICH8DH", 2},
159 {"ICH8DO", 2},
acf60351 160 {"ICH8M", 2},
28d41f53 161 {"ICH8M-E", 2},
286201dc
WVS		 162 {"ICH9", 2},
163 {"ICH9R", 2},
164 {"ICH9DH", 2},
a49056da 165 {"ICH9DO", 2},
28d41f53
WVS		 166 {"ICH9M", 2},
167 {"ICH9M-E", 2},
168 {"ICH10", 2},
169 {"ICH10R", 2},
170 {"ICH10D", 2},
171 {"ICH10DO", 2},
79e8941d
SH		 172 {"PCH Desktop Full Featured", 2},
173 {"PCH Mobile Full Featured", 2},
3c9d8ecc
SH		 174 {"P55", 2},
175 {"PM55", 2},
176 {"H55", 2},
177 {"QM57", 2},
178 {"H57", 2},
179 {"HM55", 2},
180 {"Q57", 2},
181 {"HM57", 2},
79e8941d 182 {"PCH Mobile SFF Full Featured", 2},
3c9d8ecc
SH		 183 {"QS57", 2},
184 {"3400", 2},
185 {"3420", 2},
186 {"3450", 2},
4946f835 187 {"EP80579", 2},
4c7d8492 188 {"Cougar Point", 2},
97b08a62
WVS		 189 {"Cougar Point Desktop", 2},
190 {"Cougar Point Mobile", 2},
c54fb811 191 {"Patsburg", 2},
203f8d89 192 {"DH89xxCC", 2},
aa1f4652 193 {"Panther Point", 2},
84e83c28 194 {"Lynx Point", 2},
0e6fa3fb 195 {NULL, 0}
9e0ea345
WVS		 196};
197
198/*
199 * This data only exists for exporting the supported PCI ids
200 * via MODULE_DEVICE_TABLE. We do not actually register a
201 * pci_driver, because the I/O Controller Hub has also other
202 * functions that probably will be registered by other drivers.
203 */
4562f539 204static DEFINE_PCI_DEVICE_TABLE(iTCO_wdt_pci_tbl) = {
97b08a62
WVS		 205 { PCI_VDEVICE(INTEL, 0x2410), TCO_ICH},
206 { PCI_VDEVICE(INTEL, 0x2420), TCO_ICH0},
207 { PCI_VDEVICE(INTEL, 0x2440), TCO_ICH2},
208 { PCI_VDEVICE(INTEL, 0x244c), TCO_ICH2M},
209 { PCI_VDEVICE(INTEL, 0x2480), TCO_ICH3},
210 { PCI_VDEVICE(INTEL, 0x248c), TCO_ICH3M},
211 { PCI_VDEVICE(INTEL, 0x24c0), TCO_ICH4},
212 { PCI_VDEVICE(INTEL, 0x24cc), TCO_ICH4M},
213 { PCI_VDEVICE(INTEL, 0x2450), TCO_CICH},
214 { PCI_VDEVICE(INTEL, 0x24d0), TCO_ICH5},
215 { PCI_VDEVICE(INTEL, 0x25a1), TCO_6300ESB},
216 { PCI_VDEVICE(INTEL, 0x2640), TCO_ICH6},
217 { PCI_VDEVICE(INTEL, 0x2641), TCO_ICH6M},
218 { PCI_VDEVICE(INTEL, 0x2642), TCO_ICH6W},
219 { PCI_VDEVICE(INTEL, 0x2670), TCO_631XESB},
220 { PCI_VDEVICE(INTEL, 0x2671), TCO_631XESB},
221 { PCI_VDEVICE(INTEL, 0x2672), TCO_631XESB},
222 { PCI_VDEVICE(INTEL, 0x2673), TCO_631XESB},
223 { PCI_VDEVICE(INTEL, 0x2674), TCO_631XESB},
224 { PCI_VDEVICE(INTEL, 0x2675), TCO_631XESB},
225 { PCI_VDEVICE(INTEL, 0x2676), TCO_631XESB},
226 { PCI_VDEVICE(INTEL, 0x2677), TCO_631XESB},
227 { PCI_VDEVICE(INTEL, 0x2678), TCO_631XESB},
228 { PCI_VDEVICE(INTEL, 0x2679), TCO_631XESB},
229 { PCI_VDEVICE(INTEL, 0x267a), TCO_631XESB},
230 { PCI_VDEVICE(INTEL, 0x267b), TCO_631XESB},
231 { PCI_VDEVICE(INTEL, 0x267c), TCO_631XESB},
232 { PCI_VDEVICE(INTEL, 0x267d), TCO_631XESB},
233 { PCI_VDEVICE(INTEL, 0x267e), TCO_631XESB},
234 { PCI_VDEVICE(INTEL, 0x267f), TCO_631XESB},
235 { PCI_VDEVICE(INTEL, 0x27b8), TCO_ICH7},
236 { PCI_VDEVICE(INTEL, 0x27b0), TCO_ICH7DH},
237 { PCI_VDEVICE(INTEL, 0x27b9), TCO_ICH7M},
238 { PCI_VDEVICE(INTEL, 0x27bd), TCO_ICH7MDH},
239 { PCI_VDEVICE(INTEL, 0x27bc), TCO_NM10},
240 { PCI_VDEVICE(INTEL, 0x2810), TCO_ICH8},
241 { PCI_VDEVICE(INTEL, 0x2812), TCO_ICH8DH},
242 { PCI_VDEVICE(INTEL, 0x2814), TCO_ICH8DO},
243 { PCI_VDEVICE(INTEL, 0x2815), TCO_ICH8M},
244 { PCI_VDEVICE(INTEL, 0x2811), TCO_ICH8ME},
245 { PCI_VDEVICE(INTEL, 0x2918), TCO_ICH9},
246 { PCI_VDEVICE(INTEL, 0x2916), TCO_ICH9R},
247 { PCI_VDEVICE(INTEL, 0x2912), TCO_ICH9DH},
248 { PCI_VDEVICE(INTEL, 0x2914), TCO_ICH9DO},
249 { PCI_VDEVICE(INTEL, 0x2919), TCO_ICH9M},
250 { PCI_VDEVICE(INTEL, 0x2917), TCO_ICH9ME},
251 { PCI_VDEVICE(INTEL, 0x3a18), TCO_ICH10},
252 { PCI_VDEVICE(INTEL, 0x3a16), TCO_ICH10R},
253 { PCI_VDEVICE(INTEL, 0x3a1a), TCO_ICH10D},
254 { PCI_VDEVICE(INTEL, 0x3a14), TCO_ICH10DO},
255 { PCI_VDEVICE(INTEL, 0x3b00), TCO_PCH},
256 { PCI_VDEVICE(INTEL, 0x3b01), TCO_PCHM},
257 { PCI_VDEVICE(INTEL, 0x3b02), TCO_P55},
258 { PCI_VDEVICE(INTEL, 0x3b03), TCO_PM55},
259 { PCI_VDEVICE(INTEL, 0x3b06), TCO_H55},
260 { PCI_VDEVICE(INTEL, 0x3b07), TCO_QM57},
261 { PCI_VDEVICE(INTEL, 0x3b08), TCO_H57},
262 { PCI_VDEVICE(INTEL, 0x3b09), TCO_HM55},
263 { PCI_VDEVICE(INTEL, 0x3b0a), TCO_Q57},
264 { PCI_VDEVICE(INTEL, 0x3b0b), TCO_HM57},
265 { PCI_VDEVICE(INTEL, 0x3b0d), TCO_PCHMSFF},
266 { PCI_VDEVICE(INTEL, 0x3b0f), TCO_QS57},
267 { PCI_VDEVICE(INTEL, 0x3b12), TCO_3400},
268 { PCI_VDEVICE(INTEL, 0x3b14), TCO_3420},
269 { PCI_VDEVICE(INTEL, 0x3b16), TCO_3450},
270 { PCI_VDEVICE(INTEL, 0x5031), TCO_EP80579},
271 { PCI_VDEVICE(INTEL, 0x1c41), TCO_CPT},
272 { PCI_VDEVICE(INTEL, 0x1c42), TCO_CPTD},
273 { PCI_VDEVICE(INTEL, 0x1c43), TCO_CPTM},
274 { PCI_VDEVICE(INTEL, 0x1c44), TCO_CPT},
275 { PCI_VDEVICE(INTEL, 0x1c45), TCO_CPT},
276 { PCI_VDEVICE(INTEL, 0x1c46), TCO_CPT},
277 { PCI_VDEVICE(INTEL, 0x1c47), TCO_CPT},
278 { PCI_VDEVICE(INTEL, 0x1c48), TCO_CPT},
279 { PCI_VDEVICE(INTEL, 0x1c49), TCO_CPT},
280 { PCI_VDEVICE(INTEL, 0x1c4a), TCO_CPT},
281 { PCI_VDEVICE(INTEL, 0x1c4b), TCO_CPT},
282 { PCI_VDEVICE(INTEL, 0x1c4c), TCO_CPT},
283 { PCI_VDEVICE(INTEL, 0x1c4d), TCO_CPT},
284 { PCI_VDEVICE(INTEL, 0x1c4e), TCO_CPT},
285 { PCI_VDEVICE(INTEL, 0x1c4f), TCO_CPT},
286 { PCI_VDEVICE(INTEL, 0x1c50), TCO_CPT},
287 { PCI_VDEVICE(INTEL, 0x1c51), TCO_CPT},
288 { PCI_VDEVICE(INTEL, 0x1c52), TCO_CPT},
289 { PCI_VDEVICE(INTEL, 0x1c53), TCO_CPT},
290 { PCI_VDEVICE(INTEL, 0x1c54), TCO_CPT},
291 { PCI_VDEVICE(INTEL, 0x1c55), TCO_CPT},
292 { PCI_VDEVICE(INTEL, 0x1c56), TCO_CPT},
293 { PCI_VDEVICE(INTEL, 0x1c57), TCO_CPT},
294 { PCI_VDEVICE(INTEL, 0x1c58), TCO_CPT},
295 { PCI_VDEVICE(INTEL, 0x1c59), TCO_CPT},
296 { PCI_VDEVICE(INTEL, 0x1c5a), TCO_CPT},
297 { PCI_VDEVICE(INTEL, 0x1c5b), TCO_CPT},
298 { PCI_VDEVICE(INTEL, 0x1c5c), TCO_CPT},
299 { PCI_VDEVICE(INTEL, 0x1c5d), TCO_CPT},
300 { PCI_VDEVICE(INTEL, 0x1c5e), TCO_CPT},
301 { PCI_VDEVICE(INTEL, 0x1c5f), TCO_CPT},
302 { PCI_VDEVICE(INTEL, 0x1d40), TCO_PBG},
303 { PCI_VDEVICE(INTEL, 0x1d41), TCO_PBG},
304 { PCI_VDEVICE(INTEL, 0x2310), TCO_DH89XXCC},
305 { PCI_VDEVICE(INTEL, 0x1e40), TCO_PPT},
306 { PCI_VDEVICE(INTEL, 0x1e41), TCO_PPT},
307 { PCI_VDEVICE(INTEL, 0x1e42), TCO_PPT},
308 { PCI_VDEVICE(INTEL, 0x1e43), TCO_PPT},
309 { PCI_VDEVICE(INTEL, 0x1e44), TCO_PPT},
310 { PCI_VDEVICE(INTEL, 0x1e45), TCO_PPT},
311 { PCI_VDEVICE(INTEL, 0x1e46), TCO_PPT},
312 { PCI_VDEVICE(INTEL, 0x1e47), TCO_PPT},
313 { PCI_VDEVICE(INTEL, 0x1e48), TCO_PPT},
314 { PCI_VDEVICE(INTEL, 0x1e49), TCO_PPT},
315 { PCI_VDEVICE(INTEL, 0x1e4a), TCO_PPT},
316 { PCI_VDEVICE(INTEL, 0x1e4b), TCO_PPT},
317 { PCI_VDEVICE(INTEL, 0x1e4c), TCO_PPT},
318 { PCI_VDEVICE(INTEL, 0x1e4d), TCO_PPT},
319 { PCI_VDEVICE(INTEL, 0x1e4e), TCO_PPT},
320 { PCI_VDEVICE(INTEL, 0x1e4f), TCO_PPT},
321 { PCI_VDEVICE(INTEL, 0x1e50), TCO_PPT},
322 { PCI_VDEVICE(INTEL, 0x1e51), TCO_PPT},
323 { PCI_VDEVICE(INTEL, 0x1e52), TCO_PPT},
324 { PCI_VDEVICE(INTEL, 0x1e53), TCO_PPT},
325 { PCI_VDEVICE(INTEL, 0x1e54), TCO_PPT},
326 { PCI_VDEVICE(INTEL, 0x1e55), TCO_PPT},
327 { PCI_VDEVICE(INTEL, 0x1e56), TCO_PPT},
328 { PCI_VDEVICE(INTEL, 0x1e57), TCO_PPT},
329 { PCI_VDEVICE(INTEL, 0x1e58), TCO_PPT},
330 { PCI_VDEVICE(INTEL, 0x1e59), TCO_PPT},
331 { PCI_VDEVICE(INTEL, 0x1e5a), TCO_PPT},
332 { PCI_VDEVICE(INTEL, 0x1e5b), TCO_PPT},
333 { PCI_VDEVICE(INTEL, 0x1e5c), TCO_PPT},
334 { PCI_VDEVICE(INTEL, 0x1e5d), TCO_PPT},
335 { PCI_VDEVICE(INTEL, 0x1e5e), TCO_PPT},
336 { PCI_VDEVICE(INTEL, 0x1e5f), TCO_PPT},
84e83c28
SH		 337 { PCI_VDEVICE(INTEL, 0x8c40), TCO_LPT},
338 { PCI_VDEVICE(INTEL, 0x8c41), TCO_LPT},
339 { PCI_VDEVICE(INTEL, 0x8c42), TCO_LPT},
340 { PCI_VDEVICE(INTEL, 0x8c43), TCO_LPT},
341 { PCI_VDEVICE(INTEL, 0x8c44), TCO_LPT},
342 { PCI_VDEVICE(INTEL, 0x8c45), TCO_LPT},
343 { PCI_VDEVICE(INTEL, 0x8c46), TCO_LPT},
344 { PCI_VDEVICE(INTEL, 0x8c47), TCO_LPT},
345 { PCI_VDEVICE(INTEL, 0x8c48), TCO_LPT},
346 { PCI_VDEVICE(INTEL, 0x8c49), TCO_LPT},
347 { PCI_VDEVICE(INTEL, 0x8c4a), TCO_LPT},
348 { PCI_VDEVICE(INTEL, 0x8c4b), TCO_LPT},
349 { PCI_VDEVICE(INTEL, 0x8c4c), TCO_LPT},
350 { PCI_VDEVICE(INTEL, 0x8c4d), TCO_LPT},
351 { PCI_VDEVICE(INTEL, 0x8c4e), TCO_LPT},
352 { PCI_VDEVICE(INTEL, 0x8c4f), TCO_LPT},
353 { PCI_VDEVICE(INTEL, 0x8c50), TCO_LPT},
354 { PCI_VDEVICE(INTEL, 0x8c51), TCO_LPT},
355 { PCI_VDEVICE(INTEL, 0x8c52), TCO_LPT},
356 { PCI_VDEVICE(INTEL, 0x8c53), TCO_LPT},
357 { PCI_VDEVICE(INTEL, 0x8c54), TCO_LPT},
358 { PCI_VDEVICE(INTEL, 0x8c55), TCO_LPT},
359 { PCI_VDEVICE(INTEL, 0x8c56), TCO_LPT},
360 { PCI_VDEVICE(INTEL, 0x8c57), TCO_LPT},
361 { PCI_VDEVICE(INTEL, 0x8c58), TCO_LPT},
362 { PCI_VDEVICE(INTEL, 0x8c59), TCO_LPT},
363 { PCI_VDEVICE(INTEL, 0x8c5a), TCO_LPT},
364 { PCI_VDEVICE(INTEL, 0x8c5b), TCO_LPT},
365 { PCI_VDEVICE(INTEL, 0x8c5c), TCO_LPT},
366 { PCI_VDEVICE(INTEL, 0x8c5d), TCO_LPT},
367 { PCI_VDEVICE(INTEL, 0x8c5e), TCO_LPT},
368 { PCI_VDEVICE(INTEL, 0x8c5f), TCO_LPT},
9e0ea345
WVS		 369 { 0, }, /* End of list */
370};
0e6fa3fb 371MODULE_DEVICE_TABLE(pci, iTCO_wdt_pci_tbl);
9e0ea345
WVS		 372
373/* Address definitions for the TCO */
0e6fa3fb 374/* TCO base address */
0a7e6582 375#define TCOBASE (iTCO_wdt_private.ACPIBASE + 0x60)
0e6fa3fb 376/* SMI Control and Enable Register */
0a7e6582 377#define SMI_EN (iTCO_wdt_private.ACPIBASE + 0x30)
9e0ea345 378
0a7e6582
WVS		 379#define TCO_RLD (TCOBASE + 0x00) /* TCO Timer Reload and Curr. Value */
380#define TCOv1_TMR (TCOBASE + 0x01) /* TCOv1 Timer Initial Value */
381#define TCO_DAT_IN (TCOBASE + 0x02) /* TCO Data In Register */
382#define TCO_DAT_OUT (TCOBASE + 0x03) /* TCO Data Out Register */
383#define TCO1_STS (TCOBASE + 0x04) /* TCO1 Status Register */
384#define TCO2_STS (TCOBASE + 0x06) /* TCO2 Status Register */
385#define TCO1_CNT (TCOBASE + 0x08) /* TCO1 Control Register */
386#define TCO2_CNT (TCOBASE + 0x0a) /* TCO2 Control Register */
387#define TCOv2_TMR (TCOBASE + 0x12) /* TCOv2 Timer Initial Value */
9e0ea345
WVS		 388
389/* internal variables */
390static unsigned long is_active;
391static char expect_release;
0e6fa3fb
AC		 392static struct { /* this is private data for the iTCO_wdt device */
393 /* TCO version/generation */
394 unsigned int iTCO_version;
641912f4 395 /* The device's ACPIBASE address (TCOBASE = ACPIBASE+0x60) */
0e6fa3fb
AC		 396 unsigned long ACPIBASE;
397 /* NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2)*/
398 unsigned long __iomem *gcs;
399 /* the lock for io operations */
400 spinlock_t io_lock;
401 /* the PCI-device */
402 struct pci_dev *pdev;
9e0ea345
WVS		 403} iTCO_wdt_private;
404
0e6fa3fb
AC		 405/* the watchdog platform device */
406static struct platform_device *iTCO_wdt_platform_device;
3836cc0f 407
9e0ea345
WVS		 408/* module parameters */
409#define WATCHDOG_HEARTBEAT 30 /* 30 sec default heartbeat */
410static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
411module_param(heartbeat, int, 0);
7e6811da
PB		 412MODULE_PARM_DESC(heartbeat, "Watchdog timeout in seconds. "
413 "5..76 (TCO v1) or 3..614 (TCO v2), default="
143a2e54 414 __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
9e0ea345
WVS		 415
416static int nowayout = WATCHDOG_NOWAYOUT;
417module_param(nowayout, int, 0);
0e6fa3fb
AC		 418MODULE_PARM_DESC(nowayout,
419 "Watchdog cannot be stopped once started (default="
420 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
e033351d 421
0d098587 422static int turn_SMI_watchdog_clear_off = 1;
deb9197b
WVS		 423module_param(turn_SMI_watchdog_clear_off, int, 0);
424MODULE_PARM_DESC(turn_SMI_watchdog_clear_off,
0d098587 425 "Turn off SMI clearing watchdog (depends on TCO-version)(default=1)");
deb9197b 426
9e0ea345
WVS		 427/*
428 * Some TCO specific functions
429 */
430
431static inline unsigned int seconds_to_ticks(int seconds)
432{
433 /* the internal timer is stored as ticks which decrement
434 * every 0.6 seconds */
435 return (seconds * 10) / 6;
436}
437
438static void iTCO_wdt_set_NO_REBOOT_bit(void)
439{
440 u32 val32;
441
442 /* Set the NO_REBOOT bit: this disables reboots */
443 if (iTCO_wdt_private.iTCO_version == 2) {
444 val32 = readl(iTCO_wdt_private.gcs);
445 val32 |= 0x00000020;
446 writel(val32, iTCO_wdt_private.gcs);
447 } else if (iTCO_wdt_private.iTCO_version == 1) {
448 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
449 val32 |= 0x00000002;
450 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
451 }
452}
453
454static int iTCO_wdt_unset_NO_REBOOT_bit(void)
455{
456 int ret = 0;
457 u32 val32;
458
459 /* Unset the NO_REBOOT bit: this enables reboots */
460 if (iTCO_wdt_private.iTCO_version == 2) {
461 val32 = readl(iTCO_wdt_private.gcs);
462 val32 &= 0xffffffdf;
463 writel(val32, iTCO_wdt_private.gcs);
464
465 val32 = readl(iTCO_wdt_private.gcs);
466 if (val32 & 0x00000020)
467 ret = -EIO;
468 } else if (iTCO_wdt_private.iTCO_version == 1) {
469 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
470 val32 &= 0xfffffffd;
471 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
472
473 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
474 if (val32 & 0x00000002)
475 ret = -EIO;
476 }
477
478 return ret; /* returns: 0 = OK, -EIO = Error */
479}
480
481static int iTCO_wdt_start(void)
482{
483 unsigned int val;
484
485 spin_lock(&iTCO_wdt_private.io_lock);
486
e033351d
WVS		 487 iTCO_vendor_pre_start(iTCO_wdt_private.ACPIBASE, heartbeat);
488
9e0ea345
WVS		 489 /* disable chipset's NO_REBOOT bit */
490 if (iTCO_wdt_unset_NO_REBOOT_bit()) {
2ba7d7b3 491 spin_unlock(&iTCO_wdt_private.io_lock);
143a2e54 492 printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, "
641912f4 493 "reboot disabled by hardware/BIOS\n");
9e0ea345
WVS		 494 return -EIO;
495 }
496
7cd5b08b
WVS		 497 /* Force the timer to its reload value by writing to the TCO_RLD
498 register */
499 if (iTCO_wdt_private.iTCO_version == 2)
500 outw(0x01, TCO_RLD);
501 else if (iTCO_wdt_private.iTCO_version == 1)
502 outb(0x01, TCO_RLD);
503
9e0ea345
WVS		 504 /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
505 val = inw(TCO1_CNT);
506 val &= 0xf7ff;
507 outw(val, TCO1_CNT);
508 val = inw(TCO1_CNT);
509 spin_unlock(&iTCO_wdt_private.io_lock);
510
511 if (val & 0x0800)
512 return -1;
513 return 0;
514}
515
516static int iTCO_wdt_stop(void)
517{
518 unsigned int val;
519
520 spin_lock(&iTCO_wdt_private.io_lock);
521
e033351d
WVS		 522 iTCO_vendor_pre_stop(iTCO_wdt_private.ACPIBASE);
523
9e0ea345
WVS		 524 /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
525 val = inw(TCO1_CNT);
526 val |= 0x0800;
527 outw(val, TCO1_CNT);
528 val = inw(TCO1_CNT);
529
530 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
531 iTCO_wdt_set_NO_REBOOT_bit();
532
533 spin_unlock(&iTCO_wdt_private.io_lock);
534
535 if ((val & 0x0800) == 0)
536 return -1;
537 return 0;
538}
539
540static int iTCO_wdt_keepalive(void)
541{
542 spin_lock(&iTCO_wdt_private.io_lock);
543
e033351d
WVS		 544 iTCO_vendor_pre_keepalive(iTCO_wdt_private.ACPIBASE, heartbeat);
545
9e0ea345 546 /* Reload the timer by writing to the TCO Timer Counter register */
0e6fa3fb 547 if (iTCO_wdt_private.iTCO_version == 2)
9e0ea345 548 outw(0x01, TCO_RLD);
7e6811da
PB		 549 else if (iTCO_wdt_private.iTCO_version == 1) {
550 /* Reset the timeout status bit so that the timer
551 * needs to count down twice again before rebooting */
552 outw(0x0008, TCO1_STS); /* write 1 to clear bit */
553
9e0ea345 554 outb(0x01, TCO_RLD);
7e6811da 555 }
9e0ea345
WVS		 556
557 spin_unlock(&iTCO_wdt_private.io_lock);
558 return 0;
559}
560
561static int iTCO_wdt_set_heartbeat(int t)
562{
563 unsigned int val16;
564 unsigned char val8;
565 unsigned int tmrval;
566
567 tmrval = seconds_to_ticks(t);
7e6811da
PB		 568
569 /* For TCO v1 the timer counts down twice before rebooting */
570 if (iTCO_wdt_private.iTCO_version == 1)
571 tmrval /= 2;
572
9e0ea345
WVS		 573 /* from the specs: */
574 /* "Values of 0h-3h are ignored and should not be attempted" */
575 if (tmrval < 0x04)
576 return -EINVAL;
577 if (((iTCO_wdt_private.iTCO_version == 2) && (tmrval > 0x3ff)) ||
578 ((iTCO_wdt_private.iTCO_version == 1) && (tmrval > 0x03f)))
579 return -EINVAL;
580
e033351d
WVS		 581 iTCO_vendor_pre_set_heartbeat(tmrval);
582
9e0ea345
WVS		 583 /* Write new heartbeat to watchdog */
584 if (iTCO_wdt_private.iTCO_version == 2) {
585 spin_lock(&iTCO_wdt_private.io_lock);
586 val16 = inw(TCOv2_TMR);
587 val16 &= 0xfc00;
588 val16 |= tmrval;
589 outw(val16, TCOv2_TMR);
590 val16 = inw(TCOv2_TMR);
591 spin_unlock(&iTCO_wdt_private.io_lock);
592
593 if ((val16 & 0x3ff) != tmrval)
594 return -EINVAL;
595 } else if (iTCO_wdt_private.iTCO_version == 1) {
596 spin_lock(&iTCO_wdt_private.io_lock);
597 val8 = inb(TCOv1_TMR);
598 val8 &= 0xc0;
599 val8 |= (tmrval & 0xff);
600 outb(val8, TCOv1_TMR);
601 val8 = inb(TCOv1_TMR);
602 spin_unlock(&iTCO_wdt_private.io_lock);
603
604 if ((val8 & 0x3f) != tmrval)
605 return -EINVAL;
606 }
607
608 heartbeat = t;
609 return 0;
610}
611
0e6fa3fb 612static int iTCO_wdt_get_timeleft(int *time_left)
9e0ea345
WVS		 613{
614 unsigned int val16;
615 unsigned char val8;
616
617 /* read the TCO Timer */
618 if (iTCO_wdt_private.iTCO_version == 2) {
619 spin_lock(&iTCO_wdt_private.io_lock);
620 val16 = inw(TCO_RLD);
621 val16 &= 0x3ff;
622 spin_unlock(&iTCO_wdt_private.io_lock);
623
624 *time_left = (val16 * 6) / 10;
625 } else if (iTCO_wdt_private.iTCO_version == 1) {
626 spin_lock(&iTCO_wdt_private.io_lock);
627 val8 = inb(TCO_RLD);
628 val8 &= 0x3f;
7e6811da
PB		 629 if (!(inw(TCO1_STS) & 0x0008))
630 val8 += (inb(TCOv1_TMR) & 0x3f);
9e0ea345
WVS		 631 spin_unlock(&iTCO_wdt_private.io_lock);
632
633 *time_left = (val8 * 6) / 10;
80060362
JG		 634 } else
635 return -EINVAL;
9e0ea345
WVS		 636 return 0;
637}
638
639/*
640 * /dev/watchdog handling
641 */
642
0e6fa3fb 643static int iTCO_wdt_open(struct inode *inode, struct file *file)
9e0ea345
WVS		 644{
645 /* /dev/watchdog can only be opened once */
646 if (test_and_set_bit(0, &is_active))
647 return -EBUSY;
648
649 /*
650 * Reload and activate timer
651 */
9e0ea345
WVS		 652 iTCO_wdt_start();
653 return nonseekable_open(inode, file);
654}
655
0e6fa3fb 656static int iTCO_wdt_release(struct inode *inode, struct file *file)
9e0ea345
WVS		 657{
658 /*
659 * Shut off the timer.
660 */
661 if (expect_release == 42) {
662 iTCO_wdt_stop();
663 } else {
0e6fa3fb
AC		 664 printk(KERN_CRIT PFX
665 "Unexpected close, not stopping watchdog!\n");
9e0ea345
WVS		 666 iTCO_wdt_keepalive();
667 }
668 clear_bit(0, &is_active);
669 expect_release = 0;
670 return 0;
671}
672
0e6fa3fb
AC		 673static ssize_t iTCO_wdt_write(struct file *file, const char __user *data,
674 size_t len, loff_t *ppos)
9e0ea345
WVS		 675{
676 /* See if we got the magic character 'V' and reload the timer */
677 if (len) {
678 if (!nowayout) {
679 size_t i;
680
0e6fa3fb
AC		 681 /* note: just in case someone wrote the magic
682 character five months ago... */
9e0ea345
WVS		 683 expect_release = 0;
684
0e6fa3fb
AC		 685 /* scan to see whether or not we got the
686 magic character */
9e0ea345
WVS		 687 for (i = 0; i != len; i++) {
688 char c;
7944d3a5 689 if (get_user(c, data + i))
9e0ea345
WVS		 690 return -EFAULT;
691 if (c == 'V')
692 expect_release = 42;
693 }
694 }
695
696 /* someone wrote to us, we should reload the timer */
697 iTCO_wdt_keepalive();
698 }
699 return len;
700}
701
0e6fa3fb
AC		 702static long iTCO_wdt_ioctl(struct file *file, unsigned int cmd,
703 unsigned long arg)
9e0ea345
WVS		 704{
705 int new_options, retval = -EINVAL;
706 int new_heartbeat;
9e0ea345
WVS		 707 void __user *argp = (void __user *)arg;
708 int __user *p = argp;
42747d71 709 static const struct watchdog_info ident = {
9e0ea345
WVS		 710 .options = WDIOF_SETTIMEOUT |
711 WDIOF_KEEPALIVEPING |
712 WDIOF_MAGICCLOSE,
713 .firmware_version = 0,
714 .identity = DRV_NAME,
715 };
716
717 switch (cmd) {
0e6fa3fb
AC		 718 case WDIOC_GETSUPPORT:
719 return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0;
720 case WDIOC_GETSTATUS:
721 case WDIOC_GETBOOTSTATUS:
722 return put_user(0, p);
9e0ea345 723
0e6fa3fb
AC		 724 case WDIOC_SETOPTIONS:
725 {
726 if (get_user(new_options, p))
727 return -EFAULT;
9e0ea345 728
0e6fa3fb
AC		 729 if (new_options & WDIOS_DISABLECARD) {
730 iTCO_wdt_stop();
731 retval = 0;
9e0ea345 732 }
0e6fa3fb 733 if (new_options & WDIOS_ENABLECARD) {
9e0ea345 734 iTCO_wdt_keepalive();
0e6fa3fb
AC		 735 iTCO_wdt_start();
736 retval = 0;
9e0ea345 737 }
0e6fa3fb
AC		 738 return retval;
739 }
0c06090c
WVS		 740 case WDIOC_KEEPALIVE:
741 iTCO_wdt_keepalive();
742 return 0;
743
0e6fa3fb
AC		 744 case WDIOC_SETTIMEOUT:
745 {
746 if (get_user(new_heartbeat, p))
747 return -EFAULT;
748 if (iTCO_wdt_set_heartbeat(new_heartbeat))
749 return -EINVAL;
750 iTCO_wdt_keepalive();
751 /* Fall */
752 }
753 case WDIOC_GETTIMEOUT:
754 return put_user(heartbeat, p);
755 case WDIOC_GETTIMELEFT:
756 {
757 int time_left;
758 if (iTCO_wdt_get_timeleft(&time_left))
759 return -EINVAL;
760 return put_user(time_left, p);
761 }
762 default:
763 return -ENOTTY;
9e0ea345
WVS		 764 }
765}
766
9e0ea345
WVS		 767/*
768 * Kernel Interfaces
769 */
770
2b8693c0 771static const struct file_operations iTCO_wdt_fops = {
0e6fa3fb
AC		 772 .owner = THIS_MODULE,
773 .llseek = no_llseek,
774 .write = iTCO_wdt_write,
775 .unlocked_ioctl = iTCO_wdt_ioctl,
776 .open = iTCO_wdt_open,
777 .release = iTCO_wdt_release,
9e0ea345
WVS		 778};
779
780static struct miscdevice iTCO_wdt_miscdev = {
781 .minor = WATCHDOG_MINOR,
782 .name = "watchdog",
783 .fops = &iTCO_wdt_fops,
784};
785
9e0ea345
WVS		 786/*
787 * Init & exit routines
788 */
789
0e6fa3fb
AC		 790static int __devinit iTCO_wdt_init(struct pci_dev *pdev,
791 const struct pci_device_id *ent, struct platform_device *dev)
9e0ea345
WVS		 792{
793 int ret;
794 u32 base_address;
795 unsigned long RCBA;
12d60e28 796 unsigned long val32;
9e0ea345
WVS		 797
798 /*
799 * Find the ACPI/PM base I/O address which is the base
800 * for the TCO registers (TCOBASE=ACPIBASE + 0x60)
801 * ACPIBASE is bits [15:7] from 0x40-0x43
802 */
803 pci_read_config_dword(pdev, 0x40, &base_address);
0d4804b3 804 base_address &= 0x0000ff80;
9e0ea345
WVS		 805 if (base_address == 0x00000000) {
806 /* Something's wrong here, ACPIBASE has to be set */
641912f4
PB		 807 printk(KERN_ERR PFX "failed to get TCOBASE address, "
808 "device disabled by hardware/BIOS\n");
9e0ea345
WVS		 809 return -ENODEV;
810 }
0e6fa3fb
AC		 811 iTCO_wdt_private.iTCO_version =
812 iTCO_chipset_info[ent->driver_data].iTCO_version;
9e0ea345
WVS		 813 iTCO_wdt_private.ACPIBASE = base_address;
814 iTCO_wdt_private.pdev = pdev;
815
0e6fa3fb
AC		 816 /* Get the Memory-Mapped GCS register, we need it for the
817 NO_REBOOT flag (TCO v2). To get access to it you have to
818 read RCBA from PCI Config space 0xf0 and use it as base.
819 GCS = RCBA + ICH6_GCS(0x3410). */
9e0ea345
WVS		 820 if (iTCO_wdt_private.iTCO_version == 2) {
821 pci_read_config_dword(pdev, 0xf0, &base_address);
de8cd9a3 822 if ((base_address & 1) == 0) {
641912f4
PB		 823 printk(KERN_ERR PFX "RCBA is disabled by hardware"
824 "/BIOS, device disabled\n");
de8cd9a3
DL		 825 ret = -ENODEV;
826 goto out;
827 }
9e0ea345 828 RCBA = base_address & 0xffffc000;
0e6fa3fb 829 iTCO_wdt_private.gcs = ioremap((RCBA + 0x3410), 4);
9e0ea345
WVS		 830 }
831
832 /* Check chipset's NO_REBOOT bit */
e033351d 833 if (iTCO_wdt_unset_NO_REBOOT_bit() && iTCO_vendor_check_noreboot_on()) {
ec26985b 834 printk(KERN_INFO PFX "unable to reset NO_REBOOT flag, "
641912f4 835 "device disabled by hardware/BIOS\n");
9e0ea345 836 ret = -ENODEV; /* Cannot reset NO_REBOOT bit */
de8cd9a3 837 goto out_unmap;
9e0ea345
WVS		 838 }
839
840 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
841 iTCO_wdt_set_NO_REBOOT_bit();
842
7cd5b08b 843 /* The TCO logic uses the TCO_EN bit in the SMI_EN register */
9e0ea345 844 if (!request_region(SMI_EN, 4, "iTCO_wdt")) {
0e6fa3fb 845 printk(KERN_ERR PFX
641912f4
PB		 846 "I/O address 0x%04lx already in use, "
847 "device disabled\n", SMI_EN);
9e0ea345 848 ret = -EIO;
de8cd9a3 849 goto out_unmap;
9e0ea345 850 }
0d098587 851 if (turn_SMI_watchdog_clear_off >= iTCO_wdt_private.iTCO_version) {
deb9197b
WVS		 852 /* Bit 13: TCO_EN -> 0 = Disables TCO logic generating an SMI# */
853 val32 = inl(SMI_EN);
854 val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
855 outl(val32, SMI_EN);
856 }
9e0ea345 857
0e6fa3fb
AC		 858 /* The TCO I/O registers reside in a 32-byte range pointed to
859 by the TCOBASE value */
860 if (!request_region(TCOBASE, 0x20, "iTCO_wdt")) {
641912f4
PB		 861 printk(KERN_ERR PFX "I/O address 0x%04lx already in use "
862 "device disabled\n", TCOBASE);
9e0ea345 863 ret = -EIO;
7cd5b08b 864 goto unreg_smi_en;
9e0ea345
WVS		 865 }
866
0e6fa3fb
AC		 867 printk(KERN_INFO PFX
868 "Found a %s TCO device (Version=%d, TCOBASE=0x%04lx)\n",
869 iTCO_chipset_info[ent->driver_data].name,
870 iTCO_chipset_info[ent->driver_data].iTCO_version,
871 TCOBASE);
9e0ea345
WVS		 872
873 /* Clear out the (probably old) status */
7e6811da
PB		 874 outw(0x0008, TCO1_STS); /* Clear the Time Out Status bit */
875 outw(0x0002, TCO2_STS); /* Clear SECOND_TO_STS bit */
876 outw(0x0004, TCO2_STS); /* Clear BOOT_STS bit */
9e0ea345
WVS		 877
878 /* Make sure the watchdog is not running */
879 iTCO_wdt_stop();
880
0e6fa3fb
AC		 881 /* Check that the heartbeat value is within it's range;
882 if not reset to the default */
9e0ea345
WVS		 883 if (iTCO_wdt_set_heartbeat(heartbeat)) {
884 iTCO_wdt_set_heartbeat(WATCHDOG_HEARTBEAT);
143a2e54 885 printk(KERN_INFO PFX
7e6811da 886 "timeout value out of range, using %d\n", heartbeat);
9e0ea345
WVS		 887 }
888
9e0ea345
WVS		 889 ret = misc_register(&iTCO_wdt_miscdev);
890 if (ret != 0) {
0e6fa3fb
AC		 891 printk(KERN_ERR PFX
892 "cannot register miscdev on minor=%d (err=%d)\n",
893 WATCHDOG_MINOR, ret);
1bef84be 894 goto unreg_region;
9e0ea345
WVS		 895 }
896
0e6fa3fb
AC		 897 printk(KERN_INFO PFX "initialized. heartbeat=%d sec (nowayout=%d)\n",
898 heartbeat, nowayout);
9e0ea345
WVS		 899
900 return 0;
901
9e0ea345 902unreg_region:
0e6fa3fb 903 release_region(TCOBASE, 0x20);
7cd5b08b
WVS		 904unreg_smi_en:
905 release_region(SMI_EN, 4);
de8cd9a3 906out_unmap:
9e0ea345
WVS		 907 if (iTCO_wdt_private.iTCO_version == 2)
908 iounmap(iTCO_wdt_private.gcs);
de8cd9a3 909out:
1bef84be 910 iTCO_wdt_private.ACPIBASE = 0;
9e0ea345
WVS		 911 return ret;
912}
913
08113e39 914static void __devexit iTCO_wdt_cleanup(void)
9e0ea345
WVS		 915{
916 /* Stop the timer before we leave */
917 if (!nowayout)
918 iTCO_wdt_stop();
919
920 /* Deregister */
921 misc_deregister(&iTCO_wdt_miscdev);
9e0ea345 922 release_region(TCOBASE, 0x20);
7cd5b08b 923 release_region(SMI_EN, 4);
9e0ea345
WVS		 924 if (iTCO_wdt_private.iTCO_version == 2)
925 iounmap(iTCO_wdt_private.gcs);
4802c653 926 pci_dev_put(iTCO_wdt_private.pdev);
1bef84be 927 iTCO_wdt_private.ACPIBASE = 0;
9e0ea345
WVS		 928}
929
08113e39 930static int __devinit iTCO_wdt_probe(struct platform_device *dev)
9e0ea345 931{
ec26985b 932 int ret = -ENODEV;
9e0ea345
WVS		 933 int found = 0;
934 struct pci_dev *pdev = NULL;
935 const struct pci_device_id *ent;
936
937 spin_lock_init(&iTCO_wdt_private.io_lock);
938
939 for_each_pci_dev(pdev) {
940 ent = pci_match_id(iTCO_wdt_pci_tbl, pdev);
941 if (ent) {
ec26985b
NC		 942 found++;
943 ret = iTCO_wdt_init(pdev, ent, dev);
944 if (!ret)
9e0ea345 945 break;
9e0ea345
WVS		 946 }
947 }
948
ec26985b 949 if (!found)
641912f4 950 printk(KERN_INFO PFX "No device detected.\n");
9e0ea345 951
ec26985b 952 return ret;
9e0ea345
WVS		 953}
954
08113e39 955static int __devexit iTCO_wdt_remove(struct platform_device *dev)
9e0ea345
WVS		 956{
957 if (iTCO_wdt_private.ACPIBASE)
958 iTCO_wdt_cleanup();
959
3836cc0f
WVS		 960 return 0;
961}
962
963static void iTCO_wdt_shutdown(struct platform_device *dev)
964{
965 iTCO_wdt_stop();
966}
967
3836cc0f
WVS		 968static struct platform_driver iTCO_wdt_driver = {
969 .probe = iTCO_wdt_probe,
08113e39 970 .remove = __devexit_p(iTCO_wdt_remove),
3836cc0f 971 .shutdown = iTCO_wdt_shutdown,
3836cc0f
WVS		 972 .driver = {
973 .owner = THIS_MODULE,
974 .name = DRV_NAME,
975 },
976};
977
978static int __init iTCO_wdt_init_module(void)
979{
980 int err;
981
7cd5b08b
WVS		 982 printk(KERN_INFO PFX "Intel TCO WatchDog Timer Driver v%s\n",
983 DRV_VERSION);
3836cc0f
WVS		 984
985 err = platform_driver_register(&iTCO_wdt_driver);
986 if (err)
987 return err;
988
0e6fa3fb
AC		 989 iTCO_wdt_platform_device = platform_device_register_simple(DRV_NAME,
990 -1, NULL, 0);
3836cc0f
WVS		 991 if (IS_ERR(iTCO_wdt_platform_device)) {
992 err = PTR_ERR(iTCO_wdt_platform_device);
993 goto unreg_platform_driver;
994 }
995
996 return 0;
997
998unreg_platform_driver:
999 platform_driver_unregister(&iTCO_wdt_driver);
1000 return err;
1001}
1002
1003static void __exit iTCO_wdt_cleanup_module(void)
1004{
1005 platform_device_unregister(iTCO_wdt_platform_device);
1006 platform_driver_unregister(&iTCO_wdt_driver);
9e0ea345
WVS		 1007 printk(KERN_INFO PFX "Watchdog Module Unloaded.\n");
1008}
1009
1010module_init(iTCO_wdt_init_module);
1011module_exit(iTCO_wdt_cleanup_module);
1012
1013MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>");
1014MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
3836cc0f 1015MODULE_VERSION(DRV_VERSION);
9e0ea345
WVS		 1016MODULE_LICENSE("GPL");
1017MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
Linux kernel - Deliverables
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