[deliverable/linux.git] / drivers / watchdog / imx2_wdt.c

/*
 * Watchdog driver for IMX2 and later processors
 *
 *  Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <w.sang@pengutronix.de>
 *  Copyright (C) 2014 Freescale Semiconductor, Inc.
 *
 * some parts adapted by similar drivers from Darius Augulis and Vladimir
 * Zapolskiy, additional improvements by Wim Van Sebroeck.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * NOTE: MX1 has a slightly different Watchdog than MX2 and later:
 *
 *			MX1:		MX2+:
 *			----		-----
 * Registers:		32-bit		16-bit
 * Stopable timer:	Yes		No
 * Need to enable clk:	No		Yes
 * Halt on suspend:	Manual		Can be automatic
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/jiffies.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/notifier.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/reboot.h>
#include <linux/regmap.h>
#include <linux/timer.h>
#include <linux/watchdog.h>

#define DRIVER_NAME "imx2-wdt"

#define IMX2_WDT_WCR		0x00		/* Control Register */
#define IMX2_WDT_WCR_WT		(0xFF << 8)	/* -> Watchdog Timeout Field */
#define IMX2_WDT_WCR_WRE	(1 << 3)	/* -> WDOG Reset Enable */
#define IMX2_WDT_WCR_WDE	(1 << 2)	/* -> Watchdog Enable */
#define IMX2_WDT_WCR_WDZST	(1 << 0)	/* -> Watchdog timer Suspend */

#define IMX2_WDT_WSR		0x02		/* Service Register */
#define IMX2_WDT_SEQ1		0x5555		/* -> service sequence 1 */
#define IMX2_WDT_SEQ2		0xAAAA		/* -> service sequence 2 */

#define IMX2_WDT_WRSR		0x04		/* Reset Status Register */
#define IMX2_WDT_WRSR_TOUT	(1 << 1)	/* -> Reset due to Timeout */

#define IMX2_WDT_MAX_TIME	128
#define IMX2_WDT_DEFAULT_TIME	60		/* in seconds */

#define WDOG_SEC_TO_COUNT(s)	((s * 2 - 1) << 8)

struct imx2_wdt_device {
	struct clk *clk;
	struct regmap *regmap;
	struct timer_list timer;	/* Pings the watchdog when closed */
	struct watchdog_device wdog;
	struct notifier_block restart_handler;
};

static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
				__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");


static unsigned timeout = IMX2_WDT_DEFAULT_TIME;
module_param(timeout, uint, 0);
MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
				__MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")");

static const struct watchdog_info imx2_wdt_info = {
	.identity = "imx2+ watchdog",
	.options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE,
};

static int imx2_restart_handler(struct notifier_block *this, unsigned long mode,
				void *cmd)
{
	unsigned int wcr_enable = IMX2_WDT_WCR_WDE;
	struct imx2_wdt_device *wdev = container_of(this,
						    struct imx2_wdt_device,
						    restart_handler);
	/* Assert SRS signal */
	regmap_write(wdev->regmap, 0, wcr_enable);
	/*
	 * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
	 * written twice), we add another two writes to ensure there must be at
	 * least two writes happen in the same one 32kHz clock period.  We save
	 * the target check here, since the writes shouldn't be a huge burden
	 * for other platforms.
	 */
	regmap_write(wdev->regmap, 0, wcr_enable);
	regmap_write(wdev->regmap, 0, wcr_enable);

	/* wait for reset to assert... */
	mdelay(500);

	return NOTIFY_DONE;
}

static inline void imx2_wdt_setup(struct watchdog_device *wdog)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	u32 val;

	regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);

	/* Suspend timer in low power mode, write once-only */
	val |= IMX2_WDT_WCR_WDZST;
	/* Strip the old watchdog Time-Out value */
	val &= ~IMX2_WDT_WCR_WT;
	/* Generate reset if WDOG times out */
	val &= ~IMX2_WDT_WCR_WRE;
	/* Keep Watchdog Disabled */
	val &= ~IMX2_WDT_WCR_WDE;
	/* Set the watchdog's Time-Out value */
	val |= WDOG_SEC_TO_COUNT(wdog->timeout);

	regmap_write(wdev->regmap, IMX2_WDT_WCR, val);

	/* enable the watchdog */
	val |= IMX2_WDT_WCR_WDE;
	regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
}

static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev)
{
	u32 val;

	regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);

	return val & IMX2_WDT_WCR_WDE;
}

static int imx2_wdt_ping(struct watchdog_device *wdog)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1);
	regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2);
	return 0;
}

static void imx2_wdt_timer_ping(unsigned long arg)
{
	struct watchdog_device *wdog = (struct watchdog_device *)arg;
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	/* ping it every wdog->timeout / 2 seconds to prevent reboot */
	imx2_wdt_ping(wdog);
	mod_timer(&wdev->timer, jiffies + wdog->timeout * HZ / 2);
}

static int imx2_wdt_set_timeout(struct watchdog_device *wdog,
				unsigned int new_timeout)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT,
			   WDOG_SEC_TO_COUNT(new_timeout));
	return 0;
}

static int imx2_wdt_start(struct watchdog_device *wdog)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	if (imx2_wdt_is_running(wdev)) {
		/* delete the timer that pings the watchdog after close */
		del_timer_sync(&wdev->timer);
		imx2_wdt_set_timeout(wdog, wdog->timeout);
	} else
		imx2_wdt_setup(wdog);

	return imx2_wdt_ping(wdog);
}

static int imx2_wdt_stop(struct watchdog_device *wdog)
{
	/*
	 * We don't need a clk_disable, it cannot be disabled once started.
	 * We use a timer to ping the watchdog while /dev/watchdog is closed
	 */
	imx2_wdt_timer_ping((unsigned long)wdog);
	return 0;
}

static inline void imx2_wdt_ping_if_active(struct watchdog_device *wdog)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	if (imx2_wdt_is_running(wdev)) {
		imx2_wdt_set_timeout(wdog, wdog->timeout);
		imx2_wdt_timer_ping((unsigned long)wdog);
	}
}

static struct watchdog_ops imx2_wdt_ops = {
	.owner = THIS_MODULE,
	.start = imx2_wdt_start,
	.stop = imx2_wdt_stop,
	.ping = imx2_wdt_ping,
	.set_timeout = imx2_wdt_set_timeout,
};

static struct regmap_config imx2_wdt_regmap_config = {
	.reg_bits = 16,
	.reg_stride = 2,
	.val_bits = 16,
	.max_register = 0x8,
};

static int __init imx2_wdt_probe(struct platform_device *pdev)
{
	struct imx2_wdt_device *wdev;
	struct watchdog_device *wdog;
	struct resource *res;
	void __iomem *base;
	int ret;
	u32 val;

	wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
	if (!wdev)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(base))
		return PTR_ERR(base);

	wdev->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
						 &imx2_wdt_regmap_config);
	if (IS_ERR(wdev->regmap)) {
		dev_err(&pdev->dev, "regmap init failed\n");
		return PTR_ERR(wdev->regmap);
	}

	wdev->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(wdev->clk)) {
		dev_err(&pdev->dev, "can't get Watchdog clock\n");
		return PTR_ERR(wdev->clk);
	}

	wdog			= &wdev->wdog;
	wdog->info		= &imx2_wdt_info;
	wdog->ops		= &imx2_wdt_ops;
	wdog->min_timeout	= 1;
	wdog->max_timeout	= IMX2_WDT_MAX_TIME;

	clk_prepare_enable(wdev->clk);

	regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val);
	wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0;

	wdog->timeout = clamp_t(unsigned, timeout, 1, IMX2_WDT_MAX_TIME);
	if (wdog->timeout != timeout)
		dev_warn(&pdev->dev, "Initial timeout out of range! Clamped from %u to %u\n",
			 timeout, wdog->timeout);

	platform_set_drvdata(pdev, wdog);
	watchdog_set_drvdata(wdog, wdev);
	watchdog_set_nowayout(wdog, nowayout);
	watchdog_init_timeout(wdog, timeout, &pdev->dev);

	setup_timer(&wdev->timer, imx2_wdt_timer_ping, (unsigned long)wdog);

	imx2_wdt_ping_if_active(wdog);

	ret = watchdog_register_device(wdog);
	if (ret) {
		dev_err(&pdev->dev, "cannot register watchdog device\n");
		return ret;
	}

	wdev->restart_handler.notifier_call = imx2_restart_handler;
	wdev->restart_handler.priority = 128;
	ret = register_restart_handler(&wdev->restart_handler);
	if (ret)
		dev_err(&pdev->dev, "cannot register restart handler\n");

	dev_info(&pdev->dev, "timeout %d sec (nowayout=%d)\n",
		 wdog->timeout, nowayout);

	return 0;
}

static int __exit imx2_wdt_remove(struct platform_device *pdev)
{
	struct watchdog_device *wdog = platform_get_drvdata(pdev);
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	unregister_restart_handler(&wdev->restart_handler);

	watchdog_unregister_device(wdog);

	if (imx2_wdt_is_running(wdev)) {
		del_timer_sync(&wdev->timer);
		imx2_wdt_ping(wdog);
		dev_crit(&pdev->dev, "Device removed: Expect reboot!\n");
	}
	return 0;
}

static void imx2_wdt_shutdown(struct platform_device *pdev)
{
	struct watchdog_device *wdog = platform_get_drvdata(pdev);
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	if (imx2_wdt_is_running(wdev)) {
		/*
		 * We are running, we need to delete the timer but will
		 * give max timeout before reboot will take place
		 */
		del_timer_sync(&wdev->timer);
		imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
		imx2_wdt_ping(wdog);
		dev_crit(&pdev->dev, "Device shutdown: Expect reboot!\n");
	}
}

#ifdef CONFIG_PM_SLEEP
/* Disable watchdog if it is active or non-active but still running */
static int imx2_wdt_suspend(struct device *dev)
{
	struct watchdog_device *wdog = dev_get_drvdata(dev);
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	/* The watchdog IP block is running */
	if (imx2_wdt_is_running(wdev)) {
		imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
		imx2_wdt_ping(wdog);

		/* The watchdog is not active */
		if (!watchdog_active(wdog))
			del_timer_sync(&wdev->timer);
	}

	clk_disable_unprepare(wdev->clk);

	return 0;
}

/* Enable watchdog and configure it if necessary */
static int imx2_wdt_resume(struct device *dev)
{
	struct watchdog_device *wdog = dev_get_drvdata(dev);
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	clk_prepare_enable(wdev->clk);

	if (watchdog_active(wdog) && !imx2_wdt_is_running(wdev)) {
		/*
		 * If the watchdog is still active and resumes
		 * from deep sleep state, need to restart the
		 * watchdog again.
		 */
		imx2_wdt_setup(wdog);
		imx2_wdt_set_timeout(wdog, wdog->timeout);
		imx2_wdt_ping(wdog);
	} else if (imx2_wdt_is_running(wdev)) {
		/* Resuming from non-deep sleep state. */
		imx2_wdt_set_timeout(wdog, wdog->timeout);
		imx2_wdt_ping(wdog);
		/*
		 * But the watchdog is not active, then start
		 * the timer again.
		 */
		if (!watchdog_active(wdog))
			mod_timer(&wdev->timer,
				  jiffies + wdog->timeout * HZ / 2);
	}

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend,
			 imx2_wdt_resume);

static const struct of_device_id imx2_wdt_dt_ids[] = {
	{ .compatible = "fsl,imx21-wdt", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids);

static struct platform_driver imx2_wdt_driver = {
	.remove		= __exit_p(imx2_wdt_remove),
	.shutdown	= imx2_wdt_shutdown,
	.driver		= {
		.name	= DRIVER_NAME,
		.pm     = &imx2_wdt_pm_ops,
		.of_match_table = imx2_wdt_dt_ids,
	},
};

module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe);

MODULE_AUTHOR("Wolfram Sang");
MODULE_DESCRIPTION("Watchdog driver for IMX2 and later");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRIVER_NAME);
Commit	Line	Data
bb2fd8a8 WS	1	/*
	2	* Watchdog driver for IMX2 and later processors
	3	*
	4	* Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <w.sang@pengutronix.de>
1a9c5efa	5	* Copyright (C) 2014 Freescale Semiconductor, Inc.
bb2fd8a8 WS	6	*
	7	* some parts adapted by similar drivers from Darius Augulis and Vladimir
	8	* Zapolskiy, additional improvements by Wim Van Sebroeck.
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License version 2 as published by
	12	* the Free Software Foundation.
	13	*
	14	* NOTE: MX1 has a slightly different Watchdog than MX2 and later:
	15	*
	16	* MX1: MX2+:
	17	* ---- -----
	18	* Registers: 32-bit 16-bit
	19	* Stopable timer: Yes No
	20	* Need to enable clk: No Yes
	21	* Halt on suspend: Manual Can be automatic
	22	*/
	23
30cb042a	24	#include <linux/clk.h>
334a9d81	25	#include <linux/delay.h>
bb2fd8a8	26	#include <linux/init.h>
30cb042a XL	27	#include <linux/io.h>
30cb042a XL	28	#include <linux/jiffies.h>
bb2fd8a8	29	#include <linux/kernel.h>
bb2fd8a8 WS	30	#include <linux/module.h>
bb2fd8a8 WS	31	#include <linux/moduleparam.h>
334a9d81	32	#include <linux/notifier.h>
f728f4bf	33	#include <linux/of_address.h>
bb2fd8a8	34	#include <linux/platform_device.h>
334a9d81	35	#include <linux/reboot.h>
a7977003	36	#include <linux/regmap.h>
bb2fd8a8	37	#include <linux/timer.h>
30cb042a	38	#include <linux/watchdog.h>
bb2fd8a8 WS	39
	40	#define DRIVER_NAME "imx2-wdt"
	41
	42	#define IMX2_WDT_WCR 0x00 /* Control Register */
	43	#define IMX2_WDT_WCR_WT (0xFF << 8) /* -> Watchdog Timeout Field */
	44	#define IMX2_WDT_WCR_WRE (1 << 3) /* -> WDOG Reset Enable */
	45	#define IMX2_WDT_WCR_WDE (1 << 2) /* -> Watchdog Enable */
1a9c5efa	46	#define IMX2_WDT_WCR_WDZST (1 << 0) /* -> Watchdog timer Suspend */
bb2fd8a8 WS	47
	48	#define IMX2_WDT_WSR 0x02 /* Service Register */
	49	#define IMX2_WDT_SEQ1 0x5555 /* -> service sequence 1 */
	50	#define IMX2_WDT_SEQ2 0xAAAA /* -> service sequence 2 */
	51
474ef121 OS	52	#define IMX2_WDT_WRSR 0x04 /* Reset Status Register */
	53	#define IMX2_WDT_WRSR_TOUT (1 << 1) /* -> Reset due to Timeout */
	54
bb2fd8a8 WS	55	#define IMX2_WDT_MAX_TIME 128
	56	#define IMX2_WDT_DEFAULT_TIME 60 /* in seconds */
	57
	58	#define WDOG_SEC_TO_COUNT(s) ((s * 2 - 1) << 8)
	59
faad5de0	60	struct imx2_wdt_device {
bb2fd8a8	61	struct clk *clk;
a7977003	62	struct regmap *regmap;
bb2fd8a8	63	struct timer_list timer; /* Pings the watchdog when closed */
faad5de0	64	struct watchdog_device wdog;
334a9d81	65	struct notifier_block restart_handler;
faad5de0	66	};
bb2fd8a8	67
86a1e189 WVS	68	static bool nowayout = WATCHDOG_NOWAYOUT;
86a1e189 WVS	69	module_param(nowayout, bool, 0);
bb2fd8a8 WS	70	MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
	71	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
	72
	73
	74	static unsigned timeout = IMX2_WDT_DEFAULT_TIME;
	75	module_param(timeout, uint, 0);
	76	MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
	77	__MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")");
	78
	79	static const struct watchdog_info imx2_wdt_info = {
	80	.identity = "imx2+ watchdog",
	81	.options = WDIOF_KEEPALIVEPING \| WDIOF_SETTIMEOUT \| WDIOF_MAGICCLOSE,
	82	};
	83
334a9d81 JL	84	static int imx2_restart_handler(struct notifier_block *this, unsigned long mode,
	85	void *cmd)
	86	{
	87	unsigned int wcr_enable = IMX2_WDT_WCR_WDE;
	88	struct imx2_wdt_device *wdev = container_of(this,
	89	struct imx2_wdt_device,
	90	restart_handler);
	91	/* Assert SRS signal */
	92	regmap_write(wdev->regmap, 0, wcr_enable);
	93	/*
	94	* Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
	95	* written twice), we add another two writes to ensure there must be at
	96	* least two writes happen in the same one 32kHz clock period. We save
	97	* the target check here, since the writes shouldn't be a huge burden
	98	* for other platforms.
	99	*/
	100	regmap_write(wdev->regmap, 0, wcr_enable);
	101	regmap_write(wdev->regmap, 0, wcr_enable);
	102
	103	/* wait for reset to assert... */
	104	mdelay(500);
	105
	106	return NOTIFY_DONE;
	107	}
	108
faad5de0	109	static inline void imx2_wdt_setup(struct watchdog_device *wdog)
bb2fd8a8	110	{
faad5de0	111	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
a7977003 XL	112	u32 val;
a7977003 XL	113
faad5de0	114	regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
bb2fd8a8	115
1a9c5efa AH	116	/* Suspend timer in low power mode, write once-only */
1a9c5efa AH	117	val \|= IMX2_WDT_WCR_WDZST;
bb2fd8a8 WS	118	/* Strip the old watchdog Time-Out value */
	119	val &= ~IMX2_WDT_WCR_WT;
	120	/* Generate reset if WDOG times out */
	121	val &= ~IMX2_WDT_WCR_WRE;
	122	/* Keep Watchdog Disabled */
	123	val &= ~IMX2_WDT_WCR_WDE;
	124	/* Set the watchdog's Time-Out value */
faad5de0	125	val \|= WDOG_SEC_TO_COUNT(wdog->timeout);
bb2fd8a8	126
faad5de0	127	regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
bb2fd8a8 WS	128
	129	/* enable the watchdog */
	130	val \|= IMX2_WDT_WCR_WDE;
faad5de0	131	regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
bb2fd8a8 WS	132	}
bb2fd8a8 WS	133
faad5de0	134	static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev)
bb2fd8a8	135	{
faad5de0	136	u32 val;
bb2fd8a8	137
faad5de0 AG	138	regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
	139
	140	return val & IMX2_WDT_WCR_WDE;
bb2fd8a8 WS	141	}
bb2fd8a8 WS	142
faad5de0	143	static int imx2_wdt_ping(struct watchdog_device *wdog)
bb2fd8a8	144	{
faad5de0	145	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
bb2fd8a8	146
faad5de0 AG	147	regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1);
	148	regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2);
	149	return 0;
bb2fd8a8 WS	150	}
bb2fd8a8 WS	151
faad5de0	152	static void imx2_wdt_timer_ping(unsigned long arg)
bb2fd8a8	153	{
faad5de0 AG	154	struct watchdog_device wdog = (struct watchdog_device )arg;
	155	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	156
	157	/* ping it every wdog->timeout / 2 seconds to prevent reboot */
	158	imx2_wdt_ping(wdog);
	159	mod_timer(&wdev->timer, jiffies + wdog->timeout * HZ / 2);
bb2fd8a8 WS	160	}
bb2fd8a8 WS	161
faad5de0 AG	162	static int imx2_wdt_set_timeout(struct watchdog_device *wdog,
faad5de0 AG	163	unsigned int new_timeout)
bb2fd8a8	164	{
faad5de0 AG	165	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	166
	167	regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT,
a7977003	168	WDOG_SEC_TO_COUNT(new_timeout));
faad5de0	169	return 0;
bb2fd8a8 WS	170	}
bb2fd8a8 WS	171
faad5de0	172	static int imx2_wdt_start(struct watchdog_device *wdog)
bb2fd8a8	173	{
faad5de0	174	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
bb2fd8a8	175
faad5de0 AG	176	if (imx2_wdt_is_running(wdev)) {
	177	/* delete the timer that pings the watchdog after close */
	178	del_timer_sync(&wdev->timer);
	179	imx2_wdt_set_timeout(wdog, wdog->timeout);
	180	} else
	181	imx2_wdt_setup(wdog);
	182
	183	return imx2_wdt_ping(wdog);
bb2fd8a8 WS	184	}
bb2fd8a8 WS	185
faad5de0	186	static int imx2_wdt_stop(struct watchdog_device *wdog)
bb2fd8a8	187	{
faad5de0 AG	188	/*
	189	* We don't need a clk_disable, it cannot be disabled once started.
	190	* We use a timer to ping the watchdog while /dev/watchdog is closed
	191	*/
	192	imx2_wdt_timer_ping((unsigned long)wdog);
bb2fd8a8 WS	193	return 0;
	194	}
	195
faad5de0	196	static inline void imx2_wdt_ping_if_active(struct watchdog_device *wdog)
bb2fd8a8	197	{
faad5de0	198	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
bb2fd8a8	199
faad5de0 AG	200	if (imx2_wdt_is_running(wdev)) {
	201	imx2_wdt_set_timeout(wdog, wdog->timeout);
	202	imx2_wdt_timer_ping((unsigned long)wdog);
bb2fd8a8 WS	203	}
	204	}
	205
faad5de0	206	static struct watchdog_ops imx2_wdt_ops = {
bb2fd8a8	207	.owner = THIS_MODULE,
faad5de0 AG	208	.start = imx2_wdt_start,
	209	.stop = imx2_wdt_stop,
	210	.ping = imx2_wdt_ping,
	211	.set_timeout = imx2_wdt_set_timeout,
bb2fd8a8 WS	212	};
bb2fd8a8 WS	213
a7977003 XL	214	static struct regmap_config imx2_wdt_regmap_config = {
	215	.reg_bits = 16,
	216	.reg_stride = 2,
	217	.val_bits = 16,
	218	.max_register = 0x8,
	219	};
	220
bb2fd8a8 WS	221	static int __init imx2_wdt_probe(struct platform_device *pdev)
bb2fd8a8 WS	222	{
faad5de0 AG	223	struct imx2_wdt_device *wdev;
faad5de0 AG	224	struct watchdog_device *wdog;
bb2fd8a8	225	struct resource *res;
a7977003 XL	226	void __iomem *base;
a7977003 XL	227	int ret;
faad5de0 AG	228	u32 val;
	229
	230	wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
	231	if (!wdev)
	232	return -ENOMEM;
bb2fd8a8 WS	233
bb2fd8a8 WS	234	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
a7977003 XL	235	base = devm_ioremap_resource(&pdev->dev, res);
	236	if (IS_ERR(base))
	237	return PTR_ERR(base);
	238
faad5de0 AG	239	wdev->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
	240	&imx2_wdt_regmap_config);
	241	if (IS_ERR(wdev->regmap)) {
a7977003	242	dev_err(&pdev->dev, "regmap init failed\n");
faad5de0	243	return PTR_ERR(wdev->regmap);
a7977003	244	}
bb2fd8a8	245
faad5de0 AG	246	wdev->clk = devm_clk_get(&pdev->dev, NULL);
faad5de0 AG	247	if (IS_ERR(wdev->clk)) {
bb2fd8a8	248	dev_err(&pdev->dev, "can't get Watchdog clock\n");
faad5de0	249	return PTR_ERR(wdev->clk);
bb2fd8a8 WS	250	}
bb2fd8a8 WS	251
faad5de0 AG	252	wdog = &wdev->wdog;
	253	wdog->info = &imx2_wdt_info;
	254	wdog->ops = &imx2_wdt_ops;
	255	wdog->min_timeout = 1;
	256	wdog->max_timeout = IMX2_WDT_MAX_TIME;
bb2fd8a8	257
faad5de0	258	clk_prepare_enable(wdev->clk);
bb2fd8a8	259
faad5de0 AG	260	regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val);
faad5de0 AG	261	wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0;
bb2fd8a8	262
faad5de0 AG	263	wdog->timeout = clamp_t(unsigned, timeout, 1, IMX2_WDT_MAX_TIME);
	264	if (wdog->timeout != timeout)
	265	dev_warn(&pdev->dev, "Initial timeout out of range! Clamped from %u to %u\n",
	266	timeout, wdog->timeout);
	267
	268	platform_set_drvdata(pdev, wdog);
	269	watchdog_set_drvdata(wdog, wdev);
	270	watchdog_set_nowayout(wdog, nowayout);
	271	watchdog_init_timeout(wdog, timeout, &pdev->dev);
	272
	273	setup_timer(&wdev->timer, imx2_wdt_timer_ping, (unsigned long)wdog);
bb2fd8a8	274
faad5de0 AG	275	imx2_wdt_ping_if_active(wdog);
	276
	277	ret = watchdog_register_device(wdog);
	278	if (ret) {
	279	dev_err(&pdev->dev, "cannot register watchdog device\n");
	280	return ret;
	281	}
	282
334a9d81 JL	283	wdev->restart_handler.notifier_call = imx2_restart_handler;
	284	wdev->restart_handler.priority = 128;
	285	ret = register_restart_handler(&wdev->restart_handler);
	286	if (ret)
	287	dev_err(&pdev->dev, "cannot register restart handler\n");
	288
faad5de0 AG	289	dev_info(&pdev->dev, "timeout %d sec (nowayout=%d)\n",
	290	wdog->timeout, nowayout);
	291
	292	return 0;
bb2fd8a8 WS	293	}
	294
	295	static int __exit imx2_wdt_remove(struct platform_device *pdev)
	296	{
faad5de0 AG	297	struct watchdog_device *wdog = platform_get_drvdata(pdev);
faad5de0 AG	298	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
bb2fd8a8	299
334a9d81 JL	300	unregister_restart_handler(&wdev->restart_handler);
334a9d81 JL	301
faad5de0	302	watchdog_unregister_device(wdog);
bb2fd8a8	303
faad5de0 AG	304	if (imx2_wdt_is_running(wdev)) {
	305	del_timer_sync(&wdev->timer);
	306	imx2_wdt_ping(wdog);
	307	dev_crit(&pdev->dev, "Device removed: Expect reboot!\n");
bdf49574	308	}
bb2fd8a8 WS	309	return 0;
	310	}
	311
	312	static void imx2_wdt_shutdown(struct platform_device *pdev)
	313	{
faad5de0 AG	314	struct watchdog_device *wdog = platform_get_drvdata(pdev);
	315	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	316
	317	if (imx2_wdt_is_running(wdev)) {
	318	/*
	319	* We are running, we need to delete the timer but will
	320	* give max timeout before reboot will take place
	321	*/
	322	del_timer_sync(&wdev->timer);
	323	imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
	324	imx2_wdt_ping(wdog);
	325	dev_crit(&pdev->dev, "Device shutdown: Expect reboot!\n");
bb2fd8a8 WS	326	}
	327	}
	328
aefbaf3a	329	#ifdef CONFIG_PM_SLEEP
bbd59009	330	/* Disable watchdog if it is active or non-active but still running */
aefbaf3a XL	331	static int imx2_wdt_suspend(struct device *dev)
	332	{
	333	struct watchdog_device *wdog = dev_get_drvdata(dev);
	334	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	335
bbd59009 XL	336	/* The watchdog IP block is running */
	337	if (imx2_wdt_is_running(wdev)) {
	338	imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
	339	imx2_wdt_ping(wdog);
aefbaf3a	340
bbd59009 XL	341	/* The watchdog is not active */
	342	if (!watchdog_active(wdog))
	343	del_timer_sync(&wdev->timer);
	344	}
aefbaf3a XL	345
	346	clk_disable_unprepare(wdev->clk);
	347
	348	return 0;
	349	}
	350
	351	/* Enable watchdog and configure it if necessary */
	352	static int imx2_wdt_resume(struct device *dev)
	353	{
	354	struct watchdog_device *wdog = dev_get_drvdata(dev);
	355	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	356
	357	clk_prepare_enable(wdev->clk);
	358
	359	if (watchdog_active(wdog) && !imx2_wdt_is_running(wdev)) {
bbd59009 XL	360	/*
	361	* If the watchdog is still active and resumes
	362	* from deep sleep state, need to restart the
	363	* watchdog again.
aefbaf3a XL	364	*/
	365	imx2_wdt_setup(wdog);
	366	imx2_wdt_set_timeout(wdog, wdog->timeout);
	367	imx2_wdt_ping(wdog);
	368	} else if (imx2_wdt_is_running(wdev)) {
bbd59009 XL	369	/* Resuming from non-deep sleep state. */
bbd59009 XL	370	imx2_wdt_set_timeout(wdog, wdog->timeout);
aefbaf3a	371	imx2_wdt_ping(wdog);
bbd59009 XL	372	/*
	373	* But the watchdog is not active, then start
	374	* the timer again.
	375	*/
	376	if (!watchdog_active(wdog))
	377	mod_timer(&wdev->timer,
	378	jiffies + wdog->timeout * HZ / 2);
aefbaf3a XL	379	}
	380
	381	return 0;
	382	}
	383	#endif
	384
	385	static SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend,
	386	imx2_wdt_resume);
	387
f5a427ee SG	388	static const struct of_device_id imx2_wdt_dt_ids[] = {
	389	{ .compatible = "fsl,imx21-wdt", },
	390	{ /* sentinel */ }
	391	};
813296a1	392	MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids);
f5a427ee	393
bb2fd8a8	394	static struct platform_driver imx2_wdt_driver = {
bb2fd8a8 WS	395	.remove = __exit_p(imx2_wdt_remove),
	396	.shutdown = imx2_wdt_shutdown,
	397	.driver = {
	398	.name = DRIVER_NAME,
aefbaf3a	399	.pm = &imx2_wdt_pm_ops,
f5a427ee	400	.of_match_table = imx2_wdt_dt_ids,
bb2fd8a8 WS	401	},
	402	};
	403
1cb9204c	404	module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe);
bb2fd8a8 WS	405
	406	MODULE_AUTHOR("Wolfram Sang");
	407	MODULE_DESCRIPTION("Watchdog driver for IMX2 and later");
	408	MODULE_LICENSE("GPL v2");
bb2fd8a8	409	MODULE_ALIAS("platform:" DRIVER_NAME);