Commit | Line | Data |
---|---|---|
b9d36b85 RK |
1 | /* |
2 | * Watchdog driver for the mpcore watchdog timer | |
3 | * | |
4 | * (c) Copyright 2004 ARM Limited | |
5 | * | |
6 | * Based on the SoftDog driver: | |
29fa0586 | 7 | * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>, |
143a2e54 | 8 | * All Rights Reserved. |
b9d36b85 RK |
9 | * |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License | |
12 | * as published by the Free Software Foundation; either version | |
13 | * 2 of the License, or (at your option) any later version. | |
14 | * | |
15 | * Neither Alan Cox nor CymruNet Ltd. admit liability nor provide | |
16 | * warranty for any of this software. This material is provided | |
17 | * "AS-IS" and at no charge. | |
18 | * | |
19 | * (c) Copyright 1995 Alan Cox <alan@lxorguk.ukuu.org.uk> | |
20 | * | |
21 | */ | |
27c766aa JP |
22 | |
23 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
24 | ||
b9d36b85 RK |
25 | #include <linux/module.h> |
26 | #include <linux/moduleparam.h> | |
b9d36b85 RK |
27 | #include <linux/types.h> |
28 | #include <linux/miscdevice.h> | |
29 | #include <linux/watchdog.h> | |
30 | #include <linux/fs.h> | |
31 | #include <linux/reboot.h> | |
32 | #include <linux/init.h> | |
33 | #include <linux/interrupt.h> | |
d052d1be | 34 | #include <linux/platform_device.h> |
83ab1a53 | 35 | #include <linux/uaccess.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
98af0570 | 37 | #include <linux/io.h> |
ad4162f3 | 38 | |
98af0570 | 39 | #include <asm/smp_twd.h> |
b9d36b85 RK |
40 | |
41 | struct mpcore_wdt { | |
42 | unsigned long timer_alive; | |
43 | struct device *dev; | |
44 | void __iomem *base; | |
45 | int irq; | |
46 | unsigned int perturb; | |
47 | char expect_close; | |
48 | }; | |
49 | ||
aa065770 | 50 | static struct platform_device *mpcore_wdt_pdev; |
98af0570 | 51 | static DEFINE_SPINLOCK(wdt_lock); |
b9d36b85 RK |
52 | |
53 | #define TIMER_MARGIN 60 | |
54 | static int mpcore_margin = TIMER_MARGIN; | |
55 | module_param(mpcore_margin, int, 0); | |
83ab1a53 AC |
56 | MODULE_PARM_DESC(mpcore_margin, |
57 | "MPcore timer margin in seconds. (0 < mpcore_margin < 65536, default=" | |
58 | __MODULE_STRING(TIMER_MARGIN) ")"); | |
b9d36b85 | 59 | |
86a1e189 WVS |
60 | static bool nowayout = WATCHDOG_NOWAYOUT; |
61 | module_param(nowayout, bool, 0); | |
83ab1a53 AC |
62 | MODULE_PARM_DESC(nowayout, |
63 | "Watchdog cannot be stopped once started (default=" | |
64 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
b9d36b85 RK |
65 | |
66 | #define ONLY_TESTING 0 | |
67 | static int mpcore_noboot = ONLY_TESTING; | |
68 | module_param(mpcore_noboot, int, 0); | |
a77dba7e WVS |
69 | MODULE_PARM_DESC(mpcore_noboot, "MPcore watchdog action, " |
70 | "set to 1 to ignore reboots, 0 to reboot (default=" | |
71 | __MODULE_STRING(ONLY_TESTING) ")"); | |
b9d36b85 RK |
72 | |
73 | /* | |
74 | * This is the interrupt handler. Note that we only use this | |
75 | * in testing mode, so don't actually do a reboot here. | |
76 | */ | |
7d12e780 | 77 | static irqreturn_t mpcore_wdt_fire(int irq, void *arg) |
b9d36b85 RK |
78 | { |
79 | struct mpcore_wdt *wdt = arg; | |
80 | ||
81 | /* Check it really was our interrupt */ | |
82 | if (readl(wdt->base + TWD_WDOG_INTSTAT)) { | |
77e0dfcc | 83 | dev_crit(wdt->dev, "Triggered - Reboot ignored\n"); |
b9d36b85 RK |
84 | /* Clear the interrupt on the watchdog */ |
85 | writel(1, wdt->base + TWD_WDOG_INTSTAT); | |
b9d36b85 RK |
86 | return IRQ_HANDLED; |
87 | } | |
b9d36b85 RK |
88 | return IRQ_NONE; |
89 | } | |
90 | ||
91 | /* | |
92 | * mpcore_wdt_keepalive - reload the timer | |
93 | * | |
94 | * Note that the spec says a DIFFERENT value must be written to the reload | |
95 | * register each time. The "perturb" variable deals with this by adding 1 | |
96 | * to the count every other time the function is called. | |
97 | */ | |
98 | static void mpcore_wdt_keepalive(struct mpcore_wdt *wdt) | |
99 | { | |
98af0570 | 100 | unsigned long count; |
b9d36b85 | 101 | |
98af0570 | 102 | spin_lock(&wdt_lock); |
b9d36b85 | 103 | /* Assume prescale is set to 256 */ |
98af0570 SK |
104 | count = __raw_readl(wdt->base + TWD_WDOG_COUNTER); |
105 | count = (0xFFFFFFFFU - count) * (HZ / 5); | |
106 | count = (count / 256) * mpcore_margin; | |
b9d36b85 RK |
107 | |
108 | /* Reload the counter */ | |
109 | writel(count + wdt->perturb, wdt->base + TWD_WDOG_LOAD); | |
b9d36b85 | 110 | wdt->perturb = wdt->perturb ? 0 : 1; |
83ab1a53 | 111 | spin_unlock(&wdt_lock); |
b9d36b85 RK |
112 | } |
113 | ||
114 | static void mpcore_wdt_stop(struct mpcore_wdt *wdt) | |
115 | { | |
83ab1a53 | 116 | spin_lock(&wdt_lock); |
b9d36b85 RK |
117 | writel(0x12345678, wdt->base + TWD_WDOG_DISABLE); |
118 | writel(0x87654321, wdt->base + TWD_WDOG_DISABLE); | |
119 | writel(0x0, wdt->base + TWD_WDOG_CONTROL); | |
83ab1a53 | 120 | spin_unlock(&wdt_lock); |
b9d36b85 RK |
121 | } |
122 | ||
123 | static void mpcore_wdt_start(struct mpcore_wdt *wdt) | |
124 | { | |
77e0dfcc | 125 | dev_info(wdt->dev, "enabling watchdog\n"); |
b9d36b85 RK |
126 | |
127 | /* This loads the count register but does NOT start the count yet */ | |
128 | mpcore_wdt_keepalive(wdt); | |
129 | ||
130 | if (mpcore_noboot) { | |
131 | /* Enable watchdog - prescale=256, watchdog mode=0, enable=1 */ | |
132 | writel(0x0000FF01, wdt->base + TWD_WDOG_CONTROL); | |
133 | } else { | |
134 | /* Enable watchdog - prescale=256, watchdog mode=1, enable=1 */ | |
135 | writel(0x0000FF09, wdt->base + TWD_WDOG_CONTROL); | |
136 | } | |
137 | } | |
138 | ||
139 | static int mpcore_wdt_set_heartbeat(int t) | |
140 | { | |
141 | if (t < 0x0001 || t > 0xFFFF) | |
142 | return -EINVAL; | |
143 | ||
144 | mpcore_margin = t; | |
145 | return 0; | |
146 | } | |
147 | ||
148 | /* | |
149 | * /dev/watchdog handling | |
150 | */ | |
151 | static int mpcore_wdt_open(struct inode *inode, struct file *file) | |
152 | { | |
aa065770 | 153 | struct mpcore_wdt *wdt = platform_get_drvdata(mpcore_wdt_pdev); |
b9d36b85 RK |
154 | |
155 | if (test_and_set_bit(0, &wdt->timer_alive)) | |
156 | return -EBUSY; | |
157 | ||
158 | if (nowayout) | |
159 | __module_get(THIS_MODULE); | |
160 | ||
161 | file->private_data = wdt; | |
162 | ||
163 | /* | |
164 | * Activate timer | |
165 | */ | |
166 | mpcore_wdt_start(wdt); | |
167 | ||
168 | return nonseekable_open(inode, file); | |
169 | } | |
170 | ||
171 | static int mpcore_wdt_release(struct inode *inode, struct file *file) | |
172 | { | |
173 | struct mpcore_wdt *wdt = file->private_data; | |
174 | ||
175 | /* | |
176 | * Shut off the timer. | |
5f3b2756 | 177 | * Lock it in if it's a module and we set nowayout |
b9d36b85 | 178 | */ |
83ab1a53 | 179 | if (wdt->expect_close == 42) |
b9d36b85 | 180 | mpcore_wdt_stop(wdt); |
83ab1a53 | 181 | else { |
77e0dfcc JP |
182 | dev_crit(wdt->dev, |
183 | "unexpected close, not stopping watchdog!\n"); | |
b9d36b85 RK |
184 | mpcore_wdt_keepalive(wdt); |
185 | } | |
186 | clear_bit(0, &wdt->timer_alive); | |
187 | wdt->expect_close = 0; | |
188 | return 0; | |
189 | } | |
190 | ||
83ab1a53 AC |
191 | static ssize_t mpcore_wdt_write(struct file *file, const char *data, |
192 | size_t len, loff_t *ppos) | |
b9d36b85 RK |
193 | { |
194 | struct mpcore_wdt *wdt = file->private_data; | |
195 | ||
b9d36b85 RK |
196 | /* |
197 | * Refresh the timer. | |
198 | */ | |
199 | if (len) { | |
200 | if (!nowayout) { | |
201 | size_t i; | |
202 | ||
203 | /* In case it was set long ago */ | |
204 | wdt->expect_close = 0; | |
205 | ||
206 | for (i = 0; i != len; i++) { | |
207 | char c; | |
208 | ||
209 | if (get_user(c, data + i)) | |
210 | return -EFAULT; | |
211 | if (c == 'V') | |
212 | wdt->expect_close = 42; | |
213 | } | |
214 | } | |
215 | mpcore_wdt_keepalive(wdt); | |
216 | } | |
217 | return len; | |
218 | } | |
219 | ||
42747d71 | 220 | static const struct watchdog_info ident = { |
b9d36b85 RK |
221 | .options = WDIOF_SETTIMEOUT | |
222 | WDIOF_KEEPALIVEPING | | |
223 | WDIOF_MAGICCLOSE, | |
224 | .identity = "MPcore Watchdog", | |
225 | }; | |
226 | ||
83ab1a53 AC |
227 | static long mpcore_wdt_ioctl(struct file *file, unsigned int cmd, |
228 | unsigned long arg) | |
b9d36b85 RK |
229 | { |
230 | struct mpcore_wdt *wdt = file->private_data; | |
231 | int ret; | |
232 | union { | |
233 | struct watchdog_info ident; | |
234 | int i; | |
235 | } uarg; | |
236 | ||
237 | if (_IOC_DIR(cmd) && _IOC_SIZE(cmd) > sizeof(uarg)) | |
795b89d2 | 238 | return -ENOTTY; |
b9d36b85 RK |
239 | |
240 | if (_IOC_DIR(cmd) & _IOC_WRITE) { | |
241 | ret = copy_from_user(&uarg, (void __user *)arg, _IOC_SIZE(cmd)); | |
242 | if (ret) | |
243 | return -EFAULT; | |
244 | } | |
245 | ||
246 | switch (cmd) { | |
247 | case WDIOC_GETSUPPORT: | |
248 | uarg.ident = ident; | |
249 | ret = 0; | |
250 | break; | |
251 | ||
0c06090c WVS |
252 | case WDIOC_GETSTATUS: |
253 | case WDIOC_GETBOOTSTATUS: | |
254 | uarg.i = 0; | |
255 | ret = 0; | |
256 | break; | |
257 | ||
b9d36b85 RK |
258 | case WDIOC_SETOPTIONS: |
259 | ret = -EINVAL; | |
260 | if (uarg.i & WDIOS_DISABLECARD) { | |
261 | mpcore_wdt_stop(wdt); | |
262 | ret = 0; | |
263 | } | |
264 | if (uarg.i & WDIOS_ENABLECARD) { | |
265 | mpcore_wdt_start(wdt); | |
266 | ret = 0; | |
267 | } | |
268 | break; | |
269 | ||
b9d36b85 RK |
270 | case WDIOC_KEEPALIVE: |
271 | mpcore_wdt_keepalive(wdt); | |
272 | ret = 0; | |
273 | break; | |
274 | ||
275 | case WDIOC_SETTIMEOUT: | |
276 | ret = mpcore_wdt_set_heartbeat(uarg.i); | |
277 | if (ret) | |
278 | break; | |
279 | ||
280 | mpcore_wdt_keepalive(wdt); | |
281 | /* Fall */ | |
282 | case WDIOC_GETTIMEOUT: | |
283 | uarg.i = mpcore_margin; | |
284 | ret = 0; | |
285 | break; | |
286 | ||
287 | default: | |
795b89d2 | 288 | return -ENOTTY; |
b9d36b85 RK |
289 | } |
290 | ||
291 | if (ret == 0 && _IOC_DIR(cmd) & _IOC_READ) { | |
292 | ret = copy_to_user((void __user *)arg, &uarg, _IOC_SIZE(cmd)); | |
293 | if (ret) | |
294 | ret = -EFAULT; | |
295 | } | |
296 | return ret; | |
297 | } | |
298 | ||
299 | /* | |
300 | * System shutdown handler. Turn off the watchdog if we're | |
301 | * restarting or halting the system. | |
302 | */ | |
aa065770 | 303 | static void mpcore_wdt_shutdown(struct platform_device *pdev) |
b9d36b85 | 304 | { |
aa065770 | 305 | struct mpcore_wdt *wdt = platform_get_drvdata(pdev); |
b9d36b85 RK |
306 | |
307 | if (system_state == SYSTEM_RESTART || system_state == SYSTEM_HALT) | |
308 | mpcore_wdt_stop(wdt); | |
309 | } | |
310 | ||
311 | /* | |
312 | * Kernel Interfaces | |
313 | */ | |
62322d25 | 314 | static const struct file_operations mpcore_wdt_fops = { |
b9d36b85 RK |
315 | .owner = THIS_MODULE, |
316 | .llseek = no_llseek, | |
317 | .write = mpcore_wdt_write, | |
83ab1a53 | 318 | .unlocked_ioctl = mpcore_wdt_ioctl, |
b9d36b85 RK |
319 | .open = mpcore_wdt_open, |
320 | .release = mpcore_wdt_release, | |
321 | }; | |
322 | ||
323 | static struct miscdevice mpcore_wdt_miscdev = { | |
324 | .minor = WATCHDOG_MINOR, | |
325 | .name = "watchdog", | |
326 | .fops = &mpcore_wdt_fops, | |
327 | }; | |
328 | ||
2d991a16 | 329 | static int mpcore_wdt_probe(struct platform_device *pdev) |
b9d36b85 | 330 | { |
b9d36b85 RK |
331 | struct mpcore_wdt *wdt; |
332 | struct resource *res; | |
333 | int ret; | |
334 | ||
335 | /* We only accept one device, and it must have an id of -1 */ | |
aa065770 | 336 | if (pdev->id != -1) |
b9d36b85 RK |
337 | return -ENODEV; |
338 | ||
aa065770 | 339 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
75f5a536 VK |
340 | if (!res) |
341 | return -ENODEV; | |
b9d36b85 | 342 | |
75f5a536 VK |
343 | wdt = devm_kzalloc(&pdev->dev, sizeof(struct mpcore_wdt), GFP_KERNEL); |
344 | if (!wdt) | |
345 | return -ENOMEM; | |
b9d36b85 | 346 | |
aa065770 VK |
347 | wdt->dev = &pdev->dev; |
348 | wdt->irq = platform_get_irq(pdev, 0); | |
60a1aa50 VK |
349 | if (wdt->irq >= 0) { |
350 | ret = devm_request_irq(wdt->dev, wdt->irq, mpcore_wdt_fire, 0, | |
351 | "mpcore_wdt", wdt); | |
352 | if (ret) { | |
77e0dfcc JP |
353 | dev_err(wdt->dev, |
354 | "cannot register IRQ%d for watchdog\n", | |
355 | wdt->irq); | |
60a1aa50 VK |
356 | return ret; |
357 | } | |
b9d36b85 RK |
358 | } |
359 | ||
75f5a536 VK |
360 | wdt->base = devm_ioremap(wdt->dev, res->start, resource_size(res)); |
361 | if (!wdt->base) | |
362 | return -ENOMEM; | |
363 | ||
aa065770 | 364 | mpcore_wdt_miscdev.parent = &pdev->dev; |
b9d36b85 RK |
365 | ret = misc_register(&mpcore_wdt_miscdev); |
366 | if (ret) { | |
77e0dfcc | 367 | dev_err(wdt->dev, |
83ab1a53 | 368 | "cannot register miscdev on minor=%d (err=%d)\n", |
77e0dfcc | 369 | WATCHDOG_MINOR, ret); |
75f5a536 | 370 | return ret; |
b9d36b85 RK |
371 | } |
372 | ||
373 | mpcore_wdt_stop(wdt); | |
aa065770 VK |
374 | platform_set_drvdata(pdev, wdt); |
375 | mpcore_wdt_pdev = pdev; | |
b9d36b85 RK |
376 | |
377 | return 0; | |
b9d36b85 RK |
378 | } |
379 | ||
4b12b896 | 380 | static int mpcore_wdt_remove(struct platform_device *pdev) |
b9d36b85 | 381 | { |
aa065770 | 382 | platform_set_drvdata(pdev, NULL); |
b9d36b85 RK |
383 | |
384 | misc_deregister(&mpcore_wdt_miscdev); | |
385 | ||
aa065770 | 386 | mpcore_wdt_pdev = NULL; |
b9d36b85 | 387 | |
b9d36b85 RK |
388 | return 0; |
389 | } | |
390 | ||
641e4f44 | 391 | #ifdef CONFIG_PM |
aa065770 | 392 | static int mpcore_wdt_suspend(struct platform_device *pdev, pm_message_t msg) |
641e4f44 | 393 | { |
aa065770 | 394 | struct mpcore_wdt *wdt = platform_get_drvdata(pdev); |
641e4f44 PF |
395 | mpcore_wdt_stop(wdt); /* Turn the WDT off */ |
396 | return 0; | |
397 | } | |
398 | ||
aa065770 | 399 | static int mpcore_wdt_resume(struct platform_device *pdev) |
641e4f44 | 400 | { |
aa065770 | 401 | struct mpcore_wdt *wdt = platform_get_drvdata(pdev); |
641e4f44 PF |
402 | /* re-activate timer */ |
403 | if (test_bit(0, &wdt->timer_alive)) | |
404 | mpcore_wdt_start(wdt); | |
405 | return 0; | |
406 | } | |
407 | #else | |
408 | #define mpcore_wdt_suspend NULL | |
409 | #define mpcore_wdt_resume NULL | |
410 | #endif | |
411 | ||
f37d193c KS |
412 | /* work with hotplug and coldplug */ |
413 | MODULE_ALIAS("platform:mpcore_wdt"); | |
414 | ||
3ae5eaec | 415 | static struct platform_driver mpcore_wdt_driver = { |
b9d36b85 | 416 | .probe = mpcore_wdt_probe, |
82268714 | 417 | .remove = mpcore_wdt_remove, |
641e4f44 PF |
418 | .suspend = mpcore_wdt_suspend, |
419 | .resume = mpcore_wdt_resume, | |
b9d36b85 | 420 | .shutdown = mpcore_wdt_shutdown, |
3ae5eaec RK |
421 | .driver = { |
422 | .owner = THIS_MODULE, | |
423 | .name = "mpcore_wdt", | |
424 | }, | |
b9d36b85 RK |
425 | }; |
426 | ||
b9d36b85 RK |
427 | static int __init mpcore_wdt_init(void) |
428 | { | |
429 | /* | |
430 | * Check that the margin value is within it's range; | |
431 | * if not reset to the default | |
432 | */ | |
433 | if (mpcore_wdt_set_heartbeat(mpcore_margin)) { | |
434 | mpcore_wdt_set_heartbeat(TIMER_MARGIN); | |
27c766aa | 435 | pr_info("mpcore_margin value must be 0 < mpcore_margin < 65536, using %d\n", |
b9d36b85 RK |
436 | TIMER_MARGIN); |
437 | } | |
438 | ||
27c766aa JP |
439 | pr_info("MPcore Watchdog Timer: 0.1. mpcore_noboot=%d mpcore_margin=%d sec (nowayout= %d)\n", |
440 | mpcore_noboot, mpcore_margin, nowayout); | |
b9d36b85 | 441 | |
3ae5eaec | 442 | return platform_driver_register(&mpcore_wdt_driver); |
b9d36b85 RK |
443 | } |
444 | ||
445 | static void __exit mpcore_wdt_exit(void) | |
446 | { | |
3ae5eaec | 447 | platform_driver_unregister(&mpcore_wdt_driver); |
b9d36b85 RK |
448 | } |
449 | ||
450 | module_init(mpcore_wdt_init); | |
451 | module_exit(mpcore_wdt_exit); | |
452 | ||
453 | MODULE_AUTHOR("ARM Limited"); | |
454 | MODULE_DESCRIPTION("MPcore Watchdog Device Driver"); | |
455 | MODULE_LICENSE("GPL"); | |
456 | MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); |