[deliverable/linux.git] / drivers / watchdog / mtk_wdt.c

/*
 * Mediatek Watchdog Driver
 *
 * Copyright (C) 2014 Matthias Brugger
 *
 * Matthias Brugger <matthias.bgg@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * Based on sunxi_wdt.c
 */

#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/types.h>
#include <linux/watchdog.h>
#include <linux/delay.h>

#define WDT_MAX_TIMEOUT		31
#define WDT_MIN_TIMEOUT		1
#define WDT_LENGTH_TIMEOUT(n)	((n) << 5)

#define WDT_LENGTH		0x04
#define WDT_LENGTH_KEY		0x8

#define WDT_RST			0x08
#define WDT_RST_RELOAD		0x1971

#define WDT_MODE		0x00
#define WDT_MODE_EN		(1 << 0)
#define WDT_MODE_EXT_POL_LOW	(0 << 1)
#define WDT_MODE_EXT_POL_HIGH	(1 << 1)
#define WDT_MODE_EXRST_EN	(1 << 2)
#define WDT_MODE_IRQ_EN		(1 << 3)
#define WDT_MODE_AUTO_START	(1 << 4)
#define WDT_MODE_DUAL_EN	(1 << 6)
#define WDT_MODE_KEY		0x22000000

#define WDT_SWRST		0x14
#define WDT_SWRST_KEY		0x1209

#define DRV_NAME		"mtk-wdt"
#define DRV_VERSION		"1.0"

static bool nowayout = WATCHDOG_NOWAYOUT;
static unsigned int timeout = WDT_MAX_TIMEOUT;

struct mtk_wdt_dev {
	struct watchdog_device wdt_dev;
	void __iomem *wdt_base;
};

static int mtk_wdt_restart(struct watchdog_device *wdt_dev)
{
	struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
	void __iomem *wdt_base;

	wdt_base = mtk_wdt->wdt_base;

	while (1) {
		writel(WDT_SWRST_KEY, wdt_base + WDT_SWRST);
		mdelay(5);
	}

	return 0;
}

static int mtk_wdt_ping(struct watchdog_device *wdt_dev)
{
	struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
	void __iomem *wdt_base = mtk_wdt->wdt_base;

	iowrite32(WDT_RST_RELOAD, wdt_base + WDT_RST);

	return 0;
}

static int mtk_wdt_set_timeout(struct watchdog_device *wdt_dev,
				unsigned int timeout)
{
	struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
	void __iomem *wdt_base = mtk_wdt->wdt_base;
	u32 reg;

	wdt_dev->timeout = timeout;

	/*
	 * One bit is the value of 512 ticks
	 * The clock has 32 KHz
	 */
	reg = WDT_LENGTH_TIMEOUT(timeout << 6) | WDT_LENGTH_KEY;
	iowrite32(reg, wdt_base + WDT_LENGTH);

	mtk_wdt_ping(wdt_dev);

	return 0;
}

static int mtk_wdt_stop(struct watchdog_device *wdt_dev)
{
	struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
	void __iomem *wdt_base = mtk_wdt->wdt_base;
	u32 reg;

	reg = readl(wdt_base + WDT_MODE);
	reg &= ~WDT_MODE_EN;
	reg |= WDT_MODE_KEY;
	iowrite32(reg, wdt_base + WDT_MODE);

	return 0;
}

static int mtk_wdt_start(struct watchdog_device *wdt_dev)
{
	u32 reg;
	struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
	void __iomem *wdt_base = mtk_wdt->wdt_base;
	int ret;

	ret = mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
	if (ret < 0)
		return ret;

	reg = ioread32(wdt_base + WDT_MODE);
	reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
	reg |= (WDT_MODE_EN | WDT_MODE_KEY);
	iowrite32(reg, wdt_base + WDT_MODE);

	return 0;
}

static const struct watchdog_info mtk_wdt_info = {
	.identity	= DRV_NAME,
	.options	= WDIOF_SETTIMEOUT |
			  WDIOF_KEEPALIVEPING |
			  WDIOF_MAGICCLOSE,
};

static const struct watchdog_ops mtk_wdt_ops = {
	.owner		= THIS_MODULE,
	.start		= mtk_wdt_start,
	.stop		= mtk_wdt_stop,
	.ping		= mtk_wdt_ping,
	.set_timeout	= mtk_wdt_set_timeout,
	.restart	= mtk_wdt_restart,
};

static int mtk_wdt_probe(struct platform_device *pdev)
{
	struct mtk_wdt_dev *mtk_wdt;
	struct resource *res;
	int err;

	mtk_wdt = devm_kzalloc(&pdev->dev, sizeof(*mtk_wdt), GFP_KERNEL);
	if (!mtk_wdt)
		return -ENOMEM;

	platform_set_drvdata(pdev, mtk_wdt);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	mtk_wdt->wdt_base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(mtk_wdt->wdt_base))
		return PTR_ERR(mtk_wdt->wdt_base);

	mtk_wdt->wdt_dev.info = &mtk_wdt_info;
	mtk_wdt->wdt_dev.ops = &mtk_wdt_ops;
	mtk_wdt->wdt_dev.timeout = WDT_MAX_TIMEOUT;
	mtk_wdt->wdt_dev.max_timeout = WDT_MAX_TIMEOUT;
	mtk_wdt->wdt_dev.min_timeout = WDT_MIN_TIMEOUT;
	mtk_wdt->wdt_dev.parent = &pdev->dev;

	watchdog_init_timeout(&mtk_wdt->wdt_dev, timeout, &pdev->dev);
	watchdog_set_nowayout(&mtk_wdt->wdt_dev, nowayout);
	watchdog_set_restart_priority(&mtk_wdt->wdt_dev, 128);

	watchdog_set_drvdata(&mtk_wdt->wdt_dev, mtk_wdt);

	mtk_wdt_stop(&mtk_wdt->wdt_dev);

	err = watchdog_register_device(&mtk_wdt->wdt_dev);
	if (unlikely(err))
		return err;

	dev_info(&pdev->dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)\n",
			mtk_wdt->wdt_dev.timeout, nowayout);

	return 0;
}

static void mtk_wdt_shutdown(struct platform_device *pdev)
{
	struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev);

	if (watchdog_active(&mtk_wdt->wdt_dev))
		mtk_wdt_stop(&mtk_wdt->wdt_dev);
}

static int mtk_wdt_remove(struct platform_device *pdev)
{
	struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev);

	watchdog_unregister_device(&mtk_wdt->wdt_dev);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int mtk_wdt_suspend(struct device *dev)
{
	struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev);

	if (watchdog_active(&mtk_wdt->wdt_dev))
		mtk_wdt_stop(&mtk_wdt->wdt_dev);

	return 0;
}

static int mtk_wdt_resume(struct device *dev)
{
	struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev);

	if (watchdog_active(&mtk_wdt->wdt_dev)) {
		mtk_wdt_start(&mtk_wdt->wdt_dev);
		mtk_wdt_ping(&mtk_wdt->wdt_dev);
	}

	return 0;
}
#endif

static const struct of_device_id mtk_wdt_dt_ids[] = {
	{ .compatible = "mediatek,mt6589-wdt" },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);

static const struct dev_pm_ops mtk_wdt_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(mtk_wdt_suspend,
				mtk_wdt_resume)
};

static struct platform_driver mtk_wdt_driver = {
	.probe		= mtk_wdt_probe,
	.remove		= mtk_wdt_remove,
	.shutdown	= mtk_wdt_shutdown,
	.driver		= {
		.name		= DRV_NAME,
		.pm		= &mtk_wdt_pm_ops,
		.of_match_table	= mtk_wdt_dt_ids,
	},
};

module_platform_driver(mtk_wdt_driver);

module_param(timeout, uint, 0);
MODULE_PARM_DESC(timeout, "Watchdog heartbeat in seconds");

module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
			__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Matthias Brugger <matthias.bgg@gmail.com>");
MODULE_DESCRIPTION("Mediatek WatchDog Timer Driver");
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
a44a4553 MB	1	/*
	2	* Mediatek Watchdog Driver
	3	*
	4	* Copyright (C) 2014 Matthias Brugger
	5	*
	6	* Matthias Brugger <matthias.bgg@gmail.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* Based on sunxi_wdt.c
	19	*/
	20
	21	#include <linux/err.h>
	22	#include <linux/init.h>
	23	#include <linux/io.h>
	24	#include <linux/kernel.h>
	25	#include <linux/module.h>
	26	#include <linux/moduleparam.h>
	27	#include <linux/of.h>
	28	#include <linux/platform_device.h>
	29	#include <linux/types.h>
	30	#include <linux/watchdog.h>
a44a4553 MB	31	#include <linux/delay.h>
	32
	33	#define WDT_MAX_TIMEOUT 31
	34	#define WDT_MIN_TIMEOUT 1
	35	#define WDT_LENGTH_TIMEOUT(n) ((n) << 5)
	36
	37	#define WDT_LENGTH 0x04
	38	#define WDT_LENGTH_KEY 0x8
	39
	40	#define WDT_RST 0x08
	41	#define WDT_RST_RELOAD 0x1971
	42
	43	#define WDT_MODE 0x00
	44	#define WDT_MODE_EN (1 << 0)
	45	#define WDT_MODE_EXT_POL_LOW (0 << 1)
	46	#define WDT_MODE_EXT_POL_HIGH (1 << 1)
	47	#define WDT_MODE_EXRST_EN (1 << 2)
	48	#define WDT_MODE_IRQ_EN (1 << 3)
	49	#define WDT_MODE_AUTO_START (1 << 4)
	50	#define WDT_MODE_DUAL_EN (1 << 6)
	51	#define WDT_MODE_KEY 0x22000000
	52
	53	#define WDT_SWRST 0x14
	54	#define WDT_SWRST_KEY 0x1209
	55
	56	#define DRV_NAME "mtk-wdt"
	57	#define DRV_VERSION "1.0"
	58
	59	static bool nowayout = WATCHDOG_NOWAYOUT;
	60	static unsigned int timeout = WDT_MAX_TIMEOUT;
	61
	62	struct mtk_wdt_dev {
	63	struct watchdog_device wdt_dev;
	64	void __iomem *wdt_base;
a44a4553 MB	65	};
a44a4553 MB	66
e86adc3f	67	static int mtk_wdt_restart(struct watchdog_device *wdt_dev)
a44a4553	68	{
e86adc3f	69	struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
a44a4553 MB	70	void __iomem *wdt_base;
a44a4553 MB	71
a44a4553 MB	72	wdt_base = mtk_wdt->wdt_base;
	73
	74	while (1) {
	75	writel(WDT_SWRST_KEY, wdt_base + WDT_SWRST);
	76	mdelay(5);
	77	}
	78
e86adc3f	79	return 0;
a44a4553 MB	80	}
	81
	82	static int mtk_wdt_ping(struct watchdog_device *wdt_dev)
	83	{
	84	struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
	85	void __iomem *wdt_base = mtk_wdt->wdt_base;
	86
	87	iowrite32(WDT_RST_RELOAD, wdt_base + WDT_RST);
	88
	89	return 0;
	90	}
	91
	92	static int mtk_wdt_set_timeout(struct watchdog_device *wdt_dev,
	93	unsigned int timeout)
	94	{
	95	struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
	96	void __iomem *wdt_base = mtk_wdt->wdt_base;
	97	u32 reg;
	98
	99	wdt_dev->timeout = timeout;
	100
	101	/*
	102	* One bit is the value of 512 ticks
	103	* The clock has 32 KHz
	104	*/
	105	reg = WDT_LENGTH_TIMEOUT(timeout << 6) \| WDT_LENGTH_KEY;
	106	iowrite32(reg, wdt_base + WDT_LENGTH);
	107
	108	mtk_wdt_ping(wdt_dev);
	109
	110	return 0;
	111	}
	112
	113	static int mtk_wdt_stop(struct watchdog_device *wdt_dev)
	114	{
	115	struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
	116	void __iomem *wdt_base = mtk_wdt->wdt_base;
	117	u32 reg;
	118
	119	reg = readl(wdt_base + WDT_MODE);
	120	reg &= ~WDT_MODE_EN;
5da2bf1a	121	reg \|= WDT_MODE_KEY;
a44a4553 MB	122	iowrite32(reg, wdt_base + WDT_MODE);
	123
	124	return 0;
	125	}
	126
	127	static int mtk_wdt_start(struct watchdog_device *wdt_dev)
	128	{
	129	u32 reg;
	130	struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
	131	void __iomem *wdt_base = mtk_wdt->wdt_base;
9ffd906d	132	int ret;
a44a4553 MB	133
	134	ret = mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
	135	if (ret < 0)
	136	return ret;
	137
	138	reg = ioread32(wdt_base + WDT_MODE);
	139	reg &= ~(WDT_MODE_IRQ_EN \| WDT_MODE_DUAL_EN);
	140	reg \|= (WDT_MODE_EN \| WDT_MODE_KEY);
	141	iowrite32(reg, wdt_base + WDT_MODE);
	142
	143	return 0;
	144	}
	145
	146	static const struct watchdog_info mtk_wdt_info = {
	147	.identity = DRV_NAME,
	148	.options = WDIOF_SETTIMEOUT \|
	149	WDIOF_KEEPALIVEPING \|
	150	WDIOF_MAGICCLOSE,
	151	};
	152
	153	static const struct watchdog_ops mtk_wdt_ops = {
	154	.owner = THIS_MODULE,
	155	.start = mtk_wdt_start,
	156	.stop = mtk_wdt_stop,
	157	.ping = mtk_wdt_ping,
	158	.set_timeout = mtk_wdt_set_timeout,
e86adc3f	159	.restart = mtk_wdt_restart,
a44a4553 MB	160	};
	161
	162	static int mtk_wdt_probe(struct platform_device *pdev)
	163	{
	164	struct mtk_wdt_dev *mtk_wdt;
	165	struct resource *res;
	166	int err;
	167
	168	mtk_wdt = devm_kzalloc(&pdev->dev, sizeof(*mtk_wdt), GFP_KERNEL);
	169	if (!mtk_wdt)
	170	return -ENOMEM;
	171
	172	platform_set_drvdata(pdev, mtk_wdt);
	173
	174	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	175	mtk_wdt->wdt_base = devm_ioremap_resource(&pdev->dev, res);
	176	if (IS_ERR(mtk_wdt->wdt_base))
	177	return PTR_ERR(mtk_wdt->wdt_base);
	178
	179	mtk_wdt->wdt_dev.info = &mtk_wdt_info;
	180	mtk_wdt->wdt_dev.ops = &mtk_wdt_ops;
	181	mtk_wdt->wdt_dev.timeout = WDT_MAX_TIMEOUT;
	182	mtk_wdt->wdt_dev.max_timeout = WDT_MAX_TIMEOUT;
	183	mtk_wdt->wdt_dev.min_timeout = WDT_MIN_TIMEOUT;
	184	mtk_wdt->wdt_dev.parent = &pdev->dev;
	185
	186	watchdog_init_timeout(&mtk_wdt->wdt_dev, timeout, &pdev->dev);
	187	watchdog_set_nowayout(&mtk_wdt->wdt_dev, nowayout);
e86adc3f	188	watchdog_set_restart_priority(&mtk_wdt->wdt_dev, 128);
a44a4553 MB	189
	190	watchdog_set_drvdata(&mtk_wdt->wdt_dev, mtk_wdt);
	191
	192	mtk_wdt_stop(&mtk_wdt->wdt_dev);
	193
	194	err = watchdog_register_device(&mtk_wdt->wdt_dev);
	195	if (unlikely(err))
	196	return err;
	197
a44a4553 MB	198	dev_info(&pdev->dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)\n",
	199	mtk_wdt->wdt_dev.timeout, nowayout);
	200
	201	return 0;
	202	}
	203
5724485b GZ	204	static void mtk_wdt_shutdown(struct platform_device *pdev)
	205	{
	206	struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev);
	207
	208	if (watchdog_active(&mtk_wdt->wdt_dev))
	209	mtk_wdt_stop(&mtk_wdt->wdt_dev);
	210	}
	211
a44a4553 MB	212	static int mtk_wdt_remove(struct platform_device *pdev)
	213	{
	214	struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev);
	215
a44a4553 MB	216	watchdog_unregister_device(&mtk_wdt->wdt_dev);
	217
	218	return 0;
	219	}
	220
9fab0692 GZ	221	#ifdef CONFIG_PM_SLEEP
	222	static int mtk_wdt_suspend(struct device *dev)
	223	{
	224	struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev);
	225
	226	if (watchdog_active(&mtk_wdt->wdt_dev))
	227	mtk_wdt_stop(&mtk_wdt->wdt_dev);
	228
	229	return 0;
	230	}
	231
	232	static int mtk_wdt_resume(struct device *dev)
	233	{
	234	struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev);
	235
	236	if (watchdog_active(&mtk_wdt->wdt_dev)) {
	237	mtk_wdt_start(&mtk_wdt->wdt_dev);
	238	mtk_wdt_ping(&mtk_wdt->wdt_dev);
	239	}
	240
	241	return 0;
	242	}
	243	#endif
	244
a44a4553 MB	245	static const struct of_device_id mtk_wdt_dt_ids[] = {
	246	{ .compatible = "mediatek,mt6589-wdt" },
	247	{ /* sentinel */ }
	248	};
	249	MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);
	250
9fab0692 GZ	251	static const struct dev_pm_ops mtk_wdt_pm_ops = {
	252	SET_SYSTEM_SLEEP_PM_OPS(mtk_wdt_suspend,
	253	mtk_wdt_resume)
	254	};
	255
a44a4553 MB	256	static struct platform_driver mtk_wdt_driver = {
	257	.probe = mtk_wdt_probe,
	258	.remove = mtk_wdt_remove,
5724485b	259	.shutdown = mtk_wdt_shutdown,
a44a4553 MB	260	.driver = {
a44a4553 MB	261	.name = DRV_NAME,
9fab0692	262	.pm = &mtk_wdt_pm_ops,
a44a4553 MB	263	.of_match_table = mtk_wdt_dt_ids,
	264	},
	265	};
	266
	267	module_platform_driver(mtk_wdt_driver);
	268
	269	module_param(timeout, uint, 0);
	270	MODULE_PARM_DESC(timeout, "Watchdog heartbeat in seconds");
	271
	272	module_param(nowayout, bool, 0);
	273	MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
	274	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
	275
	276	MODULE_LICENSE("GPL");
	277	MODULE_AUTHOR("Matthias Brugger <matthias.bgg@gmail.com>");
	278	MODULE_DESCRIPTION("Mediatek WatchDog Timer Driver");
	279	MODULE_VERSION(DRV_VERSION);