Commit | Line | Data |
---|---|---|
7768a13c | 1 | /* |
2817142f | 2 | * omap_wdt.c |
7768a13c | 3 | * |
2817142f | 4 | * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog |
7768a13c KS |
5 | * |
6 | * Author: MontaVista Software, Inc. | |
7 | * <gdavis@mvista.com> or <source@mvista.com> | |
8 | * | |
9 | * 2003 (c) MontaVista Software, Inc. This file is licensed under the | |
10 | * terms of the GNU General Public License version 2. This program is | |
11 | * licensed "as is" without any warranty of any kind, whether express | |
12 | * or implied. | |
13 | * | |
14 | * History: | |
15 | * | |
16 | * 20030527: George G. Davis <gdavis@mvista.com> | |
17 | * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c | |
18 | * (c) Copyright 2000 Oleg Drokin <green@crimea.edu> | |
29fa0586 | 19 | * Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk> |
7768a13c KS |
20 | * |
21 | * Copyright (c) 2004 Texas Instruments. | |
22 | * 1. Modified to support OMAP1610 32-KHz watchdog timer | |
23 | * 2. Ported to 2.6 kernel | |
24 | * | |
25 | * Copyright (c) 2005 David Brownell | |
26 | * Use the driver model and standard identifiers; handle bigger timeouts. | |
27 | */ | |
28 | ||
29 | #include <linux/module.h> | |
7768a13c KS |
30 | #include <linux/types.h> |
31 | #include <linux/kernel.h> | |
32 | #include <linux/fs.h> | |
33 | #include <linux/mm.h> | |
34 | #include <linux/miscdevice.h> | |
35 | #include <linux/watchdog.h> | |
36 | #include <linux/reboot.h> | |
7768a13c KS |
37 | #include <linux/init.h> |
38 | #include <linux/err.h> | |
39 | #include <linux/platform_device.h> | |
40 | #include <linux/moduleparam.h> | |
41 | #include <linux/clk.h> | |
1977f032 | 42 | #include <linux/bitops.h> |
089ab079 | 43 | #include <linux/io.h> |
12b9df7d | 44 | #include <linux/uaccess.h> |
5a0e3ad6 | 45 | #include <linux/slab.h> |
a09e64fb | 46 | #include <mach/hardware.h> |
ce491cf8 | 47 | #include <plat/prcm.h> |
7768a13c KS |
48 | |
49 | #include "omap_wdt.h" | |
50 | ||
2817142f FB |
51 | static struct platform_device *omap_wdt_dev; |
52 | ||
7768a13c KS |
53 | static unsigned timer_margin; |
54 | module_param(timer_margin, uint, 0); | |
55 | MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)"); | |
56 | ||
7768a13c | 57 | static unsigned int wdt_trgr_pattern = 0x1234; |
12b9df7d | 58 | static spinlock_t wdt_lock; |
7768a13c | 59 | |
2817142f FB |
60 | struct omap_wdt_dev { |
61 | void __iomem *base; /* physical */ | |
62 | struct device *dev; | |
63 | int omap_wdt_users; | |
39a80c7f RK |
64 | struct clk *ick; |
65 | struct clk *fck; | |
2817142f FB |
66 | struct resource *mem; |
67 | struct miscdevice omap_wdt_miscdev; | |
68 | }; | |
69 | ||
70 | static void omap_wdt_ping(struct omap_wdt_dev *wdev) | |
7768a13c | 71 | { |
2817142f | 72 | void __iomem *base = wdev->base; |
b3112180 | 73 | |
7768a13c | 74 | /* wait for posted write to complete */ |
9f69e3b0 | 75 | while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08) |
7768a13c | 76 | cpu_relax(); |
b3112180 | 77 | |
7768a13c | 78 | wdt_trgr_pattern = ~wdt_trgr_pattern; |
9f69e3b0 | 79 | __raw_writel(wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR)); |
b3112180 | 80 | |
7768a13c | 81 | /* wait for posted write to complete */ |
9f69e3b0 | 82 | while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08) |
7768a13c KS |
83 | cpu_relax(); |
84 | /* reloaded WCRR from WLDR */ | |
85 | } | |
86 | ||
2817142f | 87 | static void omap_wdt_enable(struct omap_wdt_dev *wdev) |
7768a13c | 88 | { |
b3112180 FB |
89 | void __iomem *base = wdev->base; |
90 | ||
7768a13c | 91 | /* Sequence to enable the watchdog */ |
9f69e3b0 FB |
92 | __raw_writel(0xBBBB, base + OMAP_WATCHDOG_SPR); |
93 | while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10) | |
7768a13c | 94 | cpu_relax(); |
b3112180 | 95 | |
9f69e3b0 FB |
96 | __raw_writel(0x4444, base + OMAP_WATCHDOG_SPR); |
97 | while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10) | |
7768a13c KS |
98 | cpu_relax(); |
99 | } | |
100 | ||
2817142f | 101 | static void omap_wdt_disable(struct omap_wdt_dev *wdev) |
7768a13c | 102 | { |
b3112180 FB |
103 | void __iomem *base = wdev->base; |
104 | ||
7768a13c | 105 | /* sequence required to disable watchdog */ |
9f69e3b0 FB |
106 | __raw_writel(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */ |
107 | while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10) | |
7768a13c | 108 | cpu_relax(); |
b3112180 | 109 | |
9f69e3b0 FB |
110 | __raw_writel(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */ |
111 | while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10) | |
7768a13c KS |
112 | cpu_relax(); |
113 | } | |
114 | ||
115 | static void omap_wdt_adjust_timeout(unsigned new_timeout) | |
116 | { | |
117 | if (new_timeout < TIMER_MARGIN_MIN) | |
118 | new_timeout = TIMER_MARGIN_DEFAULT; | |
119 | if (new_timeout > TIMER_MARGIN_MAX) | |
120 | new_timeout = TIMER_MARGIN_MAX; | |
121 | timer_margin = new_timeout; | |
122 | } | |
123 | ||
2817142f | 124 | static void omap_wdt_set_timeout(struct omap_wdt_dev *wdev) |
7768a13c KS |
125 | { |
126 | u32 pre_margin = GET_WLDR_VAL(timer_margin); | |
b3112180 | 127 | void __iomem *base = wdev->base; |
7768a13c KS |
128 | |
129 | /* just count up at 32 KHz */ | |
9f69e3b0 | 130 | while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04) |
7768a13c | 131 | cpu_relax(); |
b3112180 | 132 | |
9f69e3b0 FB |
133 | __raw_writel(pre_margin, base + OMAP_WATCHDOG_LDR); |
134 | while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04) | |
7768a13c KS |
135 | cpu_relax(); |
136 | } | |
137 | ||
138 | /* | |
139 | * Allow only one task to hold it open | |
140 | */ | |
7768a13c KS |
141 | static int omap_wdt_open(struct inode *inode, struct file *file) |
142 | { | |
b3112180 FB |
143 | struct omap_wdt_dev *wdev = platform_get_drvdata(omap_wdt_dev); |
144 | void __iomem *base = wdev->base; | |
145 | ||
2817142f | 146 | if (test_and_set_bit(1, (unsigned long *)&(wdev->omap_wdt_users))) |
7768a13c KS |
147 | return -EBUSY; |
148 | ||
4c5e1946 | 149 | clk_enable(wdev->ick); /* Enable the interface clock */ |
39a80c7f | 150 | clk_enable(wdev->fck); /* Enable the functional clock */ |
7768a13c KS |
151 | |
152 | /* initialize prescaler */ | |
9f69e3b0 | 153 | while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01) |
7768a13c | 154 | cpu_relax(); |
b3112180 | 155 | |
9f69e3b0 FB |
156 | __raw_writel((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL); |
157 | while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01) | |
7768a13c KS |
158 | cpu_relax(); |
159 | ||
2817142f FB |
160 | file->private_data = (void *) wdev; |
161 | ||
162 | omap_wdt_set_timeout(wdev); | |
789cd470 | 163 | omap_wdt_ping(wdev); /* trigger loading of new timeout value */ |
2817142f | 164 | omap_wdt_enable(wdev); |
b3112180 | 165 | |
ec9505a7 | 166 | return nonseekable_open(inode, file); |
7768a13c KS |
167 | } |
168 | ||
169 | static int omap_wdt_release(struct inode *inode, struct file *file) | |
170 | { | |
b3112180 FB |
171 | struct omap_wdt_dev *wdev = file->private_data; |
172 | ||
7768a13c KS |
173 | /* |
174 | * Shut off the timer unless NOWAYOUT is defined. | |
175 | */ | |
176 | #ifndef CONFIG_WATCHDOG_NOWAYOUT | |
7768a13c | 177 | |
2817142f | 178 | omap_wdt_disable(wdev); |
7768a13c | 179 | |
4c5e1946 | 180 | clk_disable(wdev->ick); |
39a80c7f | 181 | clk_disable(wdev->fck); |
7768a13c KS |
182 | #else |
183 | printk(KERN_CRIT "omap_wdt: Unexpected close, not stopping!\n"); | |
184 | #endif | |
2817142f | 185 | wdev->omap_wdt_users = 0; |
b3112180 | 186 | |
7768a13c KS |
187 | return 0; |
188 | } | |
189 | ||
12b9df7d | 190 | static ssize_t omap_wdt_write(struct file *file, const char __user *data, |
7768a13c KS |
191 | size_t len, loff_t *ppos) |
192 | { | |
b3112180 FB |
193 | struct omap_wdt_dev *wdev = file->private_data; |
194 | ||
7768a13c | 195 | /* Refresh LOAD_TIME. */ |
12b9df7d AC |
196 | if (len) { |
197 | spin_lock(&wdt_lock); | |
2817142f | 198 | omap_wdt_ping(wdev); |
12b9df7d AC |
199 | spin_unlock(&wdt_lock); |
200 | } | |
7768a13c KS |
201 | return len; |
202 | } | |
203 | ||
12b9df7d AC |
204 | static long omap_wdt_ioctl(struct file *file, unsigned int cmd, |
205 | unsigned long arg) | |
7768a13c | 206 | { |
2817142f | 207 | struct omap_wdt_dev *wdev; |
7768a13c | 208 | int new_margin; |
12b9df7d | 209 | static const struct watchdog_info ident = { |
7768a13c KS |
210 | .identity = "OMAP Watchdog", |
211 | .options = WDIOF_SETTIMEOUT, | |
212 | .firmware_version = 0, | |
213 | }; | |
b3112180 | 214 | |
2817142f | 215 | wdev = file->private_data; |
7768a13c KS |
216 | |
217 | switch (cmd) { | |
7768a13c KS |
218 | case WDIOC_GETSUPPORT: |
219 | return copy_to_user((struct watchdog_info __user *)arg, &ident, | |
220 | sizeof(ident)); | |
221 | case WDIOC_GETSTATUS: | |
222 | return put_user(0, (int __user *)arg); | |
223 | case WDIOC_GETBOOTSTATUS: | |
224 | if (cpu_is_omap16xx()) | |
9f69e3b0 | 225 | return put_user(__raw_readw(ARM_SYSST), |
7768a13c KS |
226 | (int __user *)arg); |
227 | if (cpu_is_omap24xx()) | |
228 | return put_user(omap_prcm_get_reset_sources(), | |
229 | (int __user *)arg); | |
230 | case WDIOC_KEEPALIVE: | |
12b9df7d | 231 | spin_lock(&wdt_lock); |
2817142f | 232 | omap_wdt_ping(wdev); |
12b9df7d | 233 | spin_unlock(&wdt_lock); |
7768a13c KS |
234 | return 0; |
235 | case WDIOC_SETTIMEOUT: | |
236 | if (get_user(new_margin, (int __user *)arg)) | |
237 | return -EFAULT; | |
238 | omap_wdt_adjust_timeout(new_margin); | |
239 | ||
12b9df7d | 240 | spin_lock(&wdt_lock); |
2817142f FB |
241 | omap_wdt_disable(wdev); |
242 | omap_wdt_set_timeout(wdev); | |
243 | omap_wdt_enable(wdev); | |
7768a13c | 244 | |
2817142f | 245 | omap_wdt_ping(wdev); |
12b9df7d | 246 | spin_unlock(&wdt_lock); |
7768a13c KS |
247 | /* Fall */ |
248 | case WDIOC_GETTIMEOUT: | |
249 | return put_user(timer_margin, (int __user *)arg); | |
0c06090c WVS |
250 | default: |
251 | return -ENOTTY; | |
7768a13c KS |
252 | } |
253 | } | |
254 | ||
2b8693c0 | 255 | static const struct file_operations omap_wdt_fops = { |
7768a13c KS |
256 | .owner = THIS_MODULE, |
257 | .write = omap_wdt_write, | |
12b9df7d | 258 | .unlocked_ioctl = omap_wdt_ioctl, |
7768a13c KS |
259 | .open = omap_wdt_open, |
260 | .release = omap_wdt_release, | |
6038f373 | 261 | .llseek = no_llseek, |
7768a13c KS |
262 | }; |
263 | ||
0e3912c7 | 264 | static int __devinit omap_wdt_probe(struct platform_device *pdev) |
7768a13c KS |
265 | { |
266 | struct resource *res, *mem; | |
2817142f | 267 | struct omap_wdt_dev *wdev; |
b3112180 | 268 | int ret; |
7768a13c KS |
269 | |
270 | /* reserve static register mappings */ | |
271 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
b3112180 FB |
272 | if (!res) { |
273 | ret = -ENOENT; | |
274 | goto err_get_resource; | |
275 | } | |
7768a13c | 276 | |
b3112180 FB |
277 | if (omap_wdt_dev) { |
278 | ret = -EBUSY; | |
279 | goto err_busy; | |
280 | } | |
2817142f | 281 | |
b782a563 | 282 | mem = request_mem_region(res->start, resource_size(res), pdev->name); |
b3112180 FB |
283 | if (!mem) { |
284 | ret = -EBUSY; | |
285 | goto err_busy; | |
286 | } | |
7768a13c | 287 | |
2817142f FB |
288 | wdev = kzalloc(sizeof(struct omap_wdt_dev), GFP_KERNEL); |
289 | if (!wdev) { | |
290 | ret = -ENOMEM; | |
b3112180 | 291 | goto err_kzalloc; |
2817142f | 292 | } |
b3112180 | 293 | |
2817142f FB |
294 | wdev->omap_wdt_users = 0; |
295 | wdev->mem = mem; | |
7768a13c | 296 | |
4c5e1946 RK |
297 | wdev->ick = clk_get(&pdev->dev, "ick"); |
298 | if (IS_ERR(wdev->ick)) { | |
299 | ret = PTR_ERR(wdev->ick); | |
300 | wdev->ick = NULL; | |
301 | goto err_clk; | |
7768a13c | 302 | } |
39a80c7f RK |
303 | wdev->fck = clk_get(&pdev->dev, "fck"); |
304 | if (IS_ERR(wdev->fck)) { | |
305 | ret = PTR_ERR(wdev->fck); | |
306 | wdev->fck = NULL; | |
307 | goto err_clk; | |
2817142f FB |
308 | } |
309 | ||
b782a563 | 310 | wdev->base = ioremap(res->start, resource_size(res)); |
9f69e3b0 FB |
311 | if (!wdev->base) { |
312 | ret = -ENOMEM; | |
b3112180 | 313 | goto err_ioremap; |
9f69e3b0 FB |
314 | } |
315 | ||
2817142f | 316 | platform_set_drvdata(pdev, wdev); |
7768a13c | 317 | |
789cd470 UBH |
318 | clk_enable(wdev->ick); |
319 | clk_enable(wdev->fck); | |
320 | ||
2817142f | 321 | omap_wdt_disable(wdev); |
7768a13c KS |
322 | omap_wdt_adjust_timeout(timer_margin); |
323 | ||
2817142f FB |
324 | wdev->omap_wdt_miscdev.parent = &pdev->dev; |
325 | wdev->omap_wdt_miscdev.minor = WATCHDOG_MINOR; | |
326 | wdev->omap_wdt_miscdev.name = "watchdog"; | |
327 | wdev->omap_wdt_miscdev.fops = &omap_wdt_fops; | |
328 | ||
329 | ret = misc_register(&(wdev->omap_wdt_miscdev)); | |
7768a13c | 330 | if (ret) |
b3112180 | 331 | goto err_misc; |
7768a13c | 332 | |
2817142f | 333 | pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n", |
9f69e3b0 | 334 | __raw_readl(wdev->base + OMAP_WATCHDOG_REV) & 0xFF, |
2817142f | 335 | timer_margin); |
7768a13c KS |
336 | |
337 | /* autogate OCP interface clock */ | |
9f69e3b0 | 338 | __raw_writel(0x01, wdev->base + OMAP_WATCHDOG_SYS_CONFIG); |
2817142f | 339 | |
789cd470 UBH |
340 | clk_disable(wdev->ick); |
341 | clk_disable(wdev->fck); | |
342 | ||
2817142f FB |
343 | omap_wdt_dev = pdev; |
344 | ||
7768a13c KS |
345 | return 0; |
346 | ||
b3112180 FB |
347 | err_misc: |
348 | platform_set_drvdata(pdev, NULL); | |
349 | iounmap(wdev->base); | |
350 | ||
351 | err_ioremap: | |
352 | wdev->base = NULL; | |
353 | ||
354 | err_clk: | |
39a80c7f RK |
355 | if (wdev->ick) |
356 | clk_put(wdev->ick); | |
357 | if (wdev->fck) | |
358 | clk_put(wdev->fck); | |
b3112180 FB |
359 | kfree(wdev); |
360 | ||
361 | err_kzalloc: | |
b782a563 | 362 | release_mem_region(res->start, resource_size(res)); |
b3112180 FB |
363 | |
364 | err_busy: | |
365 | err_get_resource: | |
366 | ||
7768a13c KS |
367 | return ret; |
368 | } | |
369 | ||
370 | static void omap_wdt_shutdown(struct platform_device *pdev) | |
371 | { | |
b3112180 | 372 | struct omap_wdt_dev *wdev = platform_get_drvdata(pdev); |
2817142f FB |
373 | |
374 | if (wdev->omap_wdt_users) | |
375 | omap_wdt_disable(wdev); | |
7768a13c KS |
376 | } |
377 | ||
0e3912c7 | 378 | static int __devexit omap_wdt_remove(struct platform_device *pdev) |
7768a13c | 379 | { |
b3112180 | 380 | struct omap_wdt_dev *wdev = platform_get_drvdata(pdev); |
2817142f FB |
381 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
382 | ||
383 | if (!res) | |
384 | return -ENOENT; | |
385 | ||
386 | misc_deregister(&(wdev->omap_wdt_miscdev)); | |
b782a563 | 387 | release_mem_region(res->start, resource_size(res)); |
2817142f | 388 | platform_set_drvdata(pdev, NULL); |
b3112180 | 389 | |
4c5e1946 | 390 | clk_put(wdev->ick); |
39a80c7f | 391 | clk_put(wdev->fck); |
9f69e3b0 FB |
392 | iounmap(wdev->base); |
393 | ||
2817142f FB |
394 | kfree(wdev); |
395 | omap_wdt_dev = NULL; | |
b3112180 | 396 | |
7768a13c KS |
397 | return 0; |
398 | } | |
399 | ||
400 | #ifdef CONFIG_PM | |
401 | ||
402 | /* REVISIT ... not clear this is the best way to handle system suspend; and | |
403 | * it's very inappropriate for selective device suspend (e.g. suspending this | |
404 | * through sysfs rather than by stopping the watchdog daemon). Also, this | |
405 | * may not play well enough with NOWAYOUT... | |
406 | */ | |
407 | ||
408 | static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state) | |
409 | { | |
b3112180 FB |
410 | struct omap_wdt_dev *wdev = platform_get_drvdata(pdev); |
411 | ||
2817142f FB |
412 | if (wdev->omap_wdt_users) |
413 | omap_wdt_disable(wdev); | |
b3112180 | 414 | |
7768a13c KS |
415 | return 0; |
416 | } | |
417 | ||
418 | static int omap_wdt_resume(struct platform_device *pdev) | |
419 | { | |
b3112180 FB |
420 | struct omap_wdt_dev *wdev = platform_get_drvdata(pdev); |
421 | ||
2817142f FB |
422 | if (wdev->omap_wdt_users) { |
423 | omap_wdt_enable(wdev); | |
424 | omap_wdt_ping(wdev); | |
7768a13c | 425 | } |
b3112180 | 426 | |
7768a13c KS |
427 | return 0; |
428 | } | |
429 | ||
430 | #else | |
431 | #define omap_wdt_suspend NULL | |
432 | #define omap_wdt_resume NULL | |
433 | #endif | |
434 | ||
435 | static struct platform_driver omap_wdt_driver = { | |
436 | .probe = omap_wdt_probe, | |
0e3912c7 | 437 | .remove = __devexit_p(omap_wdt_remove), |
7768a13c KS |
438 | .shutdown = omap_wdt_shutdown, |
439 | .suspend = omap_wdt_suspend, | |
440 | .resume = omap_wdt_resume, | |
441 | .driver = { | |
442 | .owner = THIS_MODULE, | |
443 | .name = "omap_wdt", | |
444 | }, | |
445 | }; | |
446 | ||
447 | static int __init omap_wdt_init(void) | |
448 | { | |
12b9df7d | 449 | spin_lock_init(&wdt_lock); |
7768a13c KS |
450 | return platform_driver_register(&omap_wdt_driver); |
451 | } | |
452 | ||
453 | static void __exit omap_wdt_exit(void) | |
454 | { | |
455 | platform_driver_unregister(&omap_wdt_driver); | |
456 | } | |
457 | ||
458 | module_init(omap_wdt_init); | |
459 | module_exit(omap_wdt_exit); | |
460 | ||
461 | MODULE_AUTHOR("George G. Davis"); | |
462 | MODULE_LICENSE("GPL"); | |
463 | MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); | |
f37d193c | 464 | MODULE_ALIAS("platform:omap_wdt"); |