[deliverable/linux.git] / drivers / watchdog / omap_wdt.c

/*
 * linux/drivers/char/watchdog/omap_wdt.c
 *
 * Watchdog driver for the TI OMAP 16xx & 24xx 32KHz (non-secure) watchdog
 *
 * Author: MontaVista Software, Inc.
 *	 <gdavis@mvista.com> or <source@mvista.com>
 *
 * 2003 (c) MontaVista Software, Inc. This file is licensed under the
 * terms of the GNU General Public License version 2. This program is
 * licensed "as is" without any warranty of any kind, whether express
 * or implied.
 *
 * History:
 *
 * 20030527: George G. Davis <gdavis@mvista.com>
 *	Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
 *	(c) Copyright 2000 Oleg Drokin <green@crimea.edu>
 *	Based on SoftDog driver by Alan Cox <alan@redhat.com>
 *
 * Copyright (c) 2004 Texas Instruments.
 *	1. Modified to support OMAP1610 32-KHz watchdog timer
 *	2. Ported to 2.6 kernel
 *
 * Copyright (c) 2005 David Brownell
 *	Use the driver model and standard identifiers; handle bigger timeouts.
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/fs.h>
#include <linux/mm.h>
#include <linux/miscdevice.h>
#include <linux/watchdog.h>
#include <linux/reboot.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/moduleparam.h>
#include <linux/clk.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/uaccess.h>
#include <linux/hardware.h>

#include <asm/arch/prcm.h>

#include "omap_wdt.h"

static unsigned timer_margin;
module_param(timer_margin, uint, 0);
MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");

static int omap_wdt_users;
static struct clk *armwdt_ck;
static struct clk *mpu_wdt_ick;
static struct clk *mpu_wdt_fck;

static unsigned int wdt_trgr_pattern = 0x1234;
static spinlock_t wdt_lock;

static void omap_wdt_ping(void)
{
	/* wait for posted write to complete */
	while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x08)
		cpu_relax();
	wdt_trgr_pattern = ~wdt_trgr_pattern;
	omap_writel(wdt_trgr_pattern, (OMAP_WATCHDOG_TGR));
	/* wait for posted write to complete */
	while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x08)
		cpu_relax();
	/* reloaded WCRR from WLDR */
}

static void omap_wdt_enable(void)
{
	/* Sequence to enable the watchdog */
	omap_writel(0xBBBB, OMAP_WATCHDOG_SPR);
	while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x10)
		cpu_relax();
	omap_writel(0x4444, OMAP_WATCHDOG_SPR);
	while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x10)
		cpu_relax();
}

static void omap_wdt_disable(void)
{
	/* sequence required to disable watchdog */
	omap_writel(0xAAAA, OMAP_WATCHDOG_SPR);	/* TIMER_MODE */
	while (omap_readl(OMAP_WATCHDOG_WPS) & 0x10)
		cpu_relax();
	omap_writel(0x5555, OMAP_WATCHDOG_SPR);	/* TIMER_MODE */
	while (omap_readl(OMAP_WATCHDOG_WPS) & 0x10)
		cpu_relax();
}

static void omap_wdt_adjust_timeout(unsigned new_timeout)
{
	if (new_timeout < TIMER_MARGIN_MIN)
		new_timeout = TIMER_MARGIN_DEFAULT;
	if (new_timeout > TIMER_MARGIN_MAX)
		new_timeout = TIMER_MARGIN_MAX;
	timer_margin = new_timeout;
}

static void omap_wdt_set_timeout(void)
{
	u32 pre_margin = GET_WLDR_VAL(timer_margin);

	/* just count up at 32 KHz */
	while (omap_readl(OMAP_WATCHDOG_WPS) & 0x04)
		cpu_relax();
	omap_writel(pre_margin, OMAP_WATCHDOG_LDR);
	while (omap_readl(OMAP_WATCHDOG_WPS) & 0x04)
		cpu_relax();
}

/*
 *	Allow only one task to hold it open
 */

static int omap_wdt_open(struct inode *inode, struct file *file)
{
	if (test_and_set_bit(1, (unsigned long *)&omap_wdt_users))
		return -EBUSY;

	if (cpu_is_omap16xx())
		clk_enable(armwdt_ck);	/* Enable the clock */

	if (cpu_is_omap24xx()) {
		clk_enable(mpu_wdt_ick);    /* Enable the interface clock */
		clk_enable(mpu_wdt_fck);    /* Enable the functional clock */
	}

	/* initialize prescaler */
	while (omap_readl(OMAP_WATCHDOG_WPS) & 0x01)
		cpu_relax();
	omap_writel((1 << 5) | (PTV << 2), OMAP_WATCHDOG_CNTRL);
	while (omap_readl(OMAP_WATCHDOG_WPS) & 0x01)
		cpu_relax();

	omap_wdt_set_timeout();
	omap_wdt_enable();
	return nonseekable_open(inode, file);
}

static int omap_wdt_release(struct inode *inode, struct file *file)
{
	/*
	 *      Shut off the timer unless NOWAYOUT is defined.
	 */
#ifndef CONFIG_WATCHDOG_NOWAYOUT
	omap_wdt_disable();

	if (cpu_is_omap16xx()) {
		clk_disable(armwdt_ck);	/* Disable the clock */
		clk_put(armwdt_ck);
		armwdt_ck = NULL;
	}

	if (cpu_is_omap24xx()) {
		clk_disable(mpu_wdt_ick);	/* Disable the clock */
		clk_disable(mpu_wdt_fck);	/* Disable the clock */
		clk_put(mpu_wdt_ick);
		clk_put(mpu_wdt_fck);
		mpu_wdt_ick = NULL;
		mpu_wdt_fck = NULL;
	}
#else
	printk(KERN_CRIT "omap_wdt: Unexpected close, not stopping!\n");
#endif
	omap_wdt_users = 0;
	return 0;
}

static ssize_t omap_wdt_write(struct file *file, const char __user *data,
		size_t len, loff_t *ppos)
{
	/* Refresh LOAD_TIME. */
	if (len) {
		spin_lock(&wdt_lock);
		omap_wdt_ping();
		spin_unlock(&wdt_lock);
	}
	return len;
}

static long omap_wdt_ioctl(struct file *file, unsigned int cmd,
						unsigned long arg)
{
	int new_margin;
	static const struct watchdog_info ident = {
		.identity = "OMAP Watchdog",
		.options = WDIOF_SETTIMEOUT,
		.firmware_version = 0,
	};

	switch (cmd) {
	case WDIOC_GETSUPPORT:
		return copy_to_user((struct watchdog_info __user *)arg, &ident,
				sizeof(ident));
	case WDIOC_GETSTATUS:
		return put_user(0, (int __user *)arg);
	case WDIOC_GETBOOTSTATUS:
		if (cpu_is_omap16xx())
			return put_user(omap_readw(ARM_SYSST),
					(int __user *)arg);
		if (cpu_is_omap24xx())
			return put_user(omap_prcm_get_reset_sources(),
					(int __user *)arg);
	case WDIOC_KEEPALIVE:
		spin_lock(&wdt_lock);
		omap_wdt_ping();
		spin_unlock(&wdt_lock);
		return 0;
	case WDIOC_SETTIMEOUT:
		if (get_user(new_margin, (int __user *)arg))
			return -EFAULT;
		omap_wdt_adjust_timeout(new_margin);

		spin_lock(&wdt_lock);
		omap_wdt_disable();
		omap_wdt_set_timeout();
		omap_wdt_enable();

		omap_wdt_ping();
		spin_unlock(&wdt_lock);
		/* Fall */
	case WDIOC_GETTIMEOUT:
		return put_user(timer_margin, (int __user *)arg);
	default:
		return -ENOTTY;
	}
}

static const struct file_operations omap_wdt_fops = {
	.owner = THIS_MODULE,
	.write = omap_wdt_write,
	.unlocked_ioctl = omap_wdt_ioctl,
	.open = omap_wdt_open,
	.release = omap_wdt_release,
};

static struct miscdevice omap_wdt_miscdev = {
	.minor = WATCHDOG_MINOR,
	.name = "watchdog",
	.fops = &omap_wdt_fops
};

static int __init omap_wdt_probe(struct platform_device *pdev)
{
	struct resource *res, *mem;
	int ret;

	/* reserve static register mappings */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res)
		return -ENOENT;

	mem = request_mem_region(res->start, res->end - res->start + 1,
				 pdev->name);
	if (mem == NULL)
		return -EBUSY;

	platform_set_drvdata(pdev, mem);

	omap_wdt_users = 0;

	if (cpu_is_omap16xx()) {
		armwdt_ck = clk_get(&pdev->dev, "armwdt_ck");
		if (IS_ERR(armwdt_ck)) {
			ret = PTR_ERR(armwdt_ck);
			armwdt_ck = NULL;
			goto fail;
		}
	}

	if (cpu_is_omap24xx()) {
		mpu_wdt_ick = clk_get(&pdev->dev, "mpu_wdt_ick");
		if (IS_ERR(mpu_wdt_ick)) {
			ret = PTR_ERR(mpu_wdt_ick);
			mpu_wdt_ick = NULL;
			goto fail;
		}
		mpu_wdt_fck = clk_get(&pdev->dev, "mpu_wdt_fck");
		if (IS_ERR(mpu_wdt_fck)) {
			ret = PTR_ERR(mpu_wdt_fck);
			mpu_wdt_fck = NULL;
			goto fail;
		}
	}

	omap_wdt_disable();
	omap_wdt_adjust_timeout(timer_margin);

	omap_wdt_miscdev.parent = &pdev->dev;
	ret = misc_register(&omap_wdt_miscdev);
	if (ret)
		goto fail;

	pr_info("OMAP Watchdog Timer: initial timeout %d sec\n", timer_margin);

	/* autogate OCP interface clock */
	omap_writel(0x01, OMAP_WATCHDOG_SYS_CONFIG);
	return 0;

fail:
	if (armwdt_ck)
		clk_put(armwdt_ck);
	if (mpu_wdt_ick)
		clk_put(mpu_wdt_ick);
	if (mpu_wdt_fck)
		clk_put(mpu_wdt_fck);
	release_resource(mem);
	return ret;
}

static void omap_wdt_shutdown(struct platform_device *pdev)
{
	omap_wdt_disable();
}

static int omap_wdt_remove(struct platform_device *pdev)
{
	struct resource *mem = platform_get_drvdata(pdev);
	misc_deregister(&omap_wdt_miscdev);
	release_resource(mem);
	if (armwdt_ck)
		clk_put(armwdt_ck);
	if (mpu_wdt_ick)
		clk_put(mpu_wdt_ick);
	if (mpu_wdt_fck)
		clk_put(mpu_wdt_fck);
	return 0;
}

#ifdef	CONFIG_PM

/* REVISIT ... not clear this is the best way to handle system suspend; and
 * it's very inappropriate for selective device suspend (e.g. suspending this
 * through sysfs rather than by stopping the watchdog daemon).  Also, this
 * may not play well enough with NOWAYOUT...
 */

static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
{
	if (omap_wdt_users)
		omap_wdt_disable();
	return 0;
}

static int omap_wdt_resume(struct platform_device *pdev)
{
	if (omap_wdt_users) {
		omap_wdt_enable();
		omap_wdt_ping();
	}
	return 0;
}

#else
#define	omap_wdt_suspend	NULL
#define	omap_wdt_resume		NULL
#endif

static struct platform_driver omap_wdt_driver = {
	.probe		= omap_wdt_probe,
	.remove		= omap_wdt_remove,
	.shutdown	= omap_wdt_shutdown,
	.suspend	= omap_wdt_suspend,
	.resume		= omap_wdt_resume,
	.driver		= {
		.owner	= THIS_MODULE,
		.name	= "omap_wdt",
	},
};

static int __init omap_wdt_init(void)
{
	spin_lock_init(&wdt_lock);
	return platform_driver_register(&omap_wdt_driver);
}

static void __exit omap_wdt_exit(void)
{
	platform_driver_unregister(&omap_wdt_driver);
}

module_init(omap_wdt_init);
module_exit(omap_wdt_exit);

MODULE_AUTHOR("George G. Davis");
MODULE_LICENSE("GPL");
MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
MODULE_ALIAS("platform:omap_wdt");
Commit	Line	Data
7768a13c KS	1	/*
	2	* linux/drivers/char/watchdog/omap_wdt.c
	3	*
	4	* Watchdog driver for the TI OMAP 16xx & 24xx 32KHz (non-secure) watchdog
	5	*
	6	* Author: MontaVista Software, Inc.
	7	* <gdavis@mvista.com> or <source@mvista.com>
	8	*
	9	* 2003 (c) MontaVista Software, Inc. This file is licensed under the
	10	* terms of the GNU General Public License version 2. This program is
	11	* licensed "as is" without any warranty of any kind, whether express
	12	* or implied.
	13	*
	14	* History:
	15	*
	16	* 20030527: George G. Davis <gdavis@mvista.com>
	17	* Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
	18	* (c) Copyright 2000 Oleg Drokin <green@crimea.edu>
	19	* Based on SoftDog driver by Alan Cox <alan@redhat.com>
	20	*
	21	* Copyright (c) 2004 Texas Instruments.
	22	* 1. Modified to support OMAP1610 32-KHz watchdog timer
	23	* 2. Ported to 2.6 kernel
	24	*
	25	* Copyright (c) 2005 David Brownell
	26	* Use the driver model and standard identifiers; handle bigger timeouts.
	27	*/
	28
	29	#include <linux/module.h>
7768a13c KS	30	#include <linux/types.h>
	31	#include <linux/kernel.h>
	32	#include <linux/fs.h>
	33	#include <linux/mm.h>
	34	#include <linux/miscdevice.h>
	35	#include <linux/watchdog.h>
	36	#include <linux/reboot.h>
7768a13c KS	37	#include <linux/init.h>
	38	#include <linux/err.h>
	39	#include <linux/platform_device.h>
	40	#include <linux/moduleparam.h>
	41	#include <linux/clk.h>
1977f032	42	#include <linux/bitops.h>
089ab079	43	#include <linux/io.h>
12b9df7d AC	44	#include <linux/uaccess.h>
12b9df7d AC	45	#include <linux/hardware.h>
7768a13c KS	46
	47	#include <asm/arch/prcm.h>
	48
	49	#include "omap_wdt.h"
	50
	51	static unsigned timer_margin;
	52	module_param(timer_margin, uint, 0);
	53	MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");
	54
	55	static int omap_wdt_users;
12b9df7d AC	56	static struct clk *armwdt_ck;
	57	static struct clk *mpu_wdt_ick;
	58	static struct clk *mpu_wdt_fck;
7768a13c KS	59
7768a13c KS	60	static unsigned int wdt_trgr_pattern = 0x1234;
12b9df7d	61	static spinlock_t wdt_lock;
7768a13c KS	62
	63	static void omap_wdt_ping(void)
	64	{
	65	/* wait for posted write to complete */
	66	while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x08)
	67	cpu_relax();
	68	wdt_trgr_pattern = ~wdt_trgr_pattern;
	69	omap_writel(wdt_trgr_pattern, (OMAP_WATCHDOG_TGR));
	70	/* wait for posted write to complete */
	71	while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x08)
	72	cpu_relax();
	73	/* reloaded WCRR from WLDR */
	74	}
	75
	76	static void omap_wdt_enable(void)
	77	{
	78	/* Sequence to enable the watchdog */
	79	omap_writel(0xBBBB, OMAP_WATCHDOG_SPR);
	80	while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x10)
	81	cpu_relax();
	82	omap_writel(0x4444, OMAP_WATCHDOG_SPR);
	83	while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x10)
	84	cpu_relax();
	85	}
	86
	87	static void omap_wdt_disable(void)
	88	{
	89	/* sequence required to disable watchdog */
	90	omap_writel(0xAAAA, OMAP_WATCHDOG_SPR); /* TIMER_MODE */
	91	while (omap_readl(OMAP_WATCHDOG_WPS) & 0x10)
	92	cpu_relax();
	93	omap_writel(0x5555, OMAP_WATCHDOG_SPR); /* TIMER_MODE */
	94	while (omap_readl(OMAP_WATCHDOG_WPS) & 0x10)
	95	cpu_relax();
	96	}
	97
	98	static void omap_wdt_adjust_timeout(unsigned new_timeout)
	99	{
	100	if (new_timeout < TIMER_MARGIN_MIN)
	101	new_timeout = TIMER_MARGIN_DEFAULT;
	102	if (new_timeout > TIMER_MARGIN_MAX)
	103	new_timeout = TIMER_MARGIN_MAX;
	104	timer_margin = new_timeout;
	105	}
	106
	107	static void omap_wdt_set_timeout(void)
	108	{
	109	u32 pre_margin = GET_WLDR_VAL(timer_margin);
	110
	111	/* just count up at 32 KHz */
	112	while (omap_readl(OMAP_WATCHDOG_WPS) & 0x04)
	113	cpu_relax();
	114	omap_writel(pre_margin, OMAP_WATCHDOG_LDR);
	115	while (omap_readl(OMAP_WATCHDOG_WPS) & 0x04)
	116	cpu_relax();
	117	}
	118
	119	/*
	120	* Allow only one task to hold it open
	121	*/
	122
	123	static int omap_wdt_open(struct inode inode, struct file file)
	124	{
	125	if (test_and_set_bit(1, (unsigned long *)&omap_wdt_users))
126	return -EBUSY;
127
128	if (cpu_is_omap16xx())
129	clk_enable(armwdt_ck); /* Enable the clock */
130
131	if (cpu_is_omap24xx()) {
132	clk_enable(mpu_wdt_ick); /* Enable the interface clock */
133	clk_enable(mpu_wdt_fck); /* Enable the functional clock */
134	}
135
136	/* initialize prescaler */
137	while (omap_readl(OMAP_WATCHDOG_WPS) & 0x01)
138	cpu_relax();
139	omap_writel((1 << 5) \| (PTV << 2), OMAP_WATCHDOG_CNTRL);
140	while (omap_readl(OMAP_WATCHDOG_WPS) & 0x01)
141	cpu_relax();
142
143	omap_wdt_set_timeout();
144	omap_wdt_enable();
ec9505a7	145	return nonseekable_open(inode, file);
7768a13c KS	146	}
	147
	148	static int omap_wdt_release(struct inode inode, struct file file)
	149	{
	150	/*
	151	* Shut off the timer unless NOWAYOUT is defined.
	152	*/
	153	#ifndef CONFIG_WATCHDOG_NOWAYOUT
	154	omap_wdt_disable();
	155
	156	if (cpu_is_omap16xx()) {
	157	clk_disable(armwdt_ck); /* Disable the clock */
	158	clk_put(armwdt_ck);
	159	armwdt_ck = NULL;
	160	}
	161
	162	if (cpu_is_omap24xx()) {
	163	clk_disable(mpu_wdt_ick); /* Disable the clock */
	164	clk_disable(mpu_wdt_fck); /* Disable the clock */
	165	clk_put(mpu_wdt_ick);
	166	clk_put(mpu_wdt_fck);
	167	mpu_wdt_ick = NULL;
	168	mpu_wdt_fck = NULL;
	169	}
	170	#else
	171	printk(KERN_CRIT "omap_wdt: Unexpected close, not stopping!\n");
	172	#endif
	173	omap_wdt_users = 0;
	174	return 0;
	175	}
	176
12b9df7d	177	static ssize_t omap_wdt_write(struct file file, const char __user data,
7768a13c KS	178	size_t len, loff_t *ppos)
	179	{
	180	/* Refresh LOAD_TIME. */
12b9df7d AC	181	if (len) {
12b9df7d AC	182	spin_lock(&wdt_lock);
7768a13c	183	omap_wdt_ping();
12b9df7d AC	184	spin_unlock(&wdt_lock);
12b9df7d AC	185	}
7768a13c KS	186	return len;
	187	}
	188
12b9df7d AC	189	static long omap_wdt_ioctl(struct file *file, unsigned int cmd,
12b9df7d AC	190	unsigned long arg)
7768a13c KS	191	{
7768a13c KS	192	int new_margin;
12b9df7d	193	static const struct watchdog_info ident = {
7768a13c KS	194	.identity = "OMAP Watchdog",
	195	.options = WDIOF_SETTIMEOUT,
	196	.firmware_version = 0,
	197	};
	198
	199	switch (cmd) {
7768a13c KS	200	case WDIOC_GETSUPPORT:
	201	return copy_to_user((struct watchdog_info __user *)arg, &ident,
	202	sizeof(ident));
	203	case WDIOC_GETSTATUS:
	204	return put_user(0, (int __user *)arg);
	205	case WDIOC_GETBOOTSTATUS:
	206	if (cpu_is_omap16xx())
	207	return put_user(omap_readw(ARM_SYSST),
	208	(int __user *)arg);
	209	if (cpu_is_omap24xx())
	210	return put_user(omap_prcm_get_reset_sources(),
	211	(int __user *)arg);
	212	case WDIOC_KEEPALIVE:
12b9df7d	213	spin_lock(&wdt_lock);
7768a13c	214	omap_wdt_ping();
12b9df7d	215	spin_unlock(&wdt_lock);
7768a13c KS	216	return 0;
	217	case WDIOC_SETTIMEOUT:
	218	if (get_user(new_margin, (int __user *)arg))
	219	return -EFAULT;
	220	omap_wdt_adjust_timeout(new_margin);
	221
12b9df7d	222	spin_lock(&wdt_lock);
7768a13c KS	223	omap_wdt_disable();
	224	omap_wdt_set_timeout();
	225	omap_wdt_enable();
	226
	227	omap_wdt_ping();
12b9df7d	228	spin_unlock(&wdt_lock);
7768a13c KS	229	/* Fall */
	230	case WDIOC_GETTIMEOUT:
	231	return put_user(timer_margin, (int __user *)arg);
0c06090c WVS	232	default:
0c06090c WVS	233	return -ENOTTY;
7768a13c KS	234	}
	235	}
	236
2b8693c0	237	static const struct file_operations omap_wdt_fops = {
7768a13c KS	238	.owner = THIS_MODULE,
7768a13c KS	239	.write = omap_wdt_write,
12b9df7d	240	.unlocked_ioctl = omap_wdt_ioctl,
7768a13c KS	241	.open = omap_wdt_open,
	242	.release = omap_wdt_release,
	243	};
	244
	245	static struct miscdevice omap_wdt_miscdev = {
	246	.minor = WATCHDOG_MINOR,
	247	.name = "watchdog",
	248	.fops = &omap_wdt_fops
	249	};
	250
	251	static int __init omap_wdt_probe(struct platform_device *pdev)
	252	{
	253	struct resource res, mem;
	254	int ret;
	255
	256	/* reserve static register mappings */
	257	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	258	if (!res)
	259	return -ENOENT;
	260
	261	mem = request_mem_region(res->start, res->end - res->start + 1,
	262	pdev->name);
	263	if (mem == NULL)
	264	return -EBUSY;
	265
	266	platform_set_drvdata(pdev, mem);
	267
	268	omap_wdt_users = 0;
	269
	270	if (cpu_is_omap16xx()) {
	271	armwdt_ck = clk_get(&pdev->dev, "armwdt_ck");
	272	if (IS_ERR(armwdt_ck)) {
	273	ret = PTR_ERR(armwdt_ck);
	274	armwdt_ck = NULL;
	275	goto fail;
	276	}
	277	}
	278
	279	if (cpu_is_omap24xx()) {
	280	mpu_wdt_ick = clk_get(&pdev->dev, "mpu_wdt_ick");
	281	if (IS_ERR(mpu_wdt_ick)) {
	282	ret = PTR_ERR(mpu_wdt_ick);
	283	mpu_wdt_ick = NULL;
	284	goto fail;
	285	}
	286	mpu_wdt_fck = clk_get(&pdev->dev, "mpu_wdt_fck");
	287	if (IS_ERR(mpu_wdt_fck)) {
	288	ret = PTR_ERR(mpu_wdt_fck);
	289	mpu_wdt_fck = NULL;
	290	goto fail;
	291	}
	292	}
	293
	294	omap_wdt_disable();
	295	omap_wdt_adjust_timeout(timer_margin);
	296
e0b79e0b	297	omap_wdt_miscdev.parent = &pdev->dev;
7768a13c KS	298	ret = misc_register(&omap_wdt_miscdev);
	299	if (ret)
	300	goto fail;
	301
	302	pr_info("OMAP Watchdog Timer: initial timeout %d sec\n", timer_margin);
	303
	304	/* autogate OCP interface clock */
	305	omap_writel(0x01, OMAP_WATCHDOG_SYS_CONFIG);
	306	return 0;
	307
	308	fail:
	309	if (armwdt_ck)
	310	clk_put(armwdt_ck);
	311	if (mpu_wdt_ick)
	312	clk_put(mpu_wdt_ick);
	313	if (mpu_wdt_fck)
	314	clk_put(mpu_wdt_fck);
	315	release_resource(mem);
	316	return ret;
	317	}
	318
	319	static void omap_wdt_shutdown(struct platform_device *pdev)
	320	{
	321	omap_wdt_disable();
	322	}
	323
	324	static int omap_wdt_remove(struct platform_device *pdev)
	325	{
	326	struct resource *mem = platform_get_drvdata(pdev);
	327	misc_deregister(&omap_wdt_miscdev);
	328	release_resource(mem);
	329	if (armwdt_ck)
	330	clk_put(armwdt_ck);
	331	if (mpu_wdt_ick)
	332	clk_put(mpu_wdt_ick);
	333	if (mpu_wdt_fck)
	334	clk_put(mpu_wdt_fck);
	335	return 0;
	336	}
	337
	338	#ifdef CONFIG_PM
	339
	340	/* REVISIT ... not clear this is the best way to handle system suspend; and
	341	* it's very inappropriate for selective device suspend (e.g. suspending this
	342	* through sysfs rather than by stopping the watchdog daemon). Also, this
	343	* may not play well enough with NOWAYOUT...
	344	*/
	345
	346	static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
	347	{
	348	if (omap_wdt_users)
	349	omap_wdt_disable();
	350	return 0;
	351	}
	352
	353	static int omap_wdt_resume(struct platform_device *pdev)
	354	{
	355	if (omap_wdt_users) {
	356	omap_wdt_enable();
	357	omap_wdt_ping();
	358	}
	359	return 0;
	360	}
	361
362	#else
363	#define omap_wdt_suspend NULL
364	#define omap_wdt_resume NULL
365	#endif
366
367	static struct platform_driver omap_wdt_driver = {
368	.probe = omap_wdt_probe,
369	.remove = omap_wdt_remove,
370	.shutdown = omap_wdt_shutdown,
371	.suspend = omap_wdt_suspend,
372	.resume = omap_wdt_resume,
373	.driver = {
374	.owner = THIS_MODULE,
375	.name = "omap_wdt",
376	},
377	};
378
379	static int __init omap_wdt_init(void)
380	{
12b9df7d	381	spin_lock_init(&wdt_lock);
7768a13c KS	382	return platform_driver_register(&omap_wdt_driver);
	383	}
	384
	385	static void __exit omap_wdt_exit(void)
	386	{
	387	platform_driver_unregister(&omap_wdt_driver);
	388	}
	389
	390	module_init(omap_wdt_init);
	391	module_exit(omap_wdt_exit);
	392
	393	MODULE_AUTHOR("George G. Davis");
	394	MODULE_LICENSE("GPL");
	395	MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
f37d193c	396	MODULE_ALIAS("platform:omap_wdt");