watchdog: gpio_wdt: Add option for early registration
[deliverable/linux.git] / drivers / watchdog / omap_wdt.c
CommitLineData
7768a13c 1/*
2817142f 2 * omap_wdt.c
7768a13c 3 *
2817142f 4 * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
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5 *
6 * Author: MontaVista Software, Inc.
7 * <gdavis@mvista.com> or <source@mvista.com>
8 *
9 * 2003 (c) MontaVista Software, Inc. This file is licensed under the
10 * terms of the GNU General Public License version 2. This program is
11 * licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 *
14 * History:
15 *
16 * 20030527: George G. Davis <gdavis@mvista.com>
17 * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
18 * (c) Copyright 2000 Oleg Drokin <green@crimea.edu>
29fa0586 19 * Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk>
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20 *
21 * Copyright (c) 2004 Texas Instruments.
22 * 1. Modified to support OMAP1610 32-KHz watchdog timer
23 * 2. Ported to 2.6 kernel
24 *
25 * Copyright (c) 2005 David Brownell
26 * Use the driver model and standard identifiers; handle bigger timeouts.
27 */
28
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29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
7768a13c 31#include <linux/module.h>
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32#include <linux/types.h>
33#include <linux/kernel.h>
7768a13c 34#include <linux/mm.h>
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35#include <linux/watchdog.h>
36#include <linux/reboot.h>
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37#include <linux/err.h>
38#include <linux/platform_device.h>
39#include <linux/moduleparam.h>
089ab079 40#include <linux/io.h>
5a0e3ad6 41#include <linux/slab.h>
7ec5ad0f 42#include <linux/pm_runtime.h>
129f5577 43#include <linux/platform_data/omap-wd-timer.h>
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44
45#include "omap_wdt.h"
46
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47static bool nowayout = WATCHDOG_NOWAYOUT;
48module_param(nowayout, bool, 0);
49MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
50 "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
51
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52static unsigned timer_margin;
53module_param(timer_margin, uint, 0);
54MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");
55
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56#define to_omap_wdt_dev(_wdog) container_of(_wdog, struct omap_wdt_dev, wdog)
57
2817142f 58struct omap_wdt_dev {
d2f78268 59 struct watchdog_device wdog;
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60 void __iomem *base; /* physical */
61 struct device *dev;
67c0f554 62 bool omap_wdt_users;
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63 int wdt_trgr_pattern;
64 struct mutex lock; /* to avoid races with PM */
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65};
66
67c0f554 67static void omap_wdt_reload(struct omap_wdt_dev *wdev)
7768a13c 68{
2817142f 69 void __iomem *base = wdev->base;
b3112180 70
7768a13c 71 /* wait for posted write to complete */
4a7e94a0 72 while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08)
7768a13c 73 cpu_relax();
b3112180 74
67c0f554 75 wdev->wdt_trgr_pattern = ~wdev->wdt_trgr_pattern;
4a7e94a0 76 writel_relaxed(wdev->wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR));
b3112180 77
7768a13c 78 /* wait for posted write to complete */
4a7e94a0 79 while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08)
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80 cpu_relax();
81 /* reloaded WCRR from WLDR */
82}
83
2817142f 84static void omap_wdt_enable(struct omap_wdt_dev *wdev)
7768a13c 85{
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86 void __iomem *base = wdev->base;
87
7768a13c 88 /* Sequence to enable the watchdog */
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89 writel_relaxed(0xBBBB, base + OMAP_WATCHDOG_SPR);
90 while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10)
7768a13c 91 cpu_relax();
b3112180 92
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93 writel_relaxed(0x4444, base + OMAP_WATCHDOG_SPR);
94 while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10)
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95 cpu_relax();
96}
97
2817142f 98static void omap_wdt_disable(struct omap_wdt_dev *wdev)
7768a13c 99{
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100 void __iomem *base = wdev->base;
101
7768a13c 102 /* sequence required to disable watchdog */
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103 writel_relaxed(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
104 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10)
7768a13c 105 cpu_relax();
b3112180 106
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107 writel_relaxed(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
108 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10)
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109 cpu_relax();
110}
111
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112static void omap_wdt_set_timer(struct omap_wdt_dev *wdev,
113 unsigned int timeout)
7768a13c 114{
67c0f554 115 u32 pre_margin = GET_WLDR_VAL(timeout);
b3112180 116 void __iomem *base = wdev->base;
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117
118 /* just count up at 32 KHz */
4a7e94a0 119 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04)
7768a13c 120 cpu_relax();
b3112180 121
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122 writel_relaxed(pre_margin, base + OMAP_WATCHDOG_LDR);
123 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04)
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124 cpu_relax();
125}
126
67c0f554 127static int omap_wdt_start(struct watchdog_device *wdog)
7768a13c 128{
d2f78268 129 struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
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130 void __iomem *base = wdev->base;
131
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132 mutex_lock(&wdev->lock);
133
134 wdev->omap_wdt_users = true;
7768a13c 135
7ec5ad0f 136 pm_runtime_get_sync(wdev->dev);
7768a13c 137
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138 /*
139 * Make sure the watchdog is disabled. This is unfortunately required
140 * because writing to various registers with the watchdog running has no
141 * effect.
142 */
143 omap_wdt_disable(wdev);
144
7768a13c 145 /* initialize prescaler */
4a7e94a0 146 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01)
7768a13c 147 cpu_relax();
b3112180 148
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149 writel_relaxed((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL);
150 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01)
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151 cpu_relax();
152
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153 omap_wdt_set_timer(wdev, wdog->timeout);
154 omap_wdt_reload(wdev); /* trigger loading of new timeout value */
2817142f 155 omap_wdt_enable(wdev);
b3112180 156
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157 mutex_unlock(&wdev->lock);
158
159 return 0;
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160}
161
67c0f554 162static int omap_wdt_stop(struct watchdog_device *wdog)
7768a13c 163{
d2f78268 164 struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
b3112180 165
67c0f554 166 mutex_lock(&wdev->lock);
2817142f 167 omap_wdt_disable(wdev);
7ec5ad0f 168 pm_runtime_put_sync(wdev->dev);
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169 wdev->omap_wdt_users = false;
170 mutex_unlock(&wdev->lock);
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171 return 0;
172}
173
67c0f554 174static int omap_wdt_ping(struct watchdog_device *wdog)
7768a13c 175{
d2f78268 176 struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
b3112180 177
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178 mutex_lock(&wdev->lock);
179 omap_wdt_reload(wdev);
180 mutex_unlock(&wdev->lock);
181
182 return 0;
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183}
184
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185static int omap_wdt_set_timeout(struct watchdog_device *wdog,
186 unsigned int timeout)
7768a13c 187{
d2f78268 188 struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
7768a13c 189
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190 mutex_lock(&wdev->lock);
191 omap_wdt_disable(wdev);
192 omap_wdt_set_timer(wdev, timeout);
193 omap_wdt_enable(wdev);
194 omap_wdt_reload(wdev);
195 wdog->timeout = timeout;
196 mutex_unlock(&wdev->lock);
197
198 return 0;
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199}
200
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201static unsigned int omap_wdt_get_timeleft(struct watchdog_device *wdog)
202{
203 struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog);
204 void __iomem *base = wdev->base;
205 u32 value;
206
207 value = readl_relaxed(base + OMAP_WATCHDOG_CRR);
208 return GET_WCCR_SECS(value);
209}
210
67c0f554 211static const struct watchdog_info omap_wdt_info = {
fb1cbeae 212 .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING,
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213 .identity = "OMAP Watchdog",
214};
215
216static const struct watchdog_ops omap_wdt_ops = {
217 .owner = THIS_MODULE,
218 .start = omap_wdt_start,
219 .stop = omap_wdt_stop,
220 .ping = omap_wdt_ping,
221 .set_timeout = omap_wdt_set_timeout,
452fafed 222 .get_timeleft = omap_wdt_get_timeleft,
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223};
224
2d991a16 225static int omap_wdt_probe(struct platform_device *pdev)
7768a13c 226{
bc8fdfbe 227 struct omap_wd_timer_platform_data *pdata = dev_get_platdata(&pdev->dev);
6e272061 228 struct resource *res;
2817142f 229 struct omap_wdt_dev *wdev;
b3112180 230 int ret;
7768a13c 231
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232 wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
233 if (!wdev)
234 return -ENOMEM;
b3112180 235
67c0f554 236 wdev->omap_wdt_users = false;
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237 wdev->dev = &pdev->dev;
238 wdev->wdt_trgr_pattern = 0x1234;
239 mutex_init(&wdev->lock);
2817142f 240
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241 /* reserve static register mappings */
242 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
243 wdev->base = devm_ioremap_resource(&pdev->dev, res);
244 if (IS_ERR(wdev->base))
245 return PTR_ERR(wdev->base);
9f69e3b0 246
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247 wdev->wdog.info = &omap_wdt_info;
248 wdev->wdog.ops = &omap_wdt_ops;
249 wdev->wdog.min_timeout = TIMER_MARGIN_MIN;
250 wdev->wdog.max_timeout = TIMER_MARGIN_MAX;
67c0f554 251
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252 if (watchdog_init_timeout(&wdev->wdog, timer_margin, &pdev->dev) < 0)
253 wdev->wdog.timeout = TIMER_MARGIN_DEFAULT;
67c0f554 254
d2f78268 255 watchdog_set_nowayout(&wdev->wdog, nowayout);
67c0f554 256
d2f78268 257 platform_set_drvdata(pdev, wdev);
7768a13c 258
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259 pm_runtime_enable(wdev->dev);
260 pm_runtime_get_sync(wdev->dev);
789cd470 261
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262 if (pdata && pdata->read_reset_sources) {
263 u32 rs = pdata->read_reset_sources();
264 if (rs & (1 << OMAP_MPU_WD_RST_SRC_ID_SHIFT))
265 wdev->wdog.bootstatus = WDIOF_CARDRESET;
266 }
7768a13c 267
67c0f554 268 omap_wdt_disable(wdev);
2817142f 269
d2f78268 270 ret = watchdog_register_device(&wdev->wdog);
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271 if (ret) {
272 pm_runtime_disable(wdev->dev);
273 return ret;
274 }
7768a13c 275
2817142f 276 pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n",
4a7e94a0 277 readl_relaxed(wdev->base + OMAP_WATCHDOG_REV) & 0xFF,
d2f78268 278 wdev->wdog.timeout);
7768a13c 279
7ec5ad0f 280 pm_runtime_put_sync(wdev->dev);
789cd470 281
7768a13c 282 return 0;
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283}
284
285static void omap_wdt_shutdown(struct platform_device *pdev)
286{
d2f78268 287 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
2817142f 288
67c0f554 289 mutex_lock(&wdev->lock);
0503add9 290 if (wdev->omap_wdt_users) {
2817142f 291 omap_wdt_disable(wdev);
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292 pm_runtime_put_sync(wdev->dev);
293 }
67c0f554 294 mutex_unlock(&wdev->lock);
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295}
296
4b12b896 297static int omap_wdt_remove(struct platform_device *pdev)
7768a13c 298{
d2f78268 299 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
2817142f 300
12c583d8 301 pm_runtime_disable(wdev->dev);
d2f78268 302 watchdog_unregister_device(&wdev->wdog);
b3112180 303
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304 return 0;
305}
306
307#ifdef CONFIG_PM
308
309/* REVISIT ... not clear this is the best way to handle system suspend; and
310 * it's very inappropriate for selective device suspend (e.g. suspending this
311 * through sysfs rather than by stopping the watchdog daemon). Also, this
312 * may not play well enough with NOWAYOUT...
313 */
314
315static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
316{
d2f78268 317 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
b3112180 318
67c0f554 319 mutex_lock(&wdev->lock);
0503add9 320 if (wdev->omap_wdt_users) {
2817142f 321 omap_wdt_disable(wdev);
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322 pm_runtime_put_sync(wdev->dev);
323 }
67c0f554 324 mutex_unlock(&wdev->lock);
b3112180 325
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326 return 0;
327}
328
329static int omap_wdt_resume(struct platform_device *pdev)
330{
d2f78268 331 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
b3112180 332
67c0f554 333 mutex_lock(&wdev->lock);
2817142f 334 if (wdev->omap_wdt_users) {
0503add9 335 pm_runtime_get_sync(wdev->dev);
2817142f 336 omap_wdt_enable(wdev);
67c0f554 337 omap_wdt_reload(wdev);
7768a13c 338 }
67c0f554 339 mutex_unlock(&wdev->lock);
b3112180 340
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341 return 0;
342}
343
344#else
345#define omap_wdt_suspend NULL
346#define omap_wdt_resume NULL
347#endif
348
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349static const struct of_device_id omap_wdt_of_match[] = {
350 { .compatible = "ti,omap3-wdt", },
351 {},
352};
353MODULE_DEVICE_TABLE(of, omap_wdt_of_match);
354
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355static struct platform_driver omap_wdt_driver = {
356 .probe = omap_wdt_probe,
82268714 357 .remove = omap_wdt_remove,
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358 .shutdown = omap_wdt_shutdown,
359 .suspend = omap_wdt_suspend,
360 .resume = omap_wdt_resume,
361 .driver = {
7768a13c 362 .name = "omap_wdt",
e6ca04ea 363 .of_match_table = omap_wdt_of_match,
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364 },
365};
366
b8ec6118 367module_platform_driver(omap_wdt_driver);
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368
369MODULE_AUTHOR("George G. Davis");
370MODULE_LICENSE("GPL");
f37d193c 371MODULE_ALIAS("platform:omap_wdt");
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