Commit | Line | Data |
---|---|---|
7768a13c | 1 | /* |
2817142f | 2 | * omap_wdt.c |
7768a13c | 3 | * |
2817142f | 4 | * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog |
7768a13c KS |
5 | * |
6 | * Author: MontaVista Software, Inc. | |
7 | * <gdavis@mvista.com> or <source@mvista.com> | |
8 | * | |
9 | * 2003 (c) MontaVista Software, Inc. This file is licensed under the | |
10 | * terms of the GNU General Public License version 2. This program is | |
11 | * licensed "as is" without any warranty of any kind, whether express | |
12 | * or implied. | |
13 | * | |
14 | * History: | |
15 | * | |
16 | * 20030527: George G. Davis <gdavis@mvista.com> | |
17 | * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c | |
18 | * (c) Copyright 2000 Oleg Drokin <green@crimea.edu> | |
29fa0586 | 19 | * Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk> |
7768a13c KS |
20 | * |
21 | * Copyright (c) 2004 Texas Instruments. | |
22 | * 1. Modified to support OMAP1610 32-KHz watchdog timer | |
23 | * 2. Ported to 2.6 kernel | |
24 | * | |
25 | * Copyright (c) 2005 David Brownell | |
26 | * Use the driver model and standard identifiers; handle bigger timeouts. | |
27 | */ | |
28 | ||
27c766aa JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
7768a13c | 31 | #include <linux/module.h> |
7768a13c KS |
32 | #include <linux/types.h> |
33 | #include <linux/kernel.h> | |
7768a13c | 34 | #include <linux/mm.h> |
7768a13c KS |
35 | #include <linux/watchdog.h> |
36 | #include <linux/reboot.h> | |
7768a13c KS |
37 | #include <linux/init.h> |
38 | #include <linux/err.h> | |
39 | #include <linux/platform_device.h> | |
40 | #include <linux/moduleparam.h> | |
089ab079 | 41 | #include <linux/io.h> |
5a0e3ad6 | 42 | #include <linux/slab.h> |
7ec5ad0f | 43 | #include <linux/pm_runtime.h> |
129f5577 | 44 | #include <linux/platform_data/omap-wd-timer.h> |
7768a13c KS |
45 | |
46 | #include "omap_wdt.h" | |
47 | ||
48 | static unsigned timer_margin; | |
49 | module_param(timer_margin, uint, 0); | |
50 | MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)"); | |
51 | ||
2817142f FB |
52 | struct omap_wdt_dev { |
53 | void __iomem *base; /* physical */ | |
54 | struct device *dev; | |
67c0f554 | 55 | bool omap_wdt_users; |
2817142f | 56 | struct resource *mem; |
67c0f554 AK |
57 | int wdt_trgr_pattern; |
58 | struct mutex lock; /* to avoid races with PM */ | |
2817142f FB |
59 | }; |
60 | ||
67c0f554 | 61 | static void omap_wdt_reload(struct omap_wdt_dev *wdev) |
7768a13c | 62 | { |
2817142f | 63 | void __iomem *base = wdev->base; |
b3112180 | 64 | |
7768a13c | 65 | /* wait for posted write to complete */ |
9f69e3b0 | 66 | while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08) |
7768a13c | 67 | cpu_relax(); |
b3112180 | 68 | |
67c0f554 AK |
69 | wdev->wdt_trgr_pattern = ~wdev->wdt_trgr_pattern; |
70 | __raw_writel(wdev->wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR)); | |
b3112180 | 71 | |
7768a13c | 72 | /* wait for posted write to complete */ |
9f69e3b0 | 73 | while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08) |
7768a13c KS |
74 | cpu_relax(); |
75 | /* reloaded WCRR from WLDR */ | |
76 | } | |
77 | ||
2817142f | 78 | static void omap_wdt_enable(struct omap_wdt_dev *wdev) |
7768a13c | 79 | { |
b3112180 FB |
80 | void __iomem *base = wdev->base; |
81 | ||
7768a13c | 82 | /* Sequence to enable the watchdog */ |
9f69e3b0 FB |
83 | __raw_writel(0xBBBB, base + OMAP_WATCHDOG_SPR); |
84 | while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10) | |
7768a13c | 85 | cpu_relax(); |
b3112180 | 86 | |
9f69e3b0 FB |
87 | __raw_writel(0x4444, base + OMAP_WATCHDOG_SPR); |
88 | while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10) | |
7768a13c KS |
89 | cpu_relax(); |
90 | } | |
91 | ||
2817142f | 92 | static void omap_wdt_disable(struct omap_wdt_dev *wdev) |
7768a13c | 93 | { |
b3112180 FB |
94 | void __iomem *base = wdev->base; |
95 | ||
7768a13c | 96 | /* sequence required to disable watchdog */ |
9f69e3b0 FB |
97 | __raw_writel(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */ |
98 | while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10) | |
7768a13c | 99 | cpu_relax(); |
b3112180 | 100 | |
9f69e3b0 FB |
101 | __raw_writel(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */ |
102 | while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10) | |
7768a13c KS |
103 | cpu_relax(); |
104 | } | |
105 | ||
67c0f554 AK |
106 | static void omap_wdt_set_timer(struct omap_wdt_dev *wdev, |
107 | unsigned int timeout) | |
7768a13c | 108 | { |
67c0f554 | 109 | u32 pre_margin = GET_WLDR_VAL(timeout); |
b3112180 | 110 | void __iomem *base = wdev->base; |
7768a13c KS |
111 | |
112 | /* just count up at 32 KHz */ | |
9f69e3b0 | 113 | while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04) |
7768a13c | 114 | cpu_relax(); |
b3112180 | 115 | |
9f69e3b0 FB |
116 | __raw_writel(pre_margin, base + OMAP_WATCHDOG_LDR); |
117 | while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04) | |
7768a13c KS |
118 | cpu_relax(); |
119 | } | |
120 | ||
67c0f554 | 121 | static int omap_wdt_start(struct watchdog_device *wdog) |
7768a13c | 122 | { |
67c0f554 | 123 | struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog); |
b3112180 FB |
124 | void __iomem *base = wdev->base; |
125 | ||
67c0f554 AK |
126 | mutex_lock(&wdev->lock); |
127 | ||
128 | wdev->omap_wdt_users = true; | |
7768a13c | 129 | |
7ec5ad0f | 130 | pm_runtime_get_sync(wdev->dev); |
7768a13c KS |
131 | |
132 | /* initialize prescaler */ | |
9f69e3b0 | 133 | while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01) |
7768a13c | 134 | cpu_relax(); |
b3112180 | 135 | |
9f69e3b0 FB |
136 | __raw_writel((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL); |
137 | while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01) | |
7768a13c KS |
138 | cpu_relax(); |
139 | ||
67c0f554 AK |
140 | omap_wdt_set_timer(wdev, wdog->timeout); |
141 | omap_wdt_reload(wdev); /* trigger loading of new timeout value */ | |
2817142f | 142 | omap_wdt_enable(wdev); |
b3112180 | 143 | |
67c0f554 AK |
144 | mutex_unlock(&wdev->lock); |
145 | ||
146 | return 0; | |
7768a13c KS |
147 | } |
148 | ||
67c0f554 | 149 | static int omap_wdt_stop(struct watchdog_device *wdog) |
7768a13c | 150 | { |
67c0f554 | 151 | struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog); |
b3112180 | 152 | |
67c0f554 | 153 | mutex_lock(&wdev->lock); |
2817142f | 154 | omap_wdt_disable(wdev); |
7ec5ad0f | 155 | pm_runtime_put_sync(wdev->dev); |
67c0f554 AK |
156 | wdev->omap_wdt_users = false; |
157 | mutex_unlock(&wdev->lock); | |
7768a13c KS |
158 | return 0; |
159 | } | |
160 | ||
67c0f554 | 161 | static int omap_wdt_ping(struct watchdog_device *wdog) |
7768a13c | 162 | { |
67c0f554 | 163 | struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog); |
b3112180 | 164 | |
67c0f554 AK |
165 | mutex_lock(&wdev->lock); |
166 | omap_wdt_reload(wdev); | |
167 | mutex_unlock(&wdev->lock); | |
168 | ||
169 | return 0; | |
7768a13c KS |
170 | } |
171 | ||
67c0f554 AK |
172 | static int omap_wdt_set_timeout(struct watchdog_device *wdog, |
173 | unsigned int timeout) | |
7768a13c | 174 | { |
67c0f554 | 175 | struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog); |
7768a13c | 176 | |
67c0f554 AK |
177 | mutex_lock(&wdev->lock); |
178 | omap_wdt_disable(wdev); | |
179 | omap_wdt_set_timer(wdev, timeout); | |
180 | omap_wdt_enable(wdev); | |
181 | omap_wdt_reload(wdev); | |
182 | wdog->timeout = timeout; | |
183 | mutex_unlock(&wdev->lock); | |
184 | ||
185 | return 0; | |
7768a13c KS |
186 | } |
187 | ||
67c0f554 AK |
188 | static const struct watchdog_info omap_wdt_info = { |
189 | .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, | |
190 | .identity = "OMAP Watchdog", | |
191 | }; | |
192 | ||
193 | static const struct watchdog_ops omap_wdt_ops = { | |
194 | .owner = THIS_MODULE, | |
195 | .start = omap_wdt_start, | |
196 | .stop = omap_wdt_stop, | |
197 | .ping = omap_wdt_ping, | |
198 | .set_timeout = omap_wdt_set_timeout, | |
7768a13c KS |
199 | }; |
200 | ||
2d991a16 | 201 | static int omap_wdt_probe(struct platform_device *pdev) |
7768a13c | 202 | { |
67c0f554 AK |
203 | struct omap_wd_timer_platform_data *pdata = pdev->dev.platform_data; |
204 | bool nowayout = WATCHDOG_NOWAYOUT; | |
205 | struct watchdog_device *omap_wdt; | |
7768a13c | 206 | struct resource *res, *mem; |
2817142f | 207 | struct omap_wdt_dev *wdev; |
67c0f554 | 208 | u32 rs; |
b3112180 | 209 | int ret; |
7768a13c | 210 | |
67c0f554 AK |
211 | omap_wdt = kzalloc(sizeof(*omap_wdt), GFP_KERNEL); |
212 | if (!omap_wdt) | |
213 | return -ENOMEM; | |
214 | ||
7768a13c KS |
215 | /* reserve static register mappings */ |
216 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
b3112180 FB |
217 | if (!res) { |
218 | ret = -ENOENT; | |
219 | goto err_get_resource; | |
220 | } | |
7768a13c | 221 | |
b782a563 | 222 | mem = request_mem_region(res->start, resource_size(res), pdev->name); |
b3112180 FB |
223 | if (!mem) { |
224 | ret = -EBUSY; | |
225 | goto err_busy; | |
226 | } | |
7768a13c | 227 | |
2817142f FB |
228 | wdev = kzalloc(sizeof(struct omap_wdt_dev), GFP_KERNEL); |
229 | if (!wdev) { | |
230 | ret = -ENOMEM; | |
b3112180 | 231 | goto err_kzalloc; |
2817142f | 232 | } |
b3112180 | 233 | |
67c0f554 AK |
234 | wdev->omap_wdt_users = false; |
235 | wdev->mem = mem; | |
236 | wdev->dev = &pdev->dev; | |
237 | wdev->wdt_trgr_pattern = 0x1234; | |
238 | mutex_init(&wdev->lock); | |
2817142f | 239 | |
b782a563 | 240 | wdev->base = ioremap(res->start, resource_size(res)); |
9f69e3b0 FB |
241 | if (!wdev->base) { |
242 | ret = -ENOMEM; | |
b3112180 | 243 | goto err_ioremap; |
9f69e3b0 FB |
244 | } |
245 | ||
67c0f554 AK |
246 | omap_wdt->info = &omap_wdt_info; |
247 | omap_wdt->ops = &omap_wdt_ops; | |
248 | omap_wdt->min_timeout = TIMER_MARGIN_MIN; | |
249 | omap_wdt->max_timeout = TIMER_MARGIN_MAX; | |
250 | ||
251 | if (timer_margin >= TIMER_MARGIN_MIN && | |
252 | timer_margin <= TIMER_MARGIN_MAX) | |
253 | omap_wdt->timeout = timer_margin; | |
254 | else | |
255 | omap_wdt->timeout = TIMER_MARGIN_DEFAULT; | |
256 | ||
257 | watchdog_set_drvdata(omap_wdt, wdev); | |
258 | watchdog_set_nowayout(omap_wdt, nowayout); | |
259 | ||
260 | platform_set_drvdata(pdev, omap_wdt); | |
7768a13c | 261 | |
7ec5ad0f VC |
262 | pm_runtime_enable(wdev->dev); |
263 | pm_runtime_get_sync(wdev->dev); | |
789cd470 | 264 | |
67c0f554 AK |
265 | if (pdata && pdata->read_reset_sources) |
266 | rs = pdata->read_reset_sources(); | |
267 | else | |
268 | rs = 0; | |
269 | omap_wdt->bootstatus = (rs & (1 << OMAP_MPU_WD_RST_SRC_ID_SHIFT)) ? | |
270 | WDIOF_CARDRESET : 0; | |
7768a13c | 271 | |
67c0f554 | 272 | omap_wdt_disable(wdev); |
2817142f | 273 | |
67c0f554 | 274 | ret = watchdog_register_device(omap_wdt); |
7768a13c | 275 | if (ret) |
67c0f554 | 276 | goto err_register; |
7768a13c | 277 | |
2817142f | 278 | pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n", |
9f69e3b0 | 279 | __raw_readl(wdev->base + OMAP_WATCHDOG_REV) & 0xFF, |
67c0f554 | 280 | omap_wdt->timeout); |
7768a13c | 281 | |
7ec5ad0f | 282 | pm_runtime_put_sync(wdev->dev); |
789cd470 | 283 | |
7768a13c KS |
284 | return 0; |
285 | ||
67c0f554 | 286 | err_register: |
12c583d8 | 287 | pm_runtime_disable(wdev->dev); |
b3112180 FB |
288 | platform_set_drvdata(pdev, NULL); |
289 | iounmap(wdev->base); | |
290 | ||
291 | err_ioremap: | |
292 | wdev->base = NULL; | |
b3112180 FB |
293 | kfree(wdev); |
294 | ||
295 | err_kzalloc: | |
b782a563 | 296 | release_mem_region(res->start, resource_size(res)); |
b3112180 FB |
297 | |
298 | err_busy: | |
299 | err_get_resource: | |
67c0f554 | 300 | kfree(omap_wdt); |
7768a13c KS |
301 | return ret; |
302 | } | |
303 | ||
304 | static void omap_wdt_shutdown(struct platform_device *pdev) | |
305 | { | |
67c0f554 AK |
306 | struct watchdog_device *wdog = platform_get_drvdata(pdev); |
307 | struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog); | |
2817142f | 308 | |
67c0f554 | 309 | mutex_lock(&wdev->lock); |
0503add9 | 310 | if (wdev->omap_wdt_users) { |
2817142f | 311 | omap_wdt_disable(wdev); |
0503add9 PW |
312 | pm_runtime_put_sync(wdev->dev); |
313 | } | |
67c0f554 | 314 | mutex_unlock(&wdev->lock); |
7768a13c KS |
315 | } |
316 | ||
4b12b896 | 317 | static int omap_wdt_remove(struct platform_device *pdev) |
7768a13c | 318 | { |
67c0f554 AK |
319 | struct watchdog_device *wdog = platform_get_drvdata(pdev); |
320 | struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog); | |
2817142f FB |
321 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
322 | ||
12c583d8 | 323 | pm_runtime_disable(wdev->dev); |
67c0f554 | 324 | watchdog_unregister_device(wdog); |
b782a563 | 325 | release_mem_region(res->start, resource_size(res)); |
2817142f | 326 | platform_set_drvdata(pdev, NULL); |
b3112180 | 327 | |
9f69e3b0 FB |
328 | iounmap(wdev->base); |
329 | ||
2817142f | 330 | kfree(wdev); |
67c0f554 | 331 | kfree(wdog); |
b3112180 | 332 | |
7768a13c KS |
333 | return 0; |
334 | } | |
335 | ||
336 | #ifdef CONFIG_PM | |
337 | ||
338 | /* REVISIT ... not clear this is the best way to handle system suspend; and | |
339 | * it's very inappropriate for selective device suspend (e.g. suspending this | |
340 | * through sysfs rather than by stopping the watchdog daemon). Also, this | |
341 | * may not play well enough with NOWAYOUT... | |
342 | */ | |
343 | ||
344 | static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state) | |
345 | { | |
67c0f554 AK |
346 | struct watchdog_device *wdog = platform_get_drvdata(pdev); |
347 | struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog); | |
b3112180 | 348 | |
67c0f554 | 349 | mutex_lock(&wdev->lock); |
0503add9 | 350 | if (wdev->omap_wdt_users) { |
2817142f | 351 | omap_wdt_disable(wdev); |
0503add9 PW |
352 | pm_runtime_put_sync(wdev->dev); |
353 | } | |
67c0f554 | 354 | mutex_unlock(&wdev->lock); |
b3112180 | 355 | |
7768a13c KS |
356 | return 0; |
357 | } | |
358 | ||
359 | static int omap_wdt_resume(struct platform_device *pdev) | |
360 | { | |
67c0f554 AK |
361 | struct watchdog_device *wdog = platform_get_drvdata(pdev); |
362 | struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog); | |
b3112180 | 363 | |
67c0f554 | 364 | mutex_lock(&wdev->lock); |
2817142f | 365 | if (wdev->omap_wdt_users) { |
0503add9 | 366 | pm_runtime_get_sync(wdev->dev); |
2817142f | 367 | omap_wdt_enable(wdev); |
67c0f554 | 368 | omap_wdt_reload(wdev); |
7768a13c | 369 | } |
67c0f554 | 370 | mutex_unlock(&wdev->lock); |
b3112180 | 371 | |
7768a13c KS |
372 | return 0; |
373 | } | |
374 | ||
375 | #else | |
376 | #define omap_wdt_suspend NULL | |
377 | #define omap_wdt_resume NULL | |
378 | #endif | |
379 | ||
e6ca04ea XJ |
380 | static const struct of_device_id omap_wdt_of_match[] = { |
381 | { .compatible = "ti,omap3-wdt", }, | |
382 | {}, | |
383 | }; | |
384 | MODULE_DEVICE_TABLE(of, omap_wdt_of_match); | |
385 | ||
7768a13c KS |
386 | static struct platform_driver omap_wdt_driver = { |
387 | .probe = omap_wdt_probe, | |
82268714 | 388 | .remove = omap_wdt_remove, |
7768a13c KS |
389 | .shutdown = omap_wdt_shutdown, |
390 | .suspend = omap_wdt_suspend, | |
391 | .resume = omap_wdt_resume, | |
392 | .driver = { | |
393 | .owner = THIS_MODULE, | |
394 | .name = "omap_wdt", | |
e6ca04ea | 395 | .of_match_table = omap_wdt_of_match, |
7768a13c KS |
396 | }, |
397 | }; | |
398 | ||
b8ec6118 | 399 | module_platform_driver(omap_wdt_driver); |
7768a13c KS |
400 | |
401 | MODULE_AUTHOR("George G. Davis"); | |
402 | MODULE_LICENSE("GPL"); | |
f37d193c | 403 | MODULE_ALIAS("platform:omap_wdt"); |