[deliverable/linux.git] / drivers / watchdog / omap_wdt.c

/*
 * omap_wdt.c
 *
 * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
 *
 * Author: MontaVista Software, Inc.
 *	 <gdavis@mvista.com> or <source@mvista.com>
 *
 * 2003 (c) MontaVista Software, Inc. This file is licensed under the
 * terms of the GNU General Public License version 2. This program is
 * licensed "as is" without any warranty of any kind, whether express
 * or implied.
 *
 * History:
 *
 * 20030527: George G. Davis <gdavis@mvista.com>
 *	Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
 *	(c) Copyright 2000 Oleg Drokin <green@crimea.edu>
 *	Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk>
 *
 * Copyright (c) 2004 Texas Instruments.
 *	1. Modified to support OMAP1610 32-KHz watchdog timer
 *	2. Ported to 2.6 kernel
 *
 * Copyright (c) 2005 David Brownell
 *	Use the driver model and standard identifiers; handle bigger timeouts.
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/watchdog.h>
#include <linux/reboot.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/moduleparam.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/platform_data/omap-wd-timer.h>

#include "omap_wdt.h"

static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
	"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

static unsigned timer_margin;
module_param(timer_margin, uint, 0);
MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");

#define to_omap_wdt_dev(_wdog)	container_of(_wdog, struct omap_wdt_dev, wdog)

struct omap_wdt_dev {
	struct watchdog_device wdog;
	void __iomem    *base;          /* physical */
	struct device   *dev;
	bool		omap_wdt_users;
	int		wdt_trgr_pattern;
	struct mutex	lock;		/* to avoid races with PM */
};

static void omap_wdt_reload(struct omap_wdt_dev *wdev)
{
	void __iomem    *base = wdev->base;

	/* wait for posted write to complete */
	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08)
		cpu_relax();

	wdev->wdt_trgr_pattern = ~wdev->wdt_trgr_pattern;
	writel_relaxed(wdev->wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR));

	/* wait for posted write to complete */
	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08)
		cpu_relax();
	/* reloaded WCRR from WLDR */
}

static void omap_wdt_enable(struct omap_wdt_dev *wdev)
{
	void __iomem *base = wdev->base;

	/* Sequence to enable the watchdog */
	writel_relaxed(0xBBBB, base + OMAP_WATCHDOG_SPR);
	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10)
		cpu_relax();

	writel_relaxed(0x4444, base + OMAP_WATCHDOG_SPR);
	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10)
		cpu_relax();
}

static void omap_wdt_disable(struct omap_wdt_dev *wdev)
{
	void __iomem *base = wdev->base;

	/* sequence required to disable watchdog */
	writel_relaxed(0xAAAA, base + OMAP_WATCHDOG_SPR);	/* TIMER_MODE */
	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10)
		cpu_relax();

	writel_relaxed(0x5555, base + OMAP_WATCHDOG_SPR);	/* TIMER_MODE */
	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10)
		cpu_relax();
}

static void omap_wdt_set_timer(struct omap_wdt_dev *wdev,
				   unsigned int timeout)
{
	u32 pre_margin = GET_WLDR_VAL(timeout);
	void __iomem *base = wdev->base;

	/* just count up at 32 KHz */
	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04)
		cpu_relax();

	writel_relaxed(pre_margin, base + OMAP_WATCHDOG_LDR);
	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04)
		cpu_relax();
}

static int omap_wdt_start(struct watchdog_device *wdog)
{
	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
	void __iomem *base = wdev->base;

	mutex_lock(&wdev->lock);

	wdev->omap_wdt_users = true;

	pm_runtime_get_sync(wdev->dev);

	/*
	 * Make sure the watchdog is disabled. This is unfortunately required
	 * because writing to various registers with the watchdog running has no
	 * effect.
	 */
	omap_wdt_disable(wdev);

	/* initialize prescaler */
	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01)
		cpu_relax();

	writel_relaxed((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL);
	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01)
		cpu_relax();

	omap_wdt_set_timer(wdev, wdog->timeout);
	omap_wdt_reload(wdev); /* trigger loading of new timeout value */
	omap_wdt_enable(wdev);

	mutex_unlock(&wdev->lock);

	return 0;
}

static int omap_wdt_stop(struct watchdog_device *wdog)
{
	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);

	mutex_lock(&wdev->lock);
	omap_wdt_disable(wdev);
	pm_runtime_put_sync(wdev->dev);
	wdev->omap_wdt_users = false;
	mutex_unlock(&wdev->lock);
	return 0;
}

static int omap_wdt_ping(struct watchdog_device *wdog)
{
	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);

	mutex_lock(&wdev->lock);
	omap_wdt_reload(wdev);
	mutex_unlock(&wdev->lock);

	return 0;
}

static int omap_wdt_set_timeout(struct watchdog_device *wdog,
				unsigned int timeout)
{
	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);

	mutex_lock(&wdev->lock);
	omap_wdt_disable(wdev);
	omap_wdt_set_timer(wdev, timeout);
	omap_wdt_enable(wdev);
	omap_wdt_reload(wdev);
	wdog->timeout = timeout;
	mutex_unlock(&wdev->lock);

	return 0;
}

static const struct watchdog_info omap_wdt_info = {
	.options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING,
	.identity = "OMAP Watchdog",
};

static const struct watchdog_ops omap_wdt_ops = {
	.owner		= THIS_MODULE,
	.start		= omap_wdt_start,
	.stop		= omap_wdt_stop,
	.ping		= omap_wdt_ping,
	.set_timeout	= omap_wdt_set_timeout,
};

static int omap_wdt_probe(struct platform_device *pdev)
{
	struct omap_wd_timer_platform_data *pdata = dev_get_platdata(&pdev->dev);
	struct resource *res;
	struct omap_wdt_dev *wdev;
	int ret;

	wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
	if (!wdev)
		return -ENOMEM;

	wdev->omap_wdt_users	= false;
	wdev->dev		= &pdev->dev;
	wdev->wdt_trgr_pattern	= 0x1234;
	mutex_init(&wdev->lock);

	/* reserve static register mappings */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	wdev->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(wdev->base))
		return PTR_ERR(wdev->base);

	wdev->wdog.info = &omap_wdt_info;
	wdev->wdog.ops = &omap_wdt_ops;
	wdev->wdog.min_timeout = TIMER_MARGIN_MIN;
	wdev->wdog.max_timeout = TIMER_MARGIN_MAX;

	if (watchdog_init_timeout(&wdev->wdog, timer_margin, &pdev->dev) < 0)
		wdev->wdog.timeout = TIMER_MARGIN_DEFAULT;

	watchdog_set_nowayout(&wdev->wdog, nowayout);

	platform_set_drvdata(pdev, wdev);

	pm_runtime_enable(wdev->dev);
	pm_runtime_get_sync(wdev->dev);

	if (pdata && pdata->read_reset_sources) {
		u32 rs = pdata->read_reset_sources();
		if (rs & (1 << OMAP_MPU_WD_RST_SRC_ID_SHIFT))
			wdev->wdog.bootstatus = WDIOF_CARDRESET;
	}

	omap_wdt_disable(wdev);

	ret = watchdog_register_device(&wdev->wdog);
	if (ret) {
		pm_runtime_disable(wdev->dev);
		return ret;
	}

	pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n",
		readl_relaxed(wdev->base + OMAP_WATCHDOG_REV) & 0xFF,
		wdev->wdog.timeout);

	pm_runtime_put_sync(wdev->dev);

	return 0;
}

static void omap_wdt_shutdown(struct platform_device *pdev)
{
	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);

	mutex_lock(&wdev->lock);
	if (wdev->omap_wdt_users) {
		omap_wdt_disable(wdev);
		pm_runtime_put_sync(wdev->dev);
	}
	mutex_unlock(&wdev->lock);
}

static int omap_wdt_remove(struct platform_device *pdev)
{
	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);

	pm_runtime_disable(wdev->dev);
	watchdog_unregister_device(&wdev->wdog);

	return 0;
}

#ifdef	CONFIG_PM

/* REVISIT ... not clear this is the best way to handle system suspend; and
 * it's very inappropriate for selective device suspend (e.g. suspending this
 * through sysfs rather than by stopping the watchdog daemon).  Also, this
 * may not play well enough with NOWAYOUT...
 */

static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
{
	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);

	mutex_lock(&wdev->lock);
	if (wdev->omap_wdt_users) {
		omap_wdt_disable(wdev);
		pm_runtime_put_sync(wdev->dev);
	}
	mutex_unlock(&wdev->lock);

	return 0;
}

static int omap_wdt_resume(struct platform_device *pdev)
{
	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);

	mutex_lock(&wdev->lock);
	if (wdev->omap_wdt_users) {
		pm_runtime_get_sync(wdev->dev);
		omap_wdt_enable(wdev);
		omap_wdt_reload(wdev);
	}
	mutex_unlock(&wdev->lock);

	return 0;
}

#else
#define	omap_wdt_suspend	NULL
#define	omap_wdt_resume		NULL
#endif

static const struct of_device_id omap_wdt_of_match[] = {
	{ .compatible = "ti,omap3-wdt", },
	{},
};
MODULE_DEVICE_TABLE(of, omap_wdt_of_match);

static struct platform_driver omap_wdt_driver = {
	.probe		= omap_wdt_probe,
	.remove		= omap_wdt_remove,
	.shutdown	= omap_wdt_shutdown,
	.suspend	= omap_wdt_suspend,
	.resume		= omap_wdt_resume,
	.driver		= {
		.name	= "omap_wdt",
		.of_match_table = omap_wdt_of_match,
	},
};

module_platform_driver(omap_wdt_driver);

MODULE_AUTHOR("George G. Davis");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:omap_wdt");
Commit	Line	Data
7768a13c	1	/*
2817142f	2	* omap_wdt.c
7768a13c	3	*
2817142f	4	* Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
7768a13c KS	5	*
	6	* Author: MontaVista Software, Inc.
	7	* <gdavis@mvista.com> or <source@mvista.com>
	8	*
	9	* 2003 (c) MontaVista Software, Inc. This file is licensed under the
	10	* terms of the GNU General Public License version 2. This program is
	11	* licensed "as is" without any warranty of any kind, whether express
	12	* or implied.
	13	*
	14	* History:
	15	*
	16	* 20030527: George G. Davis <gdavis@mvista.com>
	17	* Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
	18	* (c) Copyright 2000 Oleg Drokin <green@crimea.edu>
29fa0586	19	* Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk>
7768a13c KS	20	*
	21	* Copyright (c) 2004 Texas Instruments.
	22	* 1. Modified to support OMAP1610 32-KHz watchdog timer
	23	* 2. Ported to 2.6 kernel
	24	*
	25	* Copyright (c) 2005 David Brownell
	26	* Use the driver model and standard identifiers; handle bigger timeouts.
	27	*/
	28
27c766aa JP	29	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27c766aa JP	30
7768a13c	31	#include <linux/module.h>
7768a13c KS	32	#include <linux/types.h>
7768a13c KS	33	#include <linux/kernel.h>
7768a13c	34	#include <linux/mm.h>
7768a13c KS	35	#include <linux/watchdog.h>
7768a13c KS	36	#include <linux/reboot.h>
7768a13c KS	37	#include <linux/err.h>
	38	#include <linux/platform_device.h>
	39	#include <linux/moduleparam.h>
089ab079	40	#include <linux/io.h>
5a0e3ad6	41	#include <linux/slab.h>
7ec5ad0f	42	#include <linux/pm_runtime.h>
129f5577	43	#include <linux/platform_data/omap-wd-timer.h>
7768a13c KS	44
	45	#include "omap_wdt.h"
	46
2dd7b244 PR	47	static bool nowayout = WATCHDOG_NOWAYOUT;
	48	module_param(nowayout, bool, 0);
	49	MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
	50	"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
	51
7768a13c KS	52	static unsigned timer_margin;
	53	module_param(timer_margin, uint, 0);
	54	MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");
	55
d2f78268 UKK	56	#define to_omap_wdt_dev(_wdog) container_of(_wdog, struct omap_wdt_dev, wdog)
d2f78268 UKK	57
2817142f	58	struct omap_wdt_dev {
d2f78268	59	struct watchdog_device wdog;
2817142f FB	60	void __iomem base; / physical */
2817142f FB	61	struct device *dev;
67c0f554	62	bool omap_wdt_users;
67c0f554 AK	63	int wdt_trgr_pattern;
67c0f554 AK	64	struct mutex lock; /* to avoid races with PM */
2817142f FB	65	};
2817142f FB	66
67c0f554	67	static void omap_wdt_reload(struct omap_wdt_dev *wdev)
7768a13c	68	{
2817142f	69	void __iomem *base = wdev->base;
b3112180	70
7768a13c	71	/* wait for posted write to complete */
4a7e94a0	72	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08)
7768a13c	73	cpu_relax();
b3112180	74
67c0f554	75	wdev->wdt_trgr_pattern = ~wdev->wdt_trgr_pattern;
4a7e94a0	76	writel_relaxed(wdev->wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR));
b3112180	77
7768a13c	78	/* wait for posted write to complete */
4a7e94a0	79	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08)
7768a13c KS	80	cpu_relax();
	81	/* reloaded WCRR from WLDR */
	82	}
	83
2817142f	84	static void omap_wdt_enable(struct omap_wdt_dev *wdev)
7768a13c	85	{
b3112180 FB	86	void __iomem *base = wdev->base;
b3112180 FB	87
7768a13c	88	/* Sequence to enable the watchdog */
4a7e94a0 VK	89	writel_relaxed(0xBBBB, base + OMAP_WATCHDOG_SPR);
4a7e94a0 VK	90	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10)
7768a13c	91	cpu_relax();
b3112180	92
4a7e94a0 VK	93	writel_relaxed(0x4444, base + OMAP_WATCHDOG_SPR);
4a7e94a0 VK	94	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10)
7768a13c KS	95	cpu_relax();
	96	}
	97
2817142f	98	static void omap_wdt_disable(struct omap_wdt_dev *wdev)
7768a13c	99	{
b3112180 FB	100	void __iomem *base = wdev->base;
b3112180 FB	101
7768a13c	102	/* sequence required to disable watchdog */
4a7e94a0 VK	103	writel_relaxed(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
4a7e94a0 VK	104	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10)
7768a13c	105	cpu_relax();
b3112180	106
4a7e94a0 VK	107	writel_relaxed(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
4a7e94a0 VK	108	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10)
7768a13c KS	109	cpu_relax();
	110	}
	111
67c0f554 AK	112	static void omap_wdt_set_timer(struct omap_wdt_dev *wdev,
67c0f554 AK	113	unsigned int timeout)
7768a13c	114	{
67c0f554	115	u32 pre_margin = GET_WLDR_VAL(timeout);
b3112180	116	void __iomem *base = wdev->base;
7768a13c KS	117
7768a13c KS	118	/* just count up at 32 KHz */
4a7e94a0	119	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04)
7768a13c	120	cpu_relax();
b3112180	121
4a7e94a0 VK	122	writel_relaxed(pre_margin, base + OMAP_WATCHDOG_LDR);
4a7e94a0 VK	123	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04)
7768a13c KS	124	cpu_relax();
	125	}
	126
67c0f554	127	static int omap_wdt_start(struct watchdog_device *wdog)
7768a13c	128	{
d2f78268	129	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
b3112180 FB	130	void __iomem *base = wdev->base;
b3112180 FB	131
67c0f554 AK	132	mutex_lock(&wdev->lock);
	133
	134	wdev->omap_wdt_users = true;
7768a13c	135
7ec5ad0f	136	pm_runtime_get_sync(wdev->dev);
7768a13c	137
530c11d4 UKK	138	/*
	139	* Make sure the watchdog is disabled. This is unfortunately required
	140	* because writing to various registers with the watchdog running has no
	141	* effect.
	142	*/
	143	omap_wdt_disable(wdev);
	144
7768a13c	145	/* initialize prescaler */
4a7e94a0	146	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01)
7768a13c	147	cpu_relax();
b3112180	148
4a7e94a0 VK	149	writel_relaxed((1 << 5) \| (PTV << 2), base + OMAP_WATCHDOG_CNTRL);
4a7e94a0 VK	150	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01)
7768a13c KS	151	cpu_relax();
7768a13c KS	152
67c0f554 AK	153	omap_wdt_set_timer(wdev, wdog->timeout);
67c0f554 AK	154	omap_wdt_reload(wdev); /* trigger loading of new timeout value */
2817142f	155	omap_wdt_enable(wdev);
b3112180	156
67c0f554 AK	157	mutex_unlock(&wdev->lock);
	158
	159	return 0;
7768a13c KS	160	}
7768a13c KS	161
67c0f554	162	static int omap_wdt_stop(struct watchdog_device *wdog)
7768a13c	163	{
d2f78268	164	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
b3112180	165
67c0f554	166	mutex_lock(&wdev->lock);
2817142f	167	omap_wdt_disable(wdev);
7ec5ad0f	168	pm_runtime_put_sync(wdev->dev);
67c0f554 AK	169	wdev->omap_wdt_users = false;
67c0f554 AK	170	mutex_unlock(&wdev->lock);
7768a13c KS	171	return 0;
	172	}
	173
67c0f554	174	static int omap_wdt_ping(struct watchdog_device *wdog)
7768a13c	175	{
d2f78268	176	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
b3112180	177
67c0f554 AK	178	mutex_lock(&wdev->lock);
	179	omap_wdt_reload(wdev);
	180	mutex_unlock(&wdev->lock);
	181
	182	return 0;
7768a13c KS	183	}
7768a13c KS	184
67c0f554 AK	185	static int omap_wdt_set_timeout(struct watchdog_device *wdog,
67c0f554 AK	186	unsigned int timeout)
7768a13c	187	{
d2f78268	188	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
7768a13c	189
67c0f554 AK	190	mutex_lock(&wdev->lock);
	191	omap_wdt_disable(wdev);
	192	omap_wdt_set_timer(wdev, timeout);
	193	omap_wdt_enable(wdev);
	194	omap_wdt_reload(wdev);
	195	wdog->timeout = timeout;
	196	mutex_unlock(&wdev->lock);
	197
	198	return 0;
7768a13c KS	199	}
7768a13c KS	200
67c0f554	201	static const struct watchdog_info omap_wdt_info = {
fb1cbeae	202	.options = WDIOF_SETTIMEOUT \| WDIOF_MAGICCLOSE \| WDIOF_KEEPALIVEPING,
67c0f554 AK	203	.identity = "OMAP Watchdog",
	204	};
	205
	206	static const struct watchdog_ops omap_wdt_ops = {
	207	.owner = THIS_MODULE,
	208	.start = omap_wdt_start,
	209	.stop = omap_wdt_stop,
	210	.ping = omap_wdt_ping,
	211	.set_timeout = omap_wdt_set_timeout,
7768a13c KS	212	};
7768a13c KS	213
2d991a16	214	static int omap_wdt_probe(struct platform_device *pdev)
7768a13c	215	{
bc8fdfbe	216	struct omap_wd_timer_platform_data *pdata = dev_get_platdata(&pdev->dev);
6e272061	217	struct resource *res;
2817142f	218	struct omap_wdt_dev *wdev;
b3112180	219	int ret;
7768a13c	220
4f4753d9 AK	221	wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
	222	if (!wdev)
	223	return -ENOMEM;
b3112180	224
67c0f554	225	wdev->omap_wdt_users = false;
67c0f554 AK	226	wdev->dev = &pdev->dev;
	227	wdev->wdt_trgr_pattern = 0x1234;
	228	mutex_init(&wdev->lock);
2817142f	229
6e272061 JH	230	/* reserve static register mappings */
	231	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	232	wdev->base = devm_ioremap_resource(&pdev->dev, res);
	233	if (IS_ERR(wdev->base))
	234	return PTR_ERR(wdev->base);
9f69e3b0	235
d2f78268 UKK	236	wdev->wdog.info = &omap_wdt_info;
	237	wdev->wdog.ops = &omap_wdt_ops;
	238	wdev->wdog.min_timeout = TIMER_MARGIN_MIN;
	239	wdev->wdog.max_timeout = TIMER_MARGIN_MAX;
67c0f554	240
d2f78268 UKK	241	if (watchdog_init_timeout(&wdev->wdog, timer_margin, &pdev->dev) < 0)
d2f78268 UKK	242	wdev->wdog.timeout = TIMER_MARGIN_DEFAULT;
67c0f554	243
d2f78268	244	watchdog_set_nowayout(&wdev->wdog, nowayout);
67c0f554	245
d2f78268	246	platform_set_drvdata(pdev, wdev);
7768a13c	247
7ec5ad0f VC	248	pm_runtime_enable(wdev->dev);
7ec5ad0f VC	249	pm_runtime_get_sync(wdev->dev);
789cd470	250
0b3330f3 UKK	251	if (pdata && pdata->read_reset_sources) {
	252	u32 rs = pdata->read_reset_sources();
	253	if (rs & (1 << OMAP_MPU_WD_RST_SRC_ID_SHIFT))
	254	wdev->wdog.bootstatus = WDIOF_CARDRESET;
	255	}
7768a13c	256
67c0f554	257	omap_wdt_disable(wdev);
2817142f	258
d2f78268	259	ret = watchdog_register_device(&wdev->wdog);
1ba85387 AK	260	if (ret) {
	261	pm_runtime_disable(wdev->dev);
	262	return ret;
	263	}
7768a13c	264
2817142f	265	pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n",
4a7e94a0	266	readl_relaxed(wdev->base + OMAP_WATCHDOG_REV) & 0xFF,
d2f78268	267	wdev->wdog.timeout);
7768a13c	268
7ec5ad0f	269	pm_runtime_put_sync(wdev->dev);
789cd470	270
7768a13c	271	return 0;
7768a13c KS	272	}
	273
	274	static void omap_wdt_shutdown(struct platform_device *pdev)
	275	{
d2f78268	276	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
2817142f	277
67c0f554	278	mutex_lock(&wdev->lock);
0503add9	279	if (wdev->omap_wdt_users) {
2817142f	280	omap_wdt_disable(wdev);
0503add9 PW	281	pm_runtime_put_sync(wdev->dev);
0503add9 PW	282	}
67c0f554	283	mutex_unlock(&wdev->lock);
7768a13c KS	284	}
7768a13c KS	285
4b12b896	286	static int omap_wdt_remove(struct platform_device *pdev)
7768a13c	287	{
d2f78268	288	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
2817142f	289
12c583d8	290	pm_runtime_disable(wdev->dev);
d2f78268	291	watchdog_unregister_device(&wdev->wdog);
b3112180	292
7768a13c KS	293	return 0;
	294	}
	295
	296	#ifdef CONFIG_PM
	297
	298	/* REVISIT ... not clear this is the best way to handle system suspend; and
	299	* it's very inappropriate for selective device suspend (e.g. suspending this
	300	* through sysfs rather than by stopping the watchdog daemon). Also, this
	301	* may not play well enough with NOWAYOUT...
	302	*/
	303
	304	static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
	305	{
d2f78268	306	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
b3112180	307
67c0f554	308	mutex_lock(&wdev->lock);
0503add9	309	if (wdev->omap_wdt_users) {
2817142f	310	omap_wdt_disable(wdev);
0503add9 PW	311	pm_runtime_put_sync(wdev->dev);
0503add9 PW	312	}
67c0f554	313	mutex_unlock(&wdev->lock);
b3112180	314
7768a13c KS	315	return 0;
	316	}
	317
	318	static int omap_wdt_resume(struct platform_device *pdev)
	319	{
d2f78268	320	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
b3112180	321
67c0f554	322	mutex_lock(&wdev->lock);
2817142f	323	if (wdev->omap_wdt_users) {
0503add9	324	pm_runtime_get_sync(wdev->dev);
2817142f	325	omap_wdt_enable(wdev);
67c0f554	326	omap_wdt_reload(wdev);
7768a13c	327	}
67c0f554	328	mutex_unlock(&wdev->lock);
b3112180	329
7768a13c KS	330	return 0;
	331	}
	332
	333	#else
	334	#define omap_wdt_suspend NULL
	335	#define omap_wdt_resume NULL
	336	#endif
	337
e6ca04ea XJ	338	static const struct of_device_id omap_wdt_of_match[] = {
	339	{ .compatible = "ti,omap3-wdt", },
	340	{},
	341	};
	342	MODULE_DEVICE_TABLE(of, omap_wdt_of_match);
	343
7768a13c KS	344	static struct platform_driver omap_wdt_driver = {
7768a13c KS	345	.probe = omap_wdt_probe,
82268714	346	.remove = omap_wdt_remove,
7768a13c KS	347	.shutdown = omap_wdt_shutdown,
	348	.suspend = omap_wdt_suspend,
	349	.resume = omap_wdt_resume,
	350	.driver = {
7768a13c	351	.name = "omap_wdt",
e6ca04ea	352	.of_match_table = omap_wdt_of_match,
7768a13c KS	353	},
	354	};
	355
b8ec6118	356	module_platform_driver(omap_wdt_driver);
7768a13c KS	357
	358	MODULE_AUTHOR("George G. Davis");
	359	MODULE_LICENSE("GPL");
f37d193c	360	MODULE_ALIAS("platform:omap_wdt");