Commit | Line | Data |
---|---|---|
7768a13c | 1 | /* |
2817142f | 2 | * omap_wdt.c |
7768a13c | 3 | * |
2817142f | 4 | * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog |
7768a13c KS |
5 | * |
6 | * Author: MontaVista Software, Inc. | |
7 | * <gdavis@mvista.com> or <source@mvista.com> | |
8 | * | |
9 | * 2003 (c) MontaVista Software, Inc. This file is licensed under the | |
10 | * terms of the GNU General Public License version 2. This program is | |
11 | * licensed "as is" without any warranty of any kind, whether express | |
12 | * or implied. | |
13 | * | |
14 | * History: | |
15 | * | |
16 | * 20030527: George G. Davis <gdavis@mvista.com> | |
17 | * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c | |
18 | * (c) Copyright 2000 Oleg Drokin <green@crimea.edu> | |
29fa0586 | 19 | * Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk> |
7768a13c KS |
20 | * |
21 | * Copyright (c) 2004 Texas Instruments. | |
22 | * 1. Modified to support OMAP1610 32-KHz watchdog timer | |
23 | * 2. Ported to 2.6 kernel | |
24 | * | |
25 | * Copyright (c) 2005 David Brownell | |
26 | * Use the driver model and standard identifiers; handle bigger timeouts. | |
27 | */ | |
28 | ||
27c766aa JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
7768a13c | 31 | #include <linux/module.h> |
7768a13c KS |
32 | #include <linux/types.h> |
33 | #include <linux/kernel.h> | |
7768a13c | 34 | #include <linux/mm.h> |
7768a13c KS |
35 | #include <linux/watchdog.h> |
36 | #include <linux/reboot.h> | |
7768a13c KS |
37 | #include <linux/init.h> |
38 | #include <linux/err.h> | |
39 | #include <linux/platform_device.h> | |
40 | #include <linux/moduleparam.h> | |
089ab079 | 41 | #include <linux/io.h> |
5a0e3ad6 | 42 | #include <linux/slab.h> |
7ec5ad0f | 43 | #include <linux/pm_runtime.h> |
129f5577 | 44 | #include <linux/platform_data/omap-wd-timer.h> |
7768a13c KS |
45 | |
46 | #include "omap_wdt.h" | |
47 | ||
2dd7b244 PR |
48 | static bool nowayout = WATCHDOG_NOWAYOUT; |
49 | module_param(nowayout, bool, 0); | |
50 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started " | |
51 | "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
52 | ||
7768a13c KS |
53 | static unsigned timer_margin; |
54 | module_param(timer_margin, uint, 0); | |
55 | MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)"); | |
56 | ||
2817142f FB |
57 | struct omap_wdt_dev { |
58 | void __iomem *base; /* physical */ | |
59 | struct device *dev; | |
67c0f554 | 60 | bool omap_wdt_users; |
2817142f | 61 | struct resource *mem; |
67c0f554 AK |
62 | int wdt_trgr_pattern; |
63 | struct mutex lock; /* to avoid races with PM */ | |
2817142f FB |
64 | }; |
65 | ||
67c0f554 | 66 | static void omap_wdt_reload(struct omap_wdt_dev *wdev) |
7768a13c | 67 | { |
2817142f | 68 | void __iomem *base = wdev->base; |
b3112180 | 69 | |
7768a13c | 70 | /* wait for posted write to complete */ |
9f69e3b0 | 71 | while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08) |
7768a13c | 72 | cpu_relax(); |
b3112180 | 73 | |
67c0f554 AK |
74 | wdev->wdt_trgr_pattern = ~wdev->wdt_trgr_pattern; |
75 | __raw_writel(wdev->wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR)); | |
b3112180 | 76 | |
7768a13c | 77 | /* wait for posted write to complete */ |
9f69e3b0 | 78 | while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08) |
7768a13c KS |
79 | cpu_relax(); |
80 | /* reloaded WCRR from WLDR */ | |
81 | } | |
82 | ||
2817142f | 83 | static void omap_wdt_enable(struct omap_wdt_dev *wdev) |
7768a13c | 84 | { |
b3112180 FB |
85 | void __iomem *base = wdev->base; |
86 | ||
7768a13c | 87 | /* Sequence to enable the watchdog */ |
9f69e3b0 FB |
88 | __raw_writel(0xBBBB, base + OMAP_WATCHDOG_SPR); |
89 | while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10) | |
7768a13c | 90 | cpu_relax(); |
b3112180 | 91 | |
9f69e3b0 FB |
92 | __raw_writel(0x4444, base + OMAP_WATCHDOG_SPR); |
93 | while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10) | |
7768a13c KS |
94 | cpu_relax(); |
95 | } | |
96 | ||
2817142f | 97 | static void omap_wdt_disable(struct omap_wdt_dev *wdev) |
7768a13c | 98 | { |
b3112180 FB |
99 | void __iomem *base = wdev->base; |
100 | ||
7768a13c | 101 | /* sequence required to disable watchdog */ |
9f69e3b0 FB |
102 | __raw_writel(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */ |
103 | while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10) | |
7768a13c | 104 | cpu_relax(); |
b3112180 | 105 | |
9f69e3b0 FB |
106 | __raw_writel(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */ |
107 | while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10) | |
7768a13c KS |
108 | cpu_relax(); |
109 | } | |
110 | ||
67c0f554 AK |
111 | static void omap_wdt_set_timer(struct omap_wdt_dev *wdev, |
112 | unsigned int timeout) | |
7768a13c | 113 | { |
67c0f554 | 114 | u32 pre_margin = GET_WLDR_VAL(timeout); |
b3112180 | 115 | void __iomem *base = wdev->base; |
7768a13c KS |
116 | |
117 | /* just count up at 32 KHz */ | |
9f69e3b0 | 118 | while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04) |
7768a13c | 119 | cpu_relax(); |
b3112180 | 120 | |
9f69e3b0 FB |
121 | __raw_writel(pre_margin, base + OMAP_WATCHDOG_LDR); |
122 | while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04) | |
7768a13c KS |
123 | cpu_relax(); |
124 | } | |
125 | ||
67c0f554 | 126 | static int omap_wdt_start(struct watchdog_device *wdog) |
7768a13c | 127 | { |
67c0f554 | 128 | struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog); |
b3112180 FB |
129 | void __iomem *base = wdev->base; |
130 | ||
67c0f554 AK |
131 | mutex_lock(&wdev->lock); |
132 | ||
133 | wdev->omap_wdt_users = true; | |
7768a13c | 134 | |
7ec5ad0f | 135 | pm_runtime_get_sync(wdev->dev); |
7768a13c KS |
136 | |
137 | /* initialize prescaler */ | |
9f69e3b0 | 138 | while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01) |
7768a13c | 139 | cpu_relax(); |
b3112180 | 140 | |
9f69e3b0 FB |
141 | __raw_writel((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL); |
142 | while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01) | |
7768a13c KS |
143 | cpu_relax(); |
144 | ||
67c0f554 AK |
145 | omap_wdt_set_timer(wdev, wdog->timeout); |
146 | omap_wdt_reload(wdev); /* trigger loading of new timeout value */ | |
2817142f | 147 | omap_wdt_enable(wdev); |
b3112180 | 148 | |
67c0f554 AK |
149 | mutex_unlock(&wdev->lock); |
150 | ||
151 | return 0; | |
7768a13c KS |
152 | } |
153 | ||
67c0f554 | 154 | static int omap_wdt_stop(struct watchdog_device *wdog) |
7768a13c | 155 | { |
67c0f554 | 156 | struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog); |
b3112180 | 157 | |
67c0f554 | 158 | mutex_lock(&wdev->lock); |
2817142f | 159 | omap_wdt_disable(wdev); |
7ec5ad0f | 160 | pm_runtime_put_sync(wdev->dev); |
67c0f554 AK |
161 | wdev->omap_wdt_users = false; |
162 | mutex_unlock(&wdev->lock); | |
7768a13c KS |
163 | return 0; |
164 | } | |
165 | ||
67c0f554 | 166 | static int omap_wdt_ping(struct watchdog_device *wdog) |
7768a13c | 167 | { |
67c0f554 | 168 | struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog); |
b3112180 | 169 | |
67c0f554 AK |
170 | mutex_lock(&wdev->lock); |
171 | omap_wdt_reload(wdev); | |
172 | mutex_unlock(&wdev->lock); | |
173 | ||
174 | return 0; | |
7768a13c KS |
175 | } |
176 | ||
67c0f554 AK |
177 | static int omap_wdt_set_timeout(struct watchdog_device *wdog, |
178 | unsigned int timeout) | |
7768a13c | 179 | { |
67c0f554 | 180 | struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog); |
7768a13c | 181 | |
67c0f554 AK |
182 | mutex_lock(&wdev->lock); |
183 | omap_wdt_disable(wdev); | |
184 | omap_wdt_set_timer(wdev, timeout); | |
185 | omap_wdt_enable(wdev); | |
186 | omap_wdt_reload(wdev); | |
187 | wdog->timeout = timeout; | |
188 | mutex_unlock(&wdev->lock); | |
189 | ||
190 | return 0; | |
7768a13c KS |
191 | } |
192 | ||
67c0f554 AK |
193 | static const struct watchdog_info omap_wdt_info = { |
194 | .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, | |
195 | .identity = "OMAP Watchdog", | |
196 | }; | |
197 | ||
198 | static const struct watchdog_ops omap_wdt_ops = { | |
199 | .owner = THIS_MODULE, | |
200 | .start = omap_wdt_start, | |
201 | .stop = omap_wdt_stop, | |
202 | .ping = omap_wdt_ping, | |
203 | .set_timeout = omap_wdt_set_timeout, | |
7768a13c KS |
204 | }; |
205 | ||
2d991a16 | 206 | static int omap_wdt_probe(struct platform_device *pdev) |
7768a13c | 207 | { |
bc8fdfbe | 208 | struct omap_wd_timer_platform_data *pdata = dev_get_platdata(&pdev->dev); |
67c0f554 | 209 | struct watchdog_device *omap_wdt; |
7768a13c | 210 | struct resource *res, *mem; |
2817142f | 211 | struct omap_wdt_dev *wdev; |
67c0f554 | 212 | u32 rs; |
b3112180 | 213 | int ret; |
7768a13c | 214 | |
4f4753d9 | 215 | omap_wdt = devm_kzalloc(&pdev->dev, sizeof(*omap_wdt), GFP_KERNEL); |
67c0f554 AK |
216 | if (!omap_wdt) |
217 | return -ENOMEM; | |
218 | ||
7768a13c KS |
219 | /* reserve static register mappings */ |
220 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
4f4753d9 AK |
221 | if (!res) |
222 | return -ENOENT; | |
7768a13c | 223 | |
4f4753d9 AK |
224 | mem = devm_request_mem_region(&pdev->dev, res->start, |
225 | resource_size(res), pdev->name); | |
226 | if (!mem) | |
227 | return -EBUSY; | |
7768a13c | 228 | |
4f4753d9 AK |
229 | wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL); |
230 | if (!wdev) | |
231 | return -ENOMEM; | |
b3112180 | 232 | |
67c0f554 AK |
233 | wdev->omap_wdt_users = false; |
234 | wdev->mem = mem; | |
235 | wdev->dev = &pdev->dev; | |
236 | wdev->wdt_trgr_pattern = 0x1234; | |
237 | mutex_init(&wdev->lock); | |
2817142f | 238 | |
4f4753d9 AK |
239 | wdev->base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); |
240 | if (!wdev->base) | |
241 | return -ENOMEM; | |
9f69e3b0 | 242 | |
67c0f554 AK |
243 | omap_wdt->info = &omap_wdt_info; |
244 | omap_wdt->ops = &omap_wdt_ops; | |
245 | omap_wdt->min_timeout = TIMER_MARGIN_MIN; | |
246 | omap_wdt->max_timeout = TIMER_MARGIN_MAX; | |
247 | ||
248 | if (timer_margin >= TIMER_MARGIN_MIN && | |
249 | timer_margin <= TIMER_MARGIN_MAX) | |
250 | omap_wdt->timeout = timer_margin; | |
251 | else | |
252 | omap_wdt->timeout = TIMER_MARGIN_DEFAULT; | |
253 | ||
254 | watchdog_set_drvdata(omap_wdt, wdev); | |
255 | watchdog_set_nowayout(omap_wdt, nowayout); | |
256 | ||
257 | platform_set_drvdata(pdev, omap_wdt); | |
7768a13c | 258 | |
7ec5ad0f VC |
259 | pm_runtime_enable(wdev->dev); |
260 | pm_runtime_get_sync(wdev->dev); | |
789cd470 | 261 | |
67c0f554 AK |
262 | if (pdata && pdata->read_reset_sources) |
263 | rs = pdata->read_reset_sources(); | |
264 | else | |
265 | rs = 0; | |
266 | omap_wdt->bootstatus = (rs & (1 << OMAP_MPU_WD_RST_SRC_ID_SHIFT)) ? | |
267 | WDIOF_CARDRESET : 0; | |
7768a13c | 268 | |
67c0f554 | 269 | omap_wdt_disable(wdev); |
2817142f | 270 | |
67c0f554 | 271 | ret = watchdog_register_device(omap_wdt); |
1ba85387 AK |
272 | if (ret) { |
273 | pm_runtime_disable(wdev->dev); | |
274 | return ret; | |
275 | } | |
7768a13c | 276 | |
2817142f | 277 | pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n", |
9f69e3b0 | 278 | __raw_readl(wdev->base + OMAP_WATCHDOG_REV) & 0xFF, |
67c0f554 | 279 | omap_wdt->timeout); |
7768a13c | 280 | |
7ec5ad0f | 281 | pm_runtime_put_sync(wdev->dev); |
789cd470 | 282 | |
7768a13c | 283 | return 0; |
7768a13c KS |
284 | } |
285 | ||
286 | static void omap_wdt_shutdown(struct platform_device *pdev) | |
287 | { | |
67c0f554 AK |
288 | struct watchdog_device *wdog = platform_get_drvdata(pdev); |
289 | struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog); | |
2817142f | 290 | |
67c0f554 | 291 | mutex_lock(&wdev->lock); |
0503add9 | 292 | if (wdev->omap_wdt_users) { |
2817142f | 293 | omap_wdt_disable(wdev); |
0503add9 PW |
294 | pm_runtime_put_sync(wdev->dev); |
295 | } | |
67c0f554 | 296 | mutex_unlock(&wdev->lock); |
7768a13c KS |
297 | } |
298 | ||
4b12b896 | 299 | static int omap_wdt_remove(struct platform_device *pdev) |
7768a13c | 300 | { |
67c0f554 AK |
301 | struct watchdog_device *wdog = platform_get_drvdata(pdev); |
302 | struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog); | |
2817142f | 303 | |
12c583d8 | 304 | pm_runtime_disable(wdev->dev); |
67c0f554 | 305 | watchdog_unregister_device(wdog); |
b3112180 | 306 | |
7768a13c KS |
307 | return 0; |
308 | } | |
309 | ||
310 | #ifdef CONFIG_PM | |
311 | ||
312 | /* REVISIT ... not clear this is the best way to handle system suspend; and | |
313 | * it's very inappropriate for selective device suspend (e.g. suspending this | |
314 | * through sysfs rather than by stopping the watchdog daemon). Also, this | |
315 | * may not play well enough with NOWAYOUT... | |
316 | */ | |
317 | ||
318 | static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state) | |
319 | { | |
67c0f554 AK |
320 | struct watchdog_device *wdog = platform_get_drvdata(pdev); |
321 | struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog); | |
b3112180 | 322 | |
67c0f554 | 323 | mutex_lock(&wdev->lock); |
0503add9 | 324 | if (wdev->omap_wdt_users) { |
2817142f | 325 | omap_wdt_disable(wdev); |
0503add9 PW |
326 | pm_runtime_put_sync(wdev->dev); |
327 | } | |
67c0f554 | 328 | mutex_unlock(&wdev->lock); |
b3112180 | 329 | |
7768a13c KS |
330 | return 0; |
331 | } | |
332 | ||
333 | static int omap_wdt_resume(struct platform_device *pdev) | |
334 | { | |
67c0f554 AK |
335 | struct watchdog_device *wdog = platform_get_drvdata(pdev); |
336 | struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog); | |
b3112180 | 337 | |
67c0f554 | 338 | mutex_lock(&wdev->lock); |
2817142f | 339 | if (wdev->omap_wdt_users) { |
0503add9 | 340 | pm_runtime_get_sync(wdev->dev); |
2817142f | 341 | omap_wdt_enable(wdev); |
67c0f554 | 342 | omap_wdt_reload(wdev); |
7768a13c | 343 | } |
67c0f554 | 344 | mutex_unlock(&wdev->lock); |
b3112180 | 345 | |
7768a13c KS |
346 | return 0; |
347 | } | |
348 | ||
349 | #else | |
350 | #define omap_wdt_suspend NULL | |
351 | #define omap_wdt_resume NULL | |
352 | #endif | |
353 | ||
e6ca04ea XJ |
354 | static const struct of_device_id omap_wdt_of_match[] = { |
355 | { .compatible = "ti,omap3-wdt", }, | |
356 | {}, | |
357 | }; | |
358 | MODULE_DEVICE_TABLE(of, omap_wdt_of_match); | |
359 | ||
7768a13c KS |
360 | static struct platform_driver omap_wdt_driver = { |
361 | .probe = omap_wdt_probe, | |
82268714 | 362 | .remove = omap_wdt_remove, |
7768a13c KS |
363 | .shutdown = omap_wdt_shutdown, |
364 | .suspend = omap_wdt_suspend, | |
365 | .resume = omap_wdt_resume, | |
366 | .driver = { | |
367 | .owner = THIS_MODULE, | |
368 | .name = "omap_wdt", | |
e6ca04ea | 369 | .of_match_table = omap_wdt_of_match, |
7768a13c KS |
370 | }, |
371 | }; | |
372 | ||
b8ec6118 | 373 | module_platform_driver(omap_wdt_driver); |
7768a13c KS |
374 | |
375 | MODULE_AUTHOR("George G. Davis"); | |
376 | MODULE_LICENSE("GPL"); | |
f37d193c | 377 | MODULE_ALIAS("platform:omap_wdt"); |