Commit | Line | Data |
---|---|---|
22ac9232 | 1 | /* |
3b937a7d | 2 | * drivers/watchdog/orion_wdt.c |
22ac9232 | 3 | * |
3b937a7d | 4 | * Watchdog driver for Orion/Kirkwood processors |
22ac9232 SB |
5 | * |
6 | * Author: Sylver Bruneau <sylver.bruneau@googlemail.com> | |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public | |
9 | * License version 2. This program is licensed "as is" without any | |
10 | * warranty of any kind, whether express or implied. | |
11 | */ | |
12 | ||
27c766aa JP |
13 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
14 | ||
22ac9232 SB |
15 | #include <linux/module.h> |
16 | #include <linux/moduleparam.h> | |
17 | #include <linux/types.h> | |
18 | #include <linux/kernel.h> | |
9e058d4f | 19 | #include <linux/platform_device.h> |
22ac9232 | 20 | #include <linux/watchdog.h> |
e97662e1 | 21 | #include <linux/interrupt.h> |
22ac9232 | 22 | #include <linux/io.h> |
4f04be62 | 23 | #include <linux/clk.h> |
0dd6e484 | 24 | #include <linux/err.h> |
1e7bad0f | 25 | #include <linux/of.h> |
fc723856 | 26 | #include <linux/of_device.h> |
22ac9232 | 27 | |
868eb616 EG |
28 | /* RSTOUT mask register physical address for Orion5x, Kirkwood and Dove */ |
29 | #define ORION_RSTOUT_MASK_OFFSET 0x20108 | |
30 | ||
31 | /* Internal registers can be configured at any 1 MiB aligned address */ | |
32 | #define INTERNAL_REGS_MASK ~(SZ_1M - 1) | |
22ac9232 SB |
33 | |
34 | /* | |
35 | * Watchdog timer block registers. | |
36 | */ | |
a855a7ce | 37 | #define TIMER_CTRL 0x0000 |
463f96e0 | 38 | #define TIMER_A370_STATUS 0x04 |
22ac9232 | 39 | |
9e058d4f | 40 | #define WDT_MAX_CYCLE_COUNT 0xffffffff |
22ac9232 | 41 | |
463f96e0 EG |
42 | #define WDT_A370_RATIO_MASK(v) ((v) << 16) |
43 | #define WDT_A370_RATIO_SHIFT 5 | |
44 | #define WDT_A370_RATIO (1 << WDT_A370_RATIO_SHIFT) | |
45 | ||
46 | #define WDT_AXP_FIXED_ENABLE_BIT BIT(10) | |
47 | #define WDT_A370_EXPIRED BIT(31) | |
fa142ff5 | 48 | |
86a1e189 | 49 | static bool nowayout = WATCHDOG_NOWAYOUT; |
9e058d4f | 50 | static int heartbeat = -1; /* module parameter (seconds) */ |
22ac9232 | 51 | |
1924227b EG |
52 | struct orion_watchdog; |
53 | ||
fc723856 EG |
54 | struct orion_watchdog_data { |
55 | int wdt_counter_offset; | |
56 | int wdt_enable_bit; | |
57 | int rstout_enable_bit; | |
b483642f | 58 | int rstout_mask_bit; |
1924227b EG |
59 | int (*clock_init)(struct platform_device *, |
60 | struct orion_watchdog *); | |
1b0ea574 | 61 | int (*enabled)(struct orion_watchdog *); |
490d8e3c | 62 | int (*start)(struct watchdog_device *); |
ebf5cf76 | 63 | int (*stop)(struct watchdog_device *); |
fc723856 EG |
64 | }; |
65 | ||
b89a9c40 EG |
66 | struct orion_watchdog { |
67 | struct watchdog_device wdt; | |
68 | void __iomem *reg; | |
69 | void __iomem *rstout; | |
b483642f | 70 | void __iomem *rstout_mask; |
b89a9c40 EG |
71 | unsigned long clk_rate; |
72 | struct clk *clk; | |
fc723856 | 73 | const struct orion_watchdog_data *data; |
b89a9c40 | 74 | }; |
22ac9232 | 75 | |
1924227b EG |
76 | static int orion_wdt_clock_init(struct platform_device *pdev, |
77 | struct orion_watchdog *dev) | |
df6707b2 | 78 | { |
1924227b | 79 | int ret; |
df6707b2 | 80 | |
463f96e0 | 81 | dev->clk = clk_get(&pdev->dev, NULL); |
1924227b EG |
82 | if (IS_ERR(dev->clk)) |
83 | return PTR_ERR(dev->clk); | |
84 | ret = clk_prepare_enable(dev->clk); | |
463f96e0 EG |
85 | if (ret) { |
86 | clk_put(dev->clk); | |
1924227b | 87 | return ret; |
463f96e0 | 88 | } |
df6707b2 | 89 | |
463f96e0 | 90 | dev->clk_rate = clk_get_rate(dev->clk); |
0dd6e484 | 91 | return 0; |
df6707b2 TR |
92 | } |
93 | ||
463f96e0 EG |
94 | static int armada370_wdt_clock_init(struct platform_device *pdev, |
95 | struct orion_watchdog *dev) | |
22ac9232 | 96 | { |
463f96e0 | 97 | int ret; |
22ac9232 | 98 | |
463f96e0 EG |
99 | dev->clk = clk_get(&pdev->dev, NULL); |
100 | if (IS_ERR(dev->clk)) | |
101 | return PTR_ERR(dev->clk); | |
102 | ret = clk_prepare_enable(dev->clk); | |
103 | if (ret) { | |
104 | clk_put(dev->clk); | |
105 | return ret; | |
106 | } | |
107 | ||
108 | /* Setup watchdog input clock */ | |
109 | atomic_io_modify(dev->reg + TIMER_CTRL, | |
110 | WDT_A370_RATIO_MASK(WDT_A370_RATIO_SHIFT), | |
111 | WDT_A370_RATIO_MASK(WDT_A370_RATIO_SHIFT)); | |
112 | ||
113 | dev->clk_rate = clk_get_rate(dev->clk) / WDT_A370_RATIO; | |
114 | return 0; | |
115 | } | |
116 | ||
8067042a EG |
117 | static int armada375_wdt_clock_init(struct platform_device *pdev, |
118 | struct orion_watchdog *dev) | |
119 | { | |
120 | int ret; | |
121 | ||
122 | dev->clk = of_clk_get_by_name(pdev->dev.of_node, "fixed"); | |
123 | if (!IS_ERR(dev->clk)) { | |
124 | ret = clk_prepare_enable(dev->clk); | |
125 | if (ret) { | |
126 | clk_put(dev->clk); | |
127 | return ret; | |
128 | } | |
129 | ||
130 | atomic_io_modify(dev->reg + TIMER_CTRL, | |
131 | WDT_AXP_FIXED_ENABLE_BIT, | |
132 | WDT_AXP_FIXED_ENABLE_BIT); | |
133 | dev->clk_rate = clk_get_rate(dev->clk); | |
134 | ||
135 | return 0; | |
136 | } | |
137 | ||
138 | /* Mandatory fallback for proper devicetree backward compatibility */ | |
139 | dev->clk = clk_get(&pdev->dev, NULL); | |
140 | if (IS_ERR(dev->clk)) | |
141 | return PTR_ERR(dev->clk); | |
142 | ||
143 | ret = clk_prepare_enable(dev->clk); | |
144 | if (ret) { | |
145 | clk_put(dev->clk); | |
146 | return ret; | |
147 | } | |
148 | ||
149 | atomic_io_modify(dev->reg + TIMER_CTRL, | |
150 | WDT_A370_RATIO_MASK(WDT_A370_RATIO_SHIFT), | |
151 | WDT_A370_RATIO_MASK(WDT_A370_RATIO_SHIFT)); | |
152 | dev->clk_rate = clk_get_rate(dev->clk) / WDT_A370_RATIO; | |
153 | ||
154 | return 0; | |
155 | } | |
156 | ||
463f96e0 EG |
157 | static int armadaxp_wdt_clock_init(struct platform_device *pdev, |
158 | struct orion_watchdog *dev) | |
159 | { | |
160 | int ret; | |
161 | ||
162 | dev->clk = of_clk_get_by_name(pdev->dev.of_node, "fixed"); | |
163 | if (IS_ERR(dev->clk)) | |
164 | return PTR_ERR(dev->clk); | |
165 | ret = clk_prepare_enable(dev->clk); | |
166 | if (ret) { | |
167 | clk_put(dev->clk); | |
168 | return ret; | |
169 | } | |
170 | ||
171 | /* Enable the fixed watchdog clock input */ | |
172 | atomic_io_modify(dev->reg + TIMER_CTRL, | |
173 | WDT_AXP_FIXED_ENABLE_BIT, | |
174 | WDT_AXP_FIXED_ENABLE_BIT); | |
1924227b EG |
175 | |
176 | dev->clk_rate = clk_get_rate(dev->clk); | |
177 | return 0; | |
178 | } | |
179 | ||
0dd6e484 | 180 | static int orion_wdt_ping(struct watchdog_device *wdt_dev) |
df6707b2 | 181 | { |
b89a9c40 | 182 | struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev); |
df6707b2 | 183 | /* Reload watchdog duration */ |
fc723856 EG |
184 | writel(dev->clk_rate * wdt_dev->timeout, |
185 | dev->reg + dev->data->wdt_counter_offset); | |
0dd6e484 | 186 | return 0; |
df6707b2 TR |
187 | } |
188 | ||
b483642f EG |
189 | static int armada375_start(struct watchdog_device *wdt_dev) |
190 | { | |
191 | struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev); | |
192 | u32 reg; | |
193 | ||
194 | /* Set watchdog duration */ | |
195 | writel(dev->clk_rate * wdt_dev->timeout, | |
196 | dev->reg + dev->data->wdt_counter_offset); | |
197 | ||
198 | /* Clear the watchdog expiration bit */ | |
199 | atomic_io_modify(dev->reg + TIMER_A370_STATUS, WDT_A370_EXPIRED, 0); | |
200 | ||
201 | /* Enable watchdog timer */ | |
202 | atomic_io_modify(dev->reg + TIMER_CTRL, dev->data->wdt_enable_bit, | |
203 | dev->data->wdt_enable_bit); | |
204 | ||
205 | /* Enable reset on watchdog */ | |
206 | reg = readl(dev->rstout); | |
207 | reg |= dev->data->rstout_enable_bit; | |
208 | writel(reg, dev->rstout); | |
209 | ||
210 | atomic_io_modify(dev->rstout_mask, dev->data->rstout_mask_bit, 0); | |
211 | return 0; | |
212 | } | |
213 | ||
463f96e0 EG |
214 | static int armada370_start(struct watchdog_device *wdt_dev) |
215 | { | |
216 | struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev); | |
eba985e2 | 217 | u32 reg; |
6d0f0dfd | 218 | |
22ac9232 | 219 | /* Set watchdog duration */ |
463f96e0 EG |
220 | writel(dev->clk_rate * wdt_dev->timeout, |
221 | dev->reg + dev->data->wdt_counter_offset); | |
22ac9232 | 222 | |
463f96e0 EG |
223 | /* Clear the watchdog expiration bit */ |
224 | atomic_io_modify(dev->reg + TIMER_A370_STATUS, WDT_A370_EXPIRED, 0); | |
22ac9232 SB |
225 | |
226 | /* Enable watchdog timer */ | |
463f96e0 EG |
227 | atomic_io_modify(dev->reg + TIMER_CTRL, dev->data->wdt_enable_bit, |
228 | dev->data->wdt_enable_bit); | |
229 | ||
eba985e2 EG |
230 | /* Enable reset on watchdog */ |
231 | reg = readl(dev->rstout); | |
232 | reg |= dev->data->rstout_enable_bit; | |
233 | writel(reg, dev->rstout); | |
463f96e0 EG |
234 | return 0; |
235 | } | |
236 | ||
490d8e3c | 237 | static int orion_start(struct watchdog_device *wdt_dev) |
22ac9232 | 238 | { |
b89a9c40 EG |
239 | struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev); |
240 | ||
22ac9232 | 241 | /* Set watchdog duration */ |
fc723856 EG |
242 | writel(dev->clk_rate * wdt_dev->timeout, |
243 | dev->reg + dev->data->wdt_counter_offset); | |
22ac9232 | 244 | |
22ac9232 | 245 | /* Enable watchdog timer */ |
fc723856 EG |
246 | atomic_io_modify(dev->reg + TIMER_CTRL, dev->data->wdt_enable_bit, |
247 | dev->data->wdt_enable_bit); | |
22ac9232 SB |
248 | |
249 | /* Enable reset on watchdog */ | |
fc723856 EG |
250 | atomic_io_modify(dev->rstout, dev->data->rstout_enable_bit, |
251 | dev->data->rstout_enable_bit); | |
6d0f0dfd | 252 | |
0dd6e484 | 253 | return 0; |
22ac9232 SB |
254 | } |
255 | ||
490d8e3c | 256 | static int orion_wdt_start(struct watchdog_device *wdt_dev) |
22ac9232 | 257 | { |
490d8e3c | 258 | struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev); |
22ac9232 | 259 | |
490d8e3c EG |
260 | /* There are some per-SoC quirks to handle */ |
261 | return dev->data->start(wdt_dev); | |
262 | } | |
263 | ||
ebf5cf76 | 264 | static int orion_stop(struct watchdog_device *wdt_dev) |
22ac9232 | 265 | { |
b89a9c40 | 266 | struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev); |
6d0f0dfd | 267 | |
22ac9232 | 268 | /* Disable reset on watchdog */ |
fc723856 | 269 | atomic_io_modify(dev->rstout, dev->data->rstout_enable_bit, 0); |
22ac9232 SB |
270 | |
271 | /* Disable watchdog timer */ | |
fc723856 | 272 | atomic_io_modify(dev->reg + TIMER_CTRL, dev->data->wdt_enable_bit, 0); |
6d0f0dfd | 273 | |
0dd6e484 | 274 | return 0; |
6d0f0dfd WVS |
275 | } |
276 | ||
b483642f EG |
277 | static int armada375_stop(struct watchdog_device *wdt_dev) |
278 | { | |
279 | struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev); | |
280 | u32 reg; | |
281 | ||
282 | /* Disable reset on watchdog */ | |
283 | atomic_io_modify(dev->rstout_mask, dev->data->rstout_mask_bit, | |
284 | dev->data->rstout_mask_bit); | |
285 | reg = readl(dev->rstout); | |
286 | reg &= ~dev->data->rstout_enable_bit; | |
287 | writel(reg, dev->rstout); | |
288 | ||
289 | /* Disable watchdog timer */ | |
290 | atomic_io_modify(dev->reg + TIMER_CTRL, dev->data->wdt_enable_bit, 0); | |
291 | ||
292 | return 0; | |
293 | } | |
294 | ||
ebf5cf76 EG |
295 | static int armada370_stop(struct watchdog_device *wdt_dev) |
296 | { | |
297 | struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev); | |
298 | u32 reg; | |
299 | ||
300 | /* Disable reset on watchdog */ | |
301 | reg = readl(dev->rstout); | |
302 | reg &= ~dev->data->rstout_enable_bit; | |
303 | writel(reg, dev->rstout); | |
304 | ||
305 | /* Disable watchdog timer */ | |
306 | atomic_io_modify(dev->reg + TIMER_CTRL, dev->data->wdt_enable_bit, 0); | |
307 | ||
308 | return 0; | |
309 | } | |
310 | ||
311 | static int orion_wdt_stop(struct watchdog_device *wdt_dev) | |
312 | { | |
313 | struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev); | |
314 | ||
315 | return dev->data->stop(wdt_dev); | |
316 | } | |
317 | ||
1b0ea574 | 318 | static int orion_enabled(struct orion_watchdog *dev) |
6d0f0dfd | 319 | { |
d9d0c53d EG |
320 | bool enabled, running; |
321 | ||
fc723856 EG |
322 | enabled = readl(dev->rstout) & dev->data->rstout_enable_bit; |
323 | running = readl(dev->reg + TIMER_CTRL) & dev->data->wdt_enable_bit; | |
0dd6e484 | 324 | |
d9d0c53d EG |
325 | return enabled && running; |
326 | } | |
22ac9232 | 327 | |
b483642f EG |
328 | static int armada375_enabled(struct orion_watchdog *dev) |
329 | { | |
330 | bool masked, enabled, running; | |
331 | ||
332 | masked = readl(dev->rstout_mask) & dev->data->rstout_mask_bit; | |
333 | enabled = readl(dev->rstout) & dev->data->rstout_enable_bit; | |
334 | running = readl(dev->reg + TIMER_CTRL) & dev->data->wdt_enable_bit; | |
335 | ||
336 | return !masked && enabled && running; | |
337 | } | |
338 | ||
1b0ea574 EG |
339 | static int orion_wdt_enabled(struct watchdog_device *wdt_dev) |
340 | { | |
341 | struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev); | |
342 | ||
343 | return dev->data->enabled(dev); | |
344 | } | |
345 | ||
0dd6e484 | 346 | static unsigned int orion_wdt_get_timeleft(struct watchdog_device *wdt_dev) |
6d0f0dfd | 347 | { |
b89a9c40 | 348 | struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev); |
fc723856 | 349 | return readl(dev->reg + dev->data->wdt_counter_offset) / dev->clk_rate; |
22ac9232 SB |
350 | } |
351 | ||
0dd6e484 AL |
352 | static int orion_wdt_set_timeout(struct watchdog_device *wdt_dev, |
353 | unsigned int timeout) | |
22ac9232 | 354 | { |
0dd6e484 | 355 | wdt_dev->timeout = timeout; |
df6707b2 TR |
356 | return 0; |
357 | } | |
358 | ||
0dd6e484 AL |
359 | static const struct watchdog_info orion_wdt_info = { |
360 | .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, | |
361 | .identity = "Orion Watchdog", | |
22ac9232 SB |
362 | }; |
363 | ||
0dd6e484 AL |
364 | static const struct watchdog_ops orion_wdt_ops = { |
365 | .owner = THIS_MODULE, | |
366 | .start = orion_wdt_start, | |
367 | .stop = orion_wdt_stop, | |
368 | .ping = orion_wdt_ping, | |
369 | .set_timeout = orion_wdt_set_timeout, | |
370 | .get_timeleft = orion_wdt_get_timeleft, | |
22ac9232 SB |
371 | }; |
372 | ||
e97662e1 EG |
373 | static irqreturn_t orion_wdt_irq(int irq, void *devid) |
374 | { | |
375 | panic("Watchdog Timeout"); | |
376 | return IRQ_HANDLED; | |
377 | } | |
378 | ||
868eb616 EG |
379 | /* |
380 | * The original devicetree binding for this driver specified only | |
381 | * one memory resource, so in order to keep DT backwards compatibility | |
382 | * we try to fallback to a hardcoded register address, if the resource | |
383 | * is missing from the devicetree. | |
384 | */ | |
385 | static void __iomem *orion_wdt_ioremap_rstout(struct platform_device *pdev, | |
386 | phys_addr_t internal_regs) | |
387 | { | |
388 | struct resource *res; | |
389 | phys_addr_t rstout; | |
390 | ||
391 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
392 | if (res) | |
393 | return devm_ioremap(&pdev->dev, res->start, | |
394 | resource_size(res)); | |
395 | ||
868eb616 EG |
396 | rstout = internal_regs + ORION_RSTOUT_MASK_OFFSET; |
397 | ||
edd9d3cf | 398 | WARN(1, FW_BUG "falling back to harcoded RSTOUT reg %pa\n", &rstout); |
868eb616 EG |
399 | return devm_ioremap(&pdev->dev, rstout, 0x4); |
400 | } | |
401 | ||
fc723856 EG |
402 | static const struct orion_watchdog_data orion_data = { |
403 | .rstout_enable_bit = BIT(1), | |
404 | .wdt_enable_bit = BIT(4), | |
405 | .wdt_counter_offset = 0x24, | |
1924227b | 406 | .clock_init = orion_wdt_clock_init, |
1b0ea574 | 407 | .enabled = orion_enabled, |
490d8e3c | 408 | .start = orion_start, |
ebf5cf76 | 409 | .stop = orion_stop, |
fc723856 EG |
410 | }; |
411 | ||
463f96e0 EG |
412 | static const struct orion_watchdog_data armada370_data = { |
413 | .rstout_enable_bit = BIT(8), | |
414 | .wdt_enable_bit = BIT(8), | |
415 | .wdt_counter_offset = 0x34, | |
416 | .clock_init = armada370_wdt_clock_init, | |
1b0ea574 | 417 | .enabled = orion_enabled, |
463f96e0 | 418 | .start = armada370_start, |
ebf5cf76 | 419 | .stop = armada370_stop, |
22ac9232 SB |
420 | }; |
421 | ||
463f96e0 EG |
422 | static const struct orion_watchdog_data armadaxp_data = { |
423 | .rstout_enable_bit = BIT(8), | |
424 | .wdt_enable_bit = BIT(8), | |
425 | .wdt_counter_offset = 0x34, | |
426 | .clock_init = armadaxp_wdt_clock_init, | |
1b0ea574 | 427 | .enabled = orion_enabled, |
463f96e0 | 428 | .start = armada370_start, |
ebf5cf76 | 429 | .stop = armada370_stop, |
463f96e0 EG |
430 | }; |
431 | ||
b483642f EG |
432 | static const struct orion_watchdog_data armada375_data = { |
433 | .rstout_enable_bit = BIT(8), | |
434 | .rstout_mask_bit = BIT(10), | |
435 | .wdt_enable_bit = BIT(8), | |
436 | .wdt_counter_offset = 0x34, | |
8067042a | 437 | .clock_init = armada375_wdt_clock_init, |
b483642f EG |
438 | .enabled = armada375_enabled, |
439 | .start = armada375_start, | |
440 | .stop = armada375_stop, | |
441 | }; | |
442 | ||
443 | static const struct orion_watchdog_data armada380_data = { | |
444 | .rstout_enable_bit = BIT(8), | |
445 | .rstout_mask_bit = BIT(10), | |
446 | .wdt_enable_bit = BIT(8), | |
447 | .wdt_counter_offset = 0x34, | |
448 | .clock_init = armadaxp_wdt_clock_init, | |
449 | .enabled = armada375_enabled, | |
450 | .start = armada375_start, | |
451 | .stop = armada375_stop, | |
452 | }; | |
453 | ||
fc723856 EG |
454 | static const struct of_device_id orion_wdt_of_match_table[] = { |
455 | { | |
456 | .compatible = "marvell,orion-wdt", | |
457 | .data = &orion_data, | |
458 | }, | |
463f96e0 EG |
459 | { |
460 | .compatible = "marvell,armada-370-wdt", | |
461 | .data = &armada370_data, | |
462 | }, | |
463 | { | |
464 | .compatible = "marvell,armada-xp-wdt", | |
465 | .data = &armadaxp_data, | |
466 | }, | |
b483642f EG |
467 | { |
468 | .compatible = "marvell,armada-375-wdt", | |
469 | .data = &armada375_data, | |
470 | }, | |
471 | { | |
472 | .compatible = "marvell,armada-380-wdt", | |
473 | .data = &armada380_data, | |
474 | }, | |
fc723856 EG |
475 | {}, |
476 | }; | |
477 | MODULE_DEVICE_TABLE(of, orion_wdt_of_match_table); | |
478 | ||
aaaac9ec EG |
479 | static int orion_wdt_get_regs(struct platform_device *pdev, |
480 | struct orion_watchdog *dev) | |
481 | { | |
92d4fc1a | 482 | struct device_node *node = pdev->dev.of_node; |
aaaac9ec EG |
483 | struct resource *res; |
484 | ||
485 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
486 | if (!res) | |
487 | return -ENODEV; | |
488 | dev->reg = devm_ioremap(&pdev->dev, res->start, | |
489 | resource_size(res)); | |
490 | if (!dev->reg) | |
491 | return -ENOMEM; | |
492 | ||
92d4fc1a EG |
493 | /* Each supported compatible has some RSTOUT register quirk */ |
494 | if (of_device_is_compatible(node, "marvell,orion-wdt")) { | |
495 | ||
496 | dev->rstout = orion_wdt_ioremap_rstout(pdev, res->start & | |
497 | INTERNAL_REGS_MASK); | |
498 | if (!dev->rstout) | |
499 | return -ENODEV; | |
500 | ||
501 | } else if (of_device_is_compatible(node, "marvell,armada-370-wdt") || | |
502 | of_device_is_compatible(node, "marvell,armada-xp-wdt")) { | |
503 | ||
504 | /* Dedicated RSTOUT register, can be requested. */ | |
505 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
506 | dev->rstout = devm_ioremap_resource(&pdev->dev, res); | |
507 | if (IS_ERR(dev->rstout)) | |
508 | return PTR_ERR(dev->rstout); | |
509 | ||
b483642f EG |
510 | } else if (of_device_is_compatible(node, "marvell,armada-375-wdt") || |
511 | of_device_is_compatible(node, "marvell,armada-380-wdt")) { | |
512 | ||
513 | /* Dedicated RSTOUT register, can be requested. */ | |
514 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
515 | dev->rstout = devm_ioremap_resource(&pdev->dev, res); | |
516 | if (IS_ERR(dev->rstout)) | |
517 | return PTR_ERR(dev->rstout); | |
518 | ||
519 | res = platform_get_resource(pdev, IORESOURCE_MEM, 2); | |
520 | if (!res) | |
521 | return -ENODEV; | |
522 | dev->rstout_mask = devm_ioremap(&pdev->dev, res->start, | |
523 | resource_size(res)); | |
524 | if (!dev->rstout_mask) | |
525 | return -ENOMEM; | |
526 | ||
92d4fc1a | 527 | } else { |
aaaac9ec | 528 | return -ENODEV; |
92d4fc1a | 529 | } |
aaaac9ec EG |
530 | |
531 | return 0; | |
532 | } | |
533 | ||
2d991a16 | 534 | static int orion_wdt_probe(struct platform_device *pdev) |
22ac9232 | 535 | { |
b89a9c40 | 536 | struct orion_watchdog *dev; |
fc723856 | 537 | const struct of_device_id *match; |
b89a9c40 | 538 | unsigned int wdt_max_duration; /* (seconds) */ |
e97662e1 | 539 | int ret, irq; |
22ac9232 | 540 | |
b89a9c40 EG |
541 | dev = devm_kzalloc(&pdev->dev, sizeof(struct orion_watchdog), |
542 | GFP_KERNEL); | |
543 | if (!dev) | |
544 | return -ENOMEM; | |
545 | ||
fc723856 EG |
546 | match = of_match_device(orion_wdt_of_match_table, &pdev->dev); |
547 | if (!match) | |
548 | /* Default legacy match */ | |
549 | match = &orion_wdt_of_match_table[0]; | |
550 | ||
b89a9c40 EG |
551 | dev->wdt.info = &orion_wdt_info; |
552 | dev->wdt.ops = &orion_wdt_ops; | |
553 | dev->wdt.min_timeout = 1; | |
fc723856 | 554 | dev->data = match->data; |
9e058d4f | 555 | |
aaaac9ec EG |
556 | ret = orion_wdt_get_regs(pdev, dev); |
557 | if (ret) | |
558 | return ret; | |
0dd6e484 | 559 | |
1924227b | 560 | ret = dev->data->clock_init(pdev, dev); |
0dd6e484 | 561 | if (ret) { |
1924227b | 562 | dev_err(&pdev->dev, "cannot initialize clock\n"); |
9e058d4f | 563 | return ret; |
0dd6e484 | 564 | } |
9e058d4f | 565 | |
b89a9c40 EG |
566 | wdt_max_duration = WDT_MAX_CYCLE_COUNT / dev->clk_rate; |
567 | ||
568 | dev->wdt.timeout = wdt_max_duration; | |
569 | dev->wdt.max_timeout = wdt_max_duration; | |
6551881c | 570 | dev->wdt.parent = &pdev->dev; |
b89a9c40 | 571 | watchdog_init_timeout(&dev->wdt, heartbeat, &pdev->dev); |
0dd6e484 | 572 | |
b89a9c40 EG |
573 | platform_set_drvdata(pdev, &dev->wdt); |
574 | watchdog_set_drvdata(&dev->wdt, dev); | |
0dd6e484 | 575 | |
d9d0c53d EG |
576 | /* |
577 | * Let's make sure the watchdog is fully stopped, unless it's | |
578 | * explicitly enabled. This may be the case if the module was | |
579 | * removed and re-insterted, or if the bootloader explicitly | |
580 | * set a running watchdog before booting the kernel. | |
581 | */ | |
1b0ea574 | 582 | if (!orion_wdt_enabled(&dev->wdt)) |
b89a9c40 | 583 | orion_wdt_stop(&dev->wdt); |
d9d0c53d | 584 | |
e97662e1 EG |
585 | /* Request the IRQ only after the watchdog is disabled */ |
586 | irq = platform_get_irq(pdev, 0); | |
587 | if (irq > 0) { | |
588 | /* | |
589 | * Not all supported platforms specify an interrupt for the | |
590 | * watchdog, so let's make it optional. | |
591 | */ | |
592 | ret = devm_request_irq(&pdev->dev, irq, orion_wdt_irq, 0, | |
b89a9c40 | 593 | pdev->name, dev); |
e97662e1 EG |
594 | if (ret < 0) { |
595 | dev_err(&pdev->dev, "failed to request IRQ\n"); | |
596 | goto disable_clk; | |
597 | } | |
598 | } | |
599 | ||
b89a9c40 EG |
600 | watchdog_set_nowayout(&dev->wdt, nowayout); |
601 | ret = watchdog_register_device(&dev->wdt); | |
bb02c662 EG |
602 | if (ret) |
603 | goto disable_clk; | |
9e058d4f | 604 | |
27c766aa | 605 | pr_info("Initial timeout %d sec%s\n", |
b89a9c40 | 606 | dev->wdt.timeout, nowayout ? ", nowayout" : ""); |
9e058d4f | 607 | return 0; |
bb02c662 EG |
608 | |
609 | disable_clk: | |
b89a9c40 | 610 | clk_disable_unprepare(dev->clk); |
463f96e0 | 611 | clk_put(dev->clk); |
bb02c662 | 612 | return ret; |
9e058d4f TR |
613 | } |
614 | ||
4b12b896 | 615 | static int orion_wdt_remove(struct platform_device *pdev) |
9e058d4f | 616 | { |
b89a9c40 EG |
617 | struct watchdog_device *wdt_dev = platform_get_drvdata(pdev); |
618 | struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev); | |
619 | ||
620 | watchdog_unregister_device(wdt_dev); | |
621 | clk_disable_unprepare(dev->clk); | |
463f96e0 | 622 | clk_put(dev->clk); |
0dd6e484 | 623 | return 0; |
22ac9232 SB |
624 | } |
625 | ||
3b937a7d | 626 | static void orion_wdt_shutdown(struct platform_device *pdev) |
df6707b2 | 627 | { |
b89a9c40 EG |
628 | struct watchdog_device *wdt_dev = platform_get_drvdata(pdev); |
629 | orion_wdt_stop(wdt_dev); | |
df6707b2 TR |
630 | } |
631 | ||
3b937a7d NP |
632 | static struct platform_driver orion_wdt_driver = { |
633 | .probe = orion_wdt_probe, | |
82268714 | 634 | .remove = orion_wdt_remove, |
3b937a7d | 635 | .shutdown = orion_wdt_shutdown, |
9e058d4f | 636 | .driver = { |
3b937a7d | 637 | .name = "orion_wdt", |
85eee819 | 638 | .of_match_table = orion_wdt_of_match_table, |
9e058d4f TR |
639 | }, |
640 | }; | |
641 | ||
b8ec6118 | 642 | module_platform_driver(orion_wdt_driver); |
22ac9232 SB |
643 | |
644 | MODULE_AUTHOR("Sylver Bruneau <sylver.bruneau@googlemail.com>"); | |
3b937a7d | 645 | MODULE_DESCRIPTION("Orion Processor Watchdog"); |
22ac9232 SB |
646 | |
647 | module_param(heartbeat, int, 0); | |
df6707b2 | 648 | MODULE_PARM_DESC(heartbeat, "Initial watchdog heartbeat in seconds"); |
22ac9232 | 649 | |
86a1e189 | 650 | module_param(nowayout, bool, 0); |
df6707b2 TR |
651 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" |
652 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
22ac9232 SB |
653 | |
654 | MODULE_LICENSE("GPL"); | |
f3ea733e | 655 | MODULE_ALIAS("platform:orion_wdt"); |