Commit | Line | Data |
---|---|---|
22ac9232 | 1 | /* |
3b937a7d | 2 | * drivers/watchdog/orion_wdt.c |
22ac9232 | 3 | * |
3b937a7d | 4 | * Watchdog driver for Orion/Kirkwood processors |
22ac9232 SB |
5 | * |
6 | * Author: Sylver Bruneau <sylver.bruneau@googlemail.com> | |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public | |
9 | * License version 2. This program is licensed "as is" without any | |
10 | * warranty of any kind, whether express or implied. | |
11 | */ | |
12 | ||
27c766aa JP |
13 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
14 | ||
22ac9232 SB |
15 | #include <linux/module.h> |
16 | #include <linux/moduleparam.h> | |
17 | #include <linux/types.h> | |
18 | #include <linux/kernel.h> | |
9e058d4f | 19 | #include <linux/platform_device.h> |
22ac9232 | 20 | #include <linux/watchdog.h> |
e97662e1 | 21 | #include <linux/interrupt.h> |
22ac9232 | 22 | #include <linux/io.h> |
4f04be62 | 23 | #include <linux/clk.h> |
0dd6e484 | 24 | #include <linux/err.h> |
1e7bad0f | 25 | #include <linux/of.h> |
fc723856 | 26 | #include <linux/of_device.h> |
22ac9232 | 27 | |
868eb616 EG |
28 | /* RSTOUT mask register physical address for Orion5x, Kirkwood and Dove */ |
29 | #define ORION_RSTOUT_MASK_OFFSET 0x20108 | |
30 | ||
31 | /* Internal registers can be configured at any 1 MiB aligned address */ | |
32 | #define INTERNAL_REGS_MASK ~(SZ_1M - 1) | |
22ac9232 SB |
33 | |
34 | /* | |
35 | * Watchdog timer block registers. | |
36 | */ | |
a855a7ce | 37 | #define TIMER_CTRL 0x0000 |
463f96e0 | 38 | #define TIMER_A370_STATUS 0x04 |
22ac9232 | 39 | |
9e058d4f | 40 | #define WDT_MAX_CYCLE_COUNT 0xffffffff |
22ac9232 | 41 | |
463f96e0 EG |
42 | #define WDT_A370_RATIO_MASK(v) ((v) << 16) |
43 | #define WDT_A370_RATIO_SHIFT 5 | |
44 | #define WDT_A370_RATIO (1 << WDT_A370_RATIO_SHIFT) | |
45 | ||
46 | #define WDT_AXP_FIXED_ENABLE_BIT BIT(10) | |
47 | #define WDT_A370_EXPIRED BIT(31) | |
fa142ff5 | 48 | |
86a1e189 | 49 | static bool nowayout = WATCHDOG_NOWAYOUT; |
9e058d4f | 50 | static int heartbeat = -1; /* module parameter (seconds) */ |
22ac9232 | 51 | |
1924227b EG |
52 | struct orion_watchdog; |
53 | ||
fc723856 EG |
54 | struct orion_watchdog_data { |
55 | int wdt_counter_offset; | |
56 | int wdt_enable_bit; | |
57 | int rstout_enable_bit; | |
1924227b EG |
58 | int (*clock_init)(struct platform_device *, |
59 | struct orion_watchdog *); | |
1b0ea574 | 60 | int (*enabled)(struct orion_watchdog *); |
490d8e3c | 61 | int (*start)(struct watchdog_device *); |
ebf5cf76 | 62 | int (*stop)(struct watchdog_device *); |
fc723856 EG |
63 | }; |
64 | ||
b89a9c40 EG |
65 | struct orion_watchdog { |
66 | struct watchdog_device wdt; | |
67 | void __iomem *reg; | |
68 | void __iomem *rstout; | |
69 | unsigned long clk_rate; | |
70 | struct clk *clk; | |
fc723856 | 71 | const struct orion_watchdog_data *data; |
b89a9c40 | 72 | }; |
22ac9232 | 73 | |
1924227b EG |
74 | static int orion_wdt_clock_init(struct platform_device *pdev, |
75 | struct orion_watchdog *dev) | |
df6707b2 | 76 | { |
1924227b | 77 | int ret; |
df6707b2 | 78 | |
463f96e0 | 79 | dev->clk = clk_get(&pdev->dev, NULL); |
1924227b EG |
80 | if (IS_ERR(dev->clk)) |
81 | return PTR_ERR(dev->clk); | |
82 | ret = clk_prepare_enable(dev->clk); | |
463f96e0 EG |
83 | if (ret) { |
84 | clk_put(dev->clk); | |
1924227b | 85 | return ret; |
463f96e0 | 86 | } |
df6707b2 | 87 | |
463f96e0 | 88 | dev->clk_rate = clk_get_rate(dev->clk); |
0dd6e484 | 89 | return 0; |
df6707b2 TR |
90 | } |
91 | ||
463f96e0 EG |
92 | static int armada370_wdt_clock_init(struct platform_device *pdev, |
93 | struct orion_watchdog *dev) | |
22ac9232 | 94 | { |
463f96e0 | 95 | int ret; |
22ac9232 | 96 | |
463f96e0 EG |
97 | dev->clk = clk_get(&pdev->dev, NULL); |
98 | if (IS_ERR(dev->clk)) | |
99 | return PTR_ERR(dev->clk); | |
100 | ret = clk_prepare_enable(dev->clk); | |
101 | if (ret) { | |
102 | clk_put(dev->clk); | |
103 | return ret; | |
104 | } | |
105 | ||
106 | /* Setup watchdog input clock */ | |
107 | atomic_io_modify(dev->reg + TIMER_CTRL, | |
108 | WDT_A370_RATIO_MASK(WDT_A370_RATIO_SHIFT), | |
109 | WDT_A370_RATIO_MASK(WDT_A370_RATIO_SHIFT)); | |
110 | ||
111 | dev->clk_rate = clk_get_rate(dev->clk) / WDT_A370_RATIO; | |
112 | return 0; | |
113 | } | |
114 | ||
115 | static int armadaxp_wdt_clock_init(struct platform_device *pdev, | |
116 | struct orion_watchdog *dev) | |
117 | { | |
118 | int ret; | |
119 | ||
120 | dev->clk = of_clk_get_by_name(pdev->dev.of_node, "fixed"); | |
121 | if (IS_ERR(dev->clk)) | |
122 | return PTR_ERR(dev->clk); | |
123 | ret = clk_prepare_enable(dev->clk); | |
124 | if (ret) { | |
125 | clk_put(dev->clk); | |
126 | return ret; | |
127 | } | |
128 | ||
129 | /* Enable the fixed watchdog clock input */ | |
130 | atomic_io_modify(dev->reg + TIMER_CTRL, | |
131 | WDT_AXP_FIXED_ENABLE_BIT, | |
132 | WDT_AXP_FIXED_ENABLE_BIT); | |
1924227b EG |
133 | |
134 | dev->clk_rate = clk_get_rate(dev->clk); | |
135 | return 0; | |
136 | } | |
137 | ||
0dd6e484 | 138 | static int orion_wdt_ping(struct watchdog_device *wdt_dev) |
df6707b2 | 139 | { |
b89a9c40 | 140 | struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev); |
df6707b2 | 141 | /* Reload watchdog duration */ |
fc723856 EG |
142 | writel(dev->clk_rate * wdt_dev->timeout, |
143 | dev->reg + dev->data->wdt_counter_offset); | |
0dd6e484 | 144 | return 0; |
df6707b2 TR |
145 | } |
146 | ||
463f96e0 EG |
147 | static int armada370_start(struct watchdog_device *wdt_dev) |
148 | { | |
149 | struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev); | |
eba985e2 | 150 | u32 reg; |
6d0f0dfd | 151 | |
22ac9232 | 152 | /* Set watchdog duration */ |
463f96e0 EG |
153 | writel(dev->clk_rate * wdt_dev->timeout, |
154 | dev->reg + dev->data->wdt_counter_offset); | |
22ac9232 | 155 | |
463f96e0 EG |
156 | /* Clear the watchdog expiration bit */ |
157 | atomic_io_modify(dev->reg + TIMER_A370_STATUS, WDT_A370_EXPIRED, 0); | |
22ac9232 SB |
158 | |
159 | /* Enable watchdog timer */ | |
463f96e0 EG |
160 | atomic_io_modify(dev->reg + TIMER_CTRL, dev->data->wdt_enable_bit, |
161 | dev->data->wdt_enable_bit); | |
162 | ||
eba985e2 EG |
163 | /* Enable reset on watchdog */ |
164 | reg = readl(dev->rstout); | |
165 | reg |= dev->data->rstout_enable_bit; | |
166 | writel(reg, dev->rstout); | |
463f96e0 EG |
167 | return 0; |
168 | } | |
169 | ||
490d8e3c | 170 | static int orion_start(struct watchdog_device *wdt_dev) |
22ac9232 | 171 | { |
b89a9c40 EG |
172 | struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev); |
173 | ||
22ac9232 | 174 | /* Set watchdog duration */ |
fc723856 EG |
175 | writel(dev->clk_rate * wdt_dev->timeout, |
176 | dev->reg + dev->data->wdt_counter_offset); | |
22ac9232 | 177 | |
22ac9232 | 178 | /* Enable watchdog timer */ |
fc723856 EG |
179 | atomic_io_modify(dev->reg + TIMER_CTRL, dev->data->wdt_enable_bit, |
180 | dev->data->wdt_enable_bit); | |
22ac9232 SB |
181 | |
182 | /* Enable reset on watchdog */ | |
fc723856 EG |
183 | atomic_io_modify(dev->rstout, dev->data->rstout_enable_bit, |
184 | dev->data->rstout_enable_bit); | |
6d0f0dfd | 185 | |
0dd6e484 | 186 | return 0; |
22ac9232 SB |
187 | } |
188 | ||
490d8e3c | 189 | static int orion_wdt_start(struct watchdog_device *wdt_dev) |
22ac9232 | 190 | { |
490d8e3c | 191 | struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev); |
22ac9232 | 192 | |
490d8e3c EG |
193 | /* There are some per-SoC quirks to handle */ |
194 | return dev->data->start(wdt_dev); | |
195 | } | |
196 | ||
ebf5cf76 | 197 | static int orion_stop(struct watchdog_device *wdt_dev) |
22ac9232 | 198 | { |
b89a9c40 | 199 | struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev); |
6d0f0dfd | 200 | |
22ac9232 | 201 | /* Disable reset on watchdog */ |
fc723856 | 202 | atomic_io_modify(dev->rstout, dev->data->rstout_enable_bit, 0); |
22ac9232 SB |
203 | |
204 | /* Disable watchdog timer */ | |
fc723856 | 205 | atomic_io_modify(dev->reg + TIMER_CTRL, dev->data->wdt_enable_bit, 0); |
6d0f0dfd | 206 | |
0dd6e484 | 207 | return 0; |
6d0f0dfd WVS |
208 | } |
209 | ||
ebf5cf76 EG |
210 | static int armada370_stop(struct watchdog_device *wdt_dev) |
211 | { | |
212 | struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev); | |
213 | u32 reg; | |
214 | ||
215 | /* Disable reset on watchdog */ | |
216 | reg = readl(dev->rstout); | |
217 | reg &= ~dev->data->rstout_enable_bit; | |
218 | writel(reg, dev->rstout); | |
219 | ||
220 | /* Disable watchdog timer */ | |
221 | atomic_io_modify(dev->reg + TIMER_CTRL, dev->data->wdt_enable_bit, 0); | |
222 | ||
223 | return 0; | |
224 | } | |
225 | ||
226 | static int orion_wdt_stop(struct watchdog_device *wdt_dev) | |
227 | { | |
228 | struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev); | |
229 | ||
230 | return dev->data->stop(wdt_dev); | |
231 | } | |
232 | ||
1b0ea574 | 233 | static int orion_enabled(struct orion_watchdog *dev) |
6d0f0dfd | 234 | { |
d9d0c53d EG |
235 | bool enabled, running; |
236 | ||
fc723856 EG |
237 | enabled = readl(dev->rstout) & dev->data->rstout_enable_bit; |
238 | running = readl(dev->reg + TIMER_CTRL) & dev->data->wdt_enable_bit; | |
0dd6e484 | 239 | |
d9d0c53d EG |
240 | return enabled && running; |
241 | } | |
22ac9232 | 242 | |
1b0ea574 EG |
243 | static int orion_wdt_enabled(struct watchdog_device *wdt_dev) |
244 | { | |
245 | struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev); | |
246 | ||
247 | return dev->data->enabled(dev); | |
248 | } | |
249 | ||
0dd6e484 | 250 | static unsigned int orion_wdt_get_timeleft(struct watchdog_device *wdt_dev) |
6d0f0dfd | 251 | { |
b89a9c40 | 252 | struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev); |
fc723856 | 253 | return readl(dev->reg + dev->data->wdt_counter_offset) / dev->clk_rate; |
22ac9232 SB |
254 | } |
255 | ||
0dd6e484 AL |
256 | static int orion_wdt_set_timeout(struct watchdog_device *wdt_dev, |
257 | unsigned int timeout) | |
22ac9232 | 258 | { |
0dd6e484 | 259 | wdt_dev->timeout = timeout; |
df6707b2 TR |
260 | return 0; |
261 | } | |
262 | ||
0dd6e484 AL |
263 | static const struct watchdog_info orion_wdt_info = { |
264 | .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, | |
265 | .identity = "Orion Watchdog", | |
22ac9232 SB |
266 | }; |
267 | ||
0dd6e484 AL |
268 | static const struct watchdog_ops orion_wdt_ops = { |
269 | .owner = THIS_MODULE, | |
270 | .start = orion_wdt_start, | |
271 | .stop = orion_wdt_stop, | |
272 | .ping = orion_wdt_ping, | |
273 | .set_timeout = orion_wdt_set_timeout, | |
274 | .get_timeleft = orion_wdt_get_timeleft, | |
22ac9232 SB |
275 | }; |
276 | ||
e97662e1 EG |
277 | static irqreturn_t orion_wdt_irq(int irq, void *devid) |
278 | { | |
279 | panic("Watchdog Timeout"); | |
280 | return IRQ_HANDLED; | |
281 | } | |
282 | ||
868eb616 EG |
283 | /* |
284 | * The original devicetree binding for this driver specified only | |
285 | * one memory resource, so in order to keep DT backwards compatibility | |
286 | * we try to fallback to a hardcoded register address, if the resource | |
287 | * is missing from the devicetree. | |
288 | */ | |
289 | static void __iomem *orion_wdt_ioremap_rstout(struct platform_device *pdev, | |
290 | phys_addr_t internal_regs) | |
291 | { | |
292 | struct resource *res; | |
293 | phys_addr_t rstout; | |
294 | ||
295 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
296 | if (res) | |
297 | return devm_ioremap(&pdev->dev, res->start, | |
298 | resource_size(res)); | |
299 | ||
868eb616 EG |
300 | rstout = internal_regs + ORION_RSTOUT_MASK_OFFSET; |
301 | ||
edd9d3cf | 302 | WARN(1, FW_BUG "falling back to harcoded RSTOUT reg %pa\n", &rstout); |
868eb616 EG |
303 | return devm_ioremap(&pdev->dev, rstout, 0x4); |
304 | } | |
305 | ||
fc723856 EG |
306 | static const struct orion_watchdog_data orion_data = { |
307 | .rstout_enable_bit = BIT(1), | |
308 | .wdt_enable_bit = BIT(4), | |
309 | .wdt_counter_offset = 0x24, | |
1924227b | 310 | .clock_init = orion_wdt_clock_init, |
1b0ea574 | 311 | .enabled = orion_enabled, |
490d8e3c | 312 | .start = orion_start, |
ebf5cf76 | 313 | .stop = orion_stop, |
fc723856 EG |
314 | }; |
315 | ||
463f96e0 EG |
316 | static const struct orion_watchdog_data armada370_data = { |
317 | .rstout_enable_bit = BIT(8), | |
318 | .wdt_enable_bit = BIT(8), | |
319 | .wdt_counter_offset = 0x34, | |
320 | .clock_init = armada370_wdt_clock_init, | |
1b0ea574 | 321 | .enabled = orion_enabled, |
463f96e0 | 322 | .start = armada370_start, |
ebf5cf76 | 323 | .stop = armada370_stop, |
22ac9232 SB |
324 | }; |
325 | ||
463f96e0 EG |
326 | static const struct orion_watchdog_data armadaxp_data = { |
327 | .rstout_enable_bit = BIT(8), | |
328 | .wdt_enable_bit = BIT(8), | |
329 | .wdt_counter_offset = 0x34, | |
330 | .clock_init = armadaxp_wdt_clock_init, | |
1b0ea574 | 331 | .enabled = orion_enabled, |
463f96e0 | 332 | .start = armada370_start, |
ebf5cf76 | 333 | .stop = armada370_stop, |
463f96e0 EG |
334 | }; |
335 | ||
fc723856 EG |
336 | static const struct of_device_id orion_wdt_of_match_table[] = { |
337 | { | |
338 | .compatible = "marvell,orion-wdt", | |
339 | .data = &orion_data, | |
340 | }, | |
463f96e0 EG |
341 | { |
342 | .compatible = "marvell,armada-370-wdt", | |
343 | .data = &armada370_data, | |
344 | }, | |
345 | { | |
346 | .compatible = "marvell,armada-xp-wdt", | |
347 | .data = &armadaxp_data, | |
348 | }, | |
fc723856 EG |
349 | {}, |
350 | }; | |
351 | MODULE_DEVICE_TABLE(of, orion_wdt_of_match_table); | |
352 | ||
aaaac9ec EG |
353 | static int orion_wdt_get_regs(struct platform_device *pdev, |
354 | struct orion_watchdog *dev) | |
355 | { | |
92d4fc1a | 356 | struct device_node *node = pdev->dev.of_node; |
aaaac9ec EG |
357 | struct resource *res; |
358 | ||
359 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
360 | if (!res) | |
361 | return -ENODEV; | |
362 | dev->reg = devm_ioremap(&pdev->dev, res->start, | |
363 | resource_size(res)); | |
364 | if (!dev->reg) | |
365 | return -ENOMEM; | |
366 | ||
92d4fc1a EG |
367 | /* Each supported compatible has some RSTOUT register quirk */ |
368 | if (of_device_is_compatible(node, "marvell,orion-wdt")) { | |
369 | ||
370 | dev->rstout = orion_wdt_ioremap_rstout(pdev, res->start & | |
371 | INTERNAL_REGS_MASK); | |
372 | if (!dev->rstout) | |
373 | return -ENODEV; | |
374 | ||
375 | } else if (of_device_is_compatible(node, "marvell,armada-370-wdt") || | |
376 | of_device_is_compatible(node, "marvell,armada-xp-wdt")) { | |
377 | ||
378 | /* Dedicated RSTOUT register, can be requested. */ | |
379 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
380 | dev->rstout = devm_ioremap_resource(&pdev->dev, res); | |
381 | if (IS_ERR(dev->rstout)) | |
382 | return PTR_ERR(dev->rstout); | |
383 | ||
384 | } else { | |
aaaac9ec | 385 | return -ENODEV; |
92d4fc1a | 386 | } |
aaaac9ec EG |
387 | |
388 | return 0; | |
389 | } | |
390 | ||
2d991a16 | 391 | static int orion_wdt_probe(struct platform_device *pdev) |
22ac9232 | 392 | { |
b89a9c40 | 393 | struct orion_watchdog *dev; |
fc723856 | 394 | const struct of_device_id *match; |
b89a9c40 | 395 | unsigned int wdt_max_duration; /* (seconds) */ |
e97662e1 | 396 | int ret, irq; |
22ac9232 | 397 | |
b89a9c40 EG |
398 | dev = devm_kzalloc(&pdev->dev, sizeof(struct orion_watchdog), |
399 | GFP_KERNEL); | |
400 | if (!dev) | |
401 | return -ENOMEM; | |
402 | ||
fc723856 EG |
403 | match = of_match_device(orion_wdt_of_match_table, &pdev->dev); |
404 | if (!match) | |
405 | /* Default legacy match */ | |
406 | match = &orion_wdt_of_match_table[0]; | |
407 | ||
b89a9c40 EG |
408 | dev->wdt.info = &orion_wdt_info; |
409 | dev->wdt.ops = &orion_wdt_ops; | |
410 | dev->wdt.min_timeout = 1; | |
fc723856 | 411 | dev->data = match->data; |
9e058d4f | 412 | |
aaaac9ec EG |
413 | ret = orion_wdt_get_regs(pdev, dev); |
414 | if (ret) | |
415 | return ret; | |
0dd6e484 | 416 | |
1924227b | 417 | ret = dev->data->clock_init(pdev, dev); |
0dd6e484 | 418 | if (ret) { |
1924227b | 419 | dev_err(&pdev->dev, "cannot initialize clock\n"); |
9e058d4f | 420 | return ret; |
0dd6e484 | 421 | } |
9e058d4f | 422 | |
b89a9c40 EG |
423 | wdt_max_duration = WDT_MAX_CYCLE_COUNT / dev->clk_rate; |
424 | ||
425 | dev->wdt.timeout = wdt_max_duration; | |
426 | dev->wdt.max_timeout = wdt_max_duration; | |
427 | watchdog_init_timeout(&dev->wdt, heartbeat, &pdev->dev); | |
0dd6e484 | 428 | |
b89a9c40 EG |
429 | platform_set_drvdata(pdev, &dev->wdt); |
430 | watchdog_set_drvdata(&dev->wdt, dev); | |
0dd6e484 | 431 | |
d9d0c53d EG |
432 | /* |
433 | * Let's make sure the watchdog is fully stopped, unless it's | |
434 | * explicitly enabled. This may be the case if the module was | |
435 | * removed and re-insterted, or if the bootloader explicitly | |
436 | * set a running watchdog before booting the kernel. | |
437 | */ | |
1b0ea574 | 438 | if (!orion_wdt_enabled(&dev->wdt)) |
b89a9c40 | 439 | orion_wdt_stop(&dev->wdt); |
d9d0c53d | 440 | |
e97662e1 EG |
441 | /* Request the IRQ only after the watchdog is disabled */ |
442 | irq = platform_get_irq(pdev, 0); | |
443 | if (irq > 0) { | |
444 | /* | |
445 | * Not all supported platforms specify an interrupt for the | |
446 | * watchdog, so let's make it optional. | |
447 | */ | |
448 | ret = devm_request_irq(&pdev->dev, irq, orion_wdt_irq, 0, | |
b89a9c40 | 449 | pdev->name, dev); |
e97662e1 EG |
450 | if (ret < 0) { |
451 | dev_err(&pdev->dev, "failed to request IRQ\n"); | |
452 | goto disable_clk; | |
453 | } | |
454 | } | |
455 | ||
b89a9c40 EG |
456 | watchdog_set_nowayout(&dev->wdt, nowayout); |
457 | ret = watchdog_register_device(&dev->wdt); | |
bb02c662 EG |
458 | if (ret) |
459 | goto disable_clk; | |
9e058d4f | 460 | |
27c766aa | 461 | pr_info("Initial timeout %d sec%s\n", |
b89a9c40 | 462 | dev->wdt.timeout, nowayout ? ", nowayout" : ""); |
9e058d4f | 463 | return 0; |
bb02c662 EG |
464 | |
465 | disable_clk: | |
b89a9c40 | 466 | clk_disable_unprepare(dev->clk); |
463f96e0 | 467 | clk_put(dev->clk); |
bb02c662 | 468 | return ret; |
9e058d4f TR |
469 | } |
470 | ||
4b12b896 | 471 | static int orion_wdt_remove(struct platform_device *pdev) |
9e058d4f | 472 | { |
b89a9c40 EG |
473 | struct watchdog_device *wdt_dev = platform_get_drvdata(pdev); |
474 | struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev); | |
475 | ||
476 | watchdog_unregister_device(wdt_dev); | |
477 | clk_disable_unprepare(dev->clk); | |
463f96e0 | 478 | clk_put(dev->clk); |
0dd6e484 | 479 | return 0; |
22ac9232 SB |
480 | } |
481 | ||
3b937a7d | 482 | static void orion_wdt_shutdown(struct platform_device *pdev) |
df6707b2 | 483 | { |
b89a9c40 EG |
484 | struct watchdog_device *wdt_dev = platform_get_drvdata(pdev); |
485 | orion_wdt_stop(wdt_dev); | |
df6707b2 TR |
486 | } |
487 | ||
3b937a7d NP |
488 | static struct platform_driver orion_wdt_driver = { |
489 | .probe = orion_wdt_probe, | |
82268714 | 490 | .remove = orion_wdt_remove, |
3b937a7d | 491 | .shutdown = orion_wdt_shutdown, |
9e058d4f TR |
492 | .driver = { |
493 | .owner = THIS_MODULE, | |
3b937a7d | 494 | .name = "orion_wdt", |
85eee819 | 495 | .of_match_table = orion_wdt_of_match_table, |
9e058d4f TR |
496 | }, |
497 | }; | |
498 | ||
b8ec6118 | 499 | module_platform_driver(orion_wdt_driver); |
22ac9232 SB |
500 | |
501 | MODULE_AUTHOR("Sylver Bruneau <sylver.bruneau@googlemail.com>"); | |
3b937a7d | 502 | MODULE_DESCRIPTION("Orion Processor Watchdog"); |
22ac9232 SB |
503 | |
504 | module_param(heartbeat, int, 0); | |
df6707b2 | 505 | MODULE_PARM_DESC(heartbeat, "Initial watchdog heartbeat in seconds"); |
22ac9232 | 506 | |
86a1e189 | 507 | module_param(nowayout, bool, 0); |
df6707b2 TR |
508 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" |
509 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
22ac9232 SB |
510 | |
511 | MODULE_LICENSE("GPL"); | |
f3ea733e | 512 | MODULE_ALIAS("platform:orion_wdt"); |