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9325fa36 VW |
1 | /* |
2 | * drivers/char/watchdog/pnx4008_wdt.c | |
3 | * | |
4 | * Watchdog driver for PNX4008 board | |
5 | * | |
6 | * Authors: Dmitry Chigirev <source@mvista.com>, | |
5f3b2756 | 7 | * Vitaly Wool <vitalywool@gmail.com> |
9325fa36 VW |
8 | * Based on sa1100 driver, |
9 | * Copyright (C) 2000 Oleg Drokin <green@crimea.edu> | |
10 | * | |
6b1e8386 WS |
11 | * 2005-2006 (c) MontaVista Software, Inc. |
12 | * | |
13 | * (C) 2012 Wolfram Sang, Pengutronix | |
14 | * | |
15 | * This file is licensed under the terms of the GNU General Public License | |
16 | * version 2. This program is licensed "as is" without any warranty of any | |
17 | * kind, whether express or implied. | |
9325fa36 VW |
18 | */ |
19 | ||
27c766aa JP |
20 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
21 | ||
9325fa36 VW |
22 | #include <linux/module.h> |
23 | #include <linux/moduleparam.h> | |
24 | #include <linux/types.h> | |
25 | #include <linux/kernel.h> | |
9325fa36 | 26 | #include <linux/watchdog.h> |
9325fa36 VW |
27 | #include <linux/platform_device.h> |
28 | #include <linux/clk.h> | |
99d2853a | 29 | #include <linux/spinlock.h> |
84ca995c | 30 | #include <linux/io.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
6b1e8386 | 32 | #include <linux/err.h> |
3ba3774b | 33 | #include <linux/of.h> |
4ed5443d SL |
34 | #include <linux/delay.h> |
35 | #include <linux/reboot.h> | |
a09e64fb | 36 | #include <mach/hardware.h> |
9325fa36 | 37 | |
9325fa36 VW |
38 | /* WatchDog Timer - Chapter 23 Page 207 */ |
39 | ||
40 | #define DEFAULT_HEARTBEAT 19 | |
41 | #define MAX_HEARTBEAT 60 | |
42 | ||
43 | /* Watchdog timer register set definition */ | |
44 | #define WDTIM_INT(p) ((p) + 0x0) | |
45 | #define WDTIM_CTRL(p) ((p) + 0x4) | |
46 | #define WDTIM_COUNTER(p) ((p) + 0x8) | |
47 | #define WDTIM_MCTRL(p) ((p) + 0xC) | |
48 | #define WDTIM_MATCH0(p) ((p) + 0x10) | |
49 | #define WDTIM_EMR(p) ((p) + 0x14) | |
50 | #define WDTIM_PULSE(p) ((p) + 0x18) | |
51 | #define WDTIM_RES(p) ((p) + 0x1C) | |
52 | ||
53 | /* WDTIM_INT bit definitions */ | |
54 | #define MATCH_INT 1 | |
55 | ||
56 | /* WDTIM_CTRL bit definitions */ | |
57 | #define COUNT_ENAB 1 | |
143a2e54 WVS |
58 | #define RESET_COUNT (1 << 1) |
59 | #define DEBUG_EN (1 << 2) | |
9325fa36 VW |
60 | |
61 | /* WDTIM_MCTRL bit definitions */ | |
62 | #define MR0_INT 1 | |
63 | #undef RESET_COUNT0 | |
143a2e54 WVS |
64 | #define RESET_COUNT0 (1 << 2) |
65 | #define STOP_COUNT0 (1 << 2) | |
66 | #define M_RES1 (1 << 3) | |
67 | #define M_RES2 (1 << 4) | |
68 | #define RESFRC1 (1 << 5) | |
69 | #define RESFRC2 (1 << 6) | |
9325fa36 VW |
70 | |
71 | /* WDTIM_EMR bit definitions */ | |
72 | #define EXT_MATCH0 1 | |
143a2e54 | 73 | #define MATCH_OUTPUT_HIGH (2 << 4) /*a MATCH_CTRL setting */ |
9325fa36 VW |
74 | |
75 | /* WDTIM_RES bit definitions */ | |
76 | #define WDOG_RESET 1 /* read only */ | |
77 | ||
78 | #define WDOG_COUNTER_RATE 13000000 /*the counter clock is 13 MHz fixed */ | |
79 | ||
86a1e189 | 80 | static bool nowayout = WATCHDOG_NOWAYOUT; |
6b1e8386 | 81 | static unsigned int heartbeat = DEFAULT_HEARTBEAT; |
9325fa36 | 82 | |
c7dfd0cc | 83 | static DEFINE_SPINLOCK(io_lock); |
9325fa36 | 84 | static void __iomem *wdt_base; |
4c30737c | 85 | static struct clk *wdt_clk; |
9325fa36 | 86 | |
6b1e8386 | 87 | static int pnx4008_wdt_start(struct watchdog_device *wdd) |
9325fa36 | 88 | { |
99d2853a WVS |
89 | spin_lock(&io_lock); |
90 | ||
9325fa36 | 91 | /* stop counter, initiate counter reset */ |
7cbc3535 | 92 | writel(RESET_COUNT, WDTIM_CTRL(wdt_base)); |
9325fa36 | 93 | /*wait for reset to complete. 100% guarantee event */ |
7cbc3535 | 94 | while (readl(WDTIM_COUNTER(wdt_base))) |
65a64ec3 | 95 | cpu_relax(); |
9325fa36 | 96 | /* internal and external reset, stop after that */ |
7cbc3535 | 97 | writel(M_RES2 | STOP_COUNT0 | RESET_COUNT0, WDTIM_MCTRL(wdt_base)); |
9325fa36 | 98 | /* configure match output */ |
7cbc3535 | 99 | writel(MATCH_OUTPUT_HIGH, WDTIM_EMR(wdt_base)); |
9325fa36 | 100 | /* clear interrupt, just in case */ |
7cbc3535 | 101 | writel(MATCH_INT, WDTIM_INT(wdt_base)); |
9325fa36 | 102 | /* the longest pulse period 65541/(13*10^6) seconds ~ 5 ms. */ |
7cbc3535 | 103 | writel(0xFFFF, WDTIM_PULSE(wdt_base)); |
6b1e8386 | 104 | writel(wdd->timeout * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base)); |
9325fa36 | 105 | /*enable counter, stop when debugger active */ |
7cbc3535 | 106 | writel(COUNT_ENAB | DEBUG_EN, WDTIM_CTRL(wdt_base)); |
99d2853a WVS |
107 | |
108 | spin_unlock(&io_lock); | |
6b1e8386 | 109 | return 0; |
9325fa36 VW |
110 | } |
111 | ||
6b1e8386 | 112 | static int pnx4008_wdt_stop(struct watchdog_device *wdd) |
9325fa36 | 113 | { |
99d2853a WVS |
114 | spin_lock(&io_lock); |
115 | ||
7cbc3535 | 116 | writel(0, WDTIM_CTRL(wdt_base)); /*stop counter */ |
99d2853a WVS |
117 | |
118 | spin_unlock(&io_lock); | |
6b1e8386 | 119 | return 0; |
9325fa36 VW |
120 | } |
121 | ||
6b1e8386 WS |
122 | static int pnx4008_wdt_set_timeout(struct watchdog_device *wdd, |
123 | unsigned int new_timeout) | |
9325fa36 | 124 | { |
0197c1c4 | 125 | wdd->timeout = new_timeout; |
6b1e8386 | 126 | return 0; |
9325fa36 VW |
127 | } |
128 | ||
4ed5443d SL |
129 | static int pnx4008_restart_handler(struct watchdog_device *wdd, |
130 | unsigned long mode, void *cmd) | |
131 | { | |
247dcad5 SL |
132 | const char *boot_cmd = cmd; |
133 | ||
134 | /* | |
135 | * Verify if a "cmd" passed from the userspace program rebooting | |
136 | * the system; if available, handle it. | |
137 | * - For details, see the 'reboot' syscall in kernel/reboot.c | |
138 | * - If the received "cmd" is not supported, use the default mode. | |
139 | */ | |
140 | if (boot_cmd) { | |
141 | if (boot_cmd[0] == 'h') | |
142 | mode = REBOOT_HARD; | |
143 | else if (boot_cmd[0] == 's') | |
144 | mode = REBOOT_SOFT; | |
145 | } | |
146 | ||
25b286c0 SL |
147 | if (mode == REBOOT_SOFT) { |
148 | /* Force match output active */ | |
149 | writel(EXT_MATCH0, WDTIM_EMR(wdt_base)); | |
150 | /* Internal reset on match output (RESOUT_N not asserted) */ | |
151 | writel(M_RES1, WDTIM_MCTRL(wdt_base)); | |
152 | } else { | |
153 | /* Instant assert of RESETOUT_N with pulse length 1mS */ | |
154 | writel(13000, WDTIM_PULSE(wdt_base)); | |
155 | writel(M_RES2 | RESFRC1 | RESFRC2, WDTIM_MCTRL(wdt_base)); | |
156 | } | |
4ed5443d SL |
157 | |
158 | /* Wait for watchdog to reset system */ | |
159 | mdelay(1000); | |
160 | ||
161 | return NOTIFY_DONE; | |
162 | } | |
163 | ||
6b1e8386 | 164 | static const struct watchdog_info pnx4008_wdt_ident = { |
9325fa36 VW |
165 | .options = WDIOF_CARDRESET | WDIOF_MAGICCLOSE | |
166 | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, | |
167 | .identity = "PNX4008 Watchdog", | |
168 | }; | |
169 | ||
6b1e8386 | 170 | static const struct watchdog_ops pnx4008_wdt_ops = { |
9325fa36 | 171 | .owner = THIS_MODULE, |
6b1e8386 WS |
172 | .start = pnx4008_wdt_start, |
173 | .stop = pnx4008_wdt_stop, | |
174 | .set_timeout = pnx4008_wdt_set_timeout, | |
4ed5443d | 175 | .restart = pnx4008_restart_handler, |
9325fa36 VW |
176 | }; |
177 | ||
6b1e8386 WS |
178 | static struct watchdog_device pnx4008_wdd = { |
179 | .info = &pnx4008_wdt_ident, | |
180 | .ops = &pnx4008_wdt_ops, | |
c1fd5f64 | 181 | .timeout = DEFAULT_HEARTBEAT, |
6b1e8386 WS |
182 | .min_timeout = 1, |
183 | .max_timeout = MAX_HEARTBEAT, | |
9325fa36 VW |
184 | }; |
185 | ||
2d991a16 | 186 | static int pnx4008_wdt_probe(struct platform_device *pdev) |
9325fa36 | 187 | { |
19f505f0 WS |
188 | struct resource *r; |
189 | int ret = 0; | |
9325fa36 | 190 | |
c1fd5f64 | 191 | watchdog_init_timeout(&pnx4008_wdd, heartbeat, &pdev->dev); |
9325fa36 | 192 | |
19f505f0 | 193 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
4c271bb6 TR |
194 | wdt_base = devm_ioremap_resource(&pdev->dev, r); |
195 | if (IS_ERR(wdt_base)) | |
196 | return PTR_ERR(wdt_base); | |
9325fa36 | 197 | |
259181fe | 198 | wdt_clk = devm_clk_get(&pdev->dev, NULL); |
19f505f0 WS |
199 | if (IS_ERR(wdt_clk)) |
200 | return PTR_ERR(wdt_clk); | |
24fd1eda | 201 | |
b647d429 | 202 | ret = clk_prepare_enable(wdt_clk); |
19f505f0 | 203 | if (ret) |
259181fe | 204 | return ret; |
19f505f0 | 205 | |
6b1e8386 | 206 | pnx4008_wdd.bootstatus = (readl(WDTIM_RES(wdt_base)) & WDOG_RESET) ? |
7cbc3535 | 207 | WDIOF_CARDRESET : 0; |
6551881c | 208 | pnx4008_wdd.parent = &pdev->dev; |
6b1e8386 | 209 | watchdog_set_nowayout(&pnx4008_wdd, nowayout); |
4ed5443d | 210 | watchdog_set_restart_priority(&pnx4008_wdd, 128); |
6b1e8386 WS |
211 | |
212 | pnx4008_wdt_stop(&pnx4008_wdd); /* disable for now */ | |
9325fa36 | 213 | |
6b1e8386 | 214 | ret = watchdog_register_device(&pnx4008_wdd); |
9325fa36 | 215 | if (ret < 0) { |
6b1e8386 WS |
216 | dev_err(&pdev->dev, "cannot register watchdog device\n"); |
217 | goto disable_clk; | |
9325fa36 VW |
218 | } |
219 | ||
43eec2f5 | 220 | dev_info(&pdev->dev, "heartbeat %d sec\n", pnx4008_wdd.timeout); |
19f505f0 WS |
221 | |
222 | return 0; | |
223 | ||
6b1e8386 | 224 | disable_clk: |
b647d429 | 225 | clk_disable_unprepare(wdt_clk); |
9325fa36 VW |
226 | return ret; |
227 | } | |
228 | ||
4b12b896 | 229 | static int pnx4008_wdt_remove(struct platform_device *pdev) |
9325fa36 | 230 | { |
6b1e8386 | 231 | watchdog_unregister_device(&pnx4008_wdd); |
24fd1eda | 232 | |
b647d429 | 233 | clk_disable_unprepare(wdt_clk); |
24fd1eda | 234 | |
9325fa36 VW |
235 | return 0; |
236 | } | |
237 | ||
3ba3774b RS |
238 | #ifdef CONFIG_OF |
239 | static const struct of_device_id pnx4008_wdt_match[] = { | |
240 | { .compatible = "nxp,pnx4008-wdt" }, | |
241 | { } | |
242 | }; | |
243 | MODULE_DEVICE_TABLE(of, pnx4008_wdt_match); | |
244 | #endif | |
245 | ||
9325fa36 VW |
246 | static struct platform_driver platform_wdt_driver = { |
247 | .driver = { | |
1508c995 | 248 | .name = "pnx4008-watchdog", |
3ba3774b | 249 | .of_match_table = of_match_ptr(pnx4008_wdt_match), |
9325fa36 VW |
250 | }, |
251 | .probe = pnx4008_wdt_probe, | |
82268714 | 252 | .remove = pnx4008_wdt_remove, |
9325fa36 VW |
253 | }; |
254 | ||
b8ec6118 | 255 | module_platform_driver(platform_wdt_driver); |
9325fa36 VW |
256 | |
257 | MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>"); | |
e8cc5366 | 258 | MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>"); |
9325fa36 VW |
259 | MODULE_DESCRIPTION("PNX4008 Watchdog Driver"); |
260 | ||
6b1e8386 | 261 | module_param(heartbeat, uint, 0); |
9325fa36 VW |
262 | MODULE_PARM_DESC(heartbeat, |
263 | "Watchdog heartbeat period in seconds from 1 to " | |
264 | __MODULE_STRING(MAX_HEARTBEAT) ", default " | |
265 | __MODULE_STRING(DEFAULT_HEARTBEAT)); | |
266 | ||
86a1e189 | 267 | module_param(nowayout, bool, 0); |
9325fa36 VW |
268 | MODULE_PARM_DESC(nowayout, |
269 | "Set to 1 to keep watchdog running after device release"); | |
270 | ||
271 | MODULE_LICENSE("GPL"); | |
1508c995 | 272 | MODULE_ALIAS("platform:pnx4008-watchdog"); |