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9325fa36 VW |
1 | /* |
2 | * drivers/char/watchdog/pnx4008_wdt.c | |
3 | * | |
4 | * Watchdog driver for PNX4008 board | |
5 | * | |
6 | * Authors: Dmitry Chigirev <source@mvista.com>, | |
7 | * Vitaly Wool <vitalywool@gmail.com> | |
8 | * Based on sa1100 driver, | |
9 | * Copyright (C) 2000 Oleg Drokin <green@crimea.edu> | |
10 | * | |
11 | * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under | |
12 | * the terms of the GNU General Public License version 2. This program | |
13 | * is licensed "as is" without any warranty of any kind, whether express | |
14 | * or implied. | |
15 | */ | |
16 | ||
9325fa36 VW |
17 | #include <linux/module.h> |
18 | #include <linux/moduleparam.h> | |
19 | #include <linux/types.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/fs.h> | |
22 | #include <linux/miscdevice.h> | |
23 | #include <linux/watchdog.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/bitops.h> | |
26 | #include <linux/ioport.h> | |
27 | #include <linux/device.h> | |
28 | #include <linux/platform_device.h> | |
29 | #include <linux/clk.h> | |
99d2853a | 30 | #include <linux/spinlock.h> |
84ca995c AC |
31 | #include <linux/uaccess.h> |
32 | #include <linux/io.h> | |
a09e64fb | 33 | #include <mach/hardware.h> |
9325fa36 VW |
34 | |
35 | #define MODULE_NAME "PNX4008-WDT: " | |
36 | ||
37 | /* WatchDog Timer - Chapter 23 Page 207 */ | |
38 | ||
39 | #define DEFAULT_HEARTBEAT 19 | |
40 | #define MAX_HEARTBEAT 60 | |
41 | ||
42 | /* Watchdog timer register set definition */ | |
43 | #define WDTIM_INT(p) ((p) + 0x0) | |
44 | #define WDTIM_CTRL(p) ((p) + 0x4) | |
45 | #define WDTIM_COUNTER(p) ((p) + 0x8) | |
46 | #define WDTIM_MCTRL(p) ((p) + 0xC) | |
47 | #define WDTIM_MATCH0(p) ((p) + 0x10) | |
48 | #define WDTIM_EMR(p) ((p) + 0x14) | |
49 | #define WDTIM_PULSE(p) ((p) + 0x18) | |
50 | #define WDTIM_RES(p) ((p) + 0x1C) | |
51 | ||
52 | /* WDTIM_INT bit definitions */ | |
53 | #define MATCH_INT 1 | |
54 | ||
55 | /* WDTIM_CTRL bit definitions */ | |
56 | #define COUNT_ENAB 1 | |
143a2e54 WVS |
57 | #define RESET_COUNT (1 << 1) |
58 | #define DEBUG_EN (1 << 2) | |
9325fa36 VW |
59 | |
60 | /* WDTIM_MCTRL bit definitions */ | |
61 | #define MR0_INT 1 | |
62 | #undef RESET_COUNT0 | |
143a2e54 WVS |
63 | #define RESET_COUNT0 (1 << 2) |
64 | #define STOP_COUNT0 (1 << 2) | |
65 | #define M_RES1 (1 << 3) | |
66 | #define M_RES2 (1 << 4) | |
67 | #define RESFRC1 (1 << 5) | |
68 | #define RESFRC2 (1 << 6) | |
9325fa36 VW |
69 | |
70 | /* WDTIM_EMR bit definitions */ | |
71 | #define EXT_MATCH0 1 | |
143a2e54 | 72 | #define MATCH_OUTPUT_HIGH (2 << 4) /*a MATCH_CTRL setting */ |
9325fa36 VW |
73 | |
74 | /* WDTIM_RES bit definitions */ | |
75 | #define WDOG_RESET 1 /* read only */ | |
76 | ||
77 | #define WDOG_COUNTER_RATE 13000000 /*the counter clock is 13 MHz fixed */ | |
78 | ||
28981727 | 79 | static int nowayout = WATCHDOG_NOWAYOUT; |
9325fa36 VW |
80 | static int heartbeat = DEFAULT_HEARTBEAT; |
81 | ||
c7dfd0cc | 82 | static DEFINE_SPINLOCK(io_lock); |
9325fa36 VW |
83 | static unsigned long wdt_status; |
84 | #define WDT_IN_USE 0 | |
85 | #define WDT_OK_TO_CLOSE 1 | |
86 | #define WDT_REGION_INITED 2 | |
87 | #define WDT_DEVICE_INITED 3 | |
88 | ||
89 | static unsigned long boot_status; | |
90 | ||
91 | static struct resource *wdt_mem; | |
92 | static void __iomem *wdt_base; | |
93 | struct clk *wdt_clk; | |
94 | ||
95 | static void wdt_enable(void) | |
96 | { | |
99d2853a WVS |
97 | spin_lock(&io_lock); |
98 | ||
9325fa36 VW |
99 | /* stop counter, initiate counter reset */ |
100 | __raw_writel(RESET_COUNT, WDTIM_CTRL(wdt_base)); | |
101 | /*wait for reset to complete. 100% guarantee event */ | |
65a64ec3 VW |
102 | while (__raw_readl(WDTIM_COUNTER(wdt_base))) |
103 | cpu_relax(); | |
9325fa36 VW |
104 | /* internal and external reset, stop after that */ |
105 | __raw_writel(M_RES2 | STOP_COUNT0 | RESET_COUNT0, | |
106 | WDTIM_MCTRL(wdt_base)); | |
107 | /* configure match output */ | |
108 | __raw_writel(MATCH_OUTPUT_HIGH, WDTIM_EMR(wdt_base)); | |
109 | /* clear interrupt, just in case */ | |
110 | __raw_writel(MATCH_INT, WDTIM_INT(wdt_base)); | |
111 | /* the longest pulse period 65541/(13*10^6) seconds ~ 5 ms. */ | |
112 | __raw_writel(0xFFFF, WDTIM_PULSE(wdt_base)); | |
113 | __raw_writel(heartbeat * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base)); | |
114 | /*enable counter, stop when debugger active */ | |
115 | __raw_writel(COUNT_ENAB | DEBUG_EN, WDTIM_CTRL(wdt_base)); | |
99d2853a WVS |
116 | |
117 | spin_unlock(&io_lock); | |
9325fa36 VW |
118 | } |
119 | ||
120 | static void wdt_disable(void) | |
121 | { | |
99d2853a WVS |
122 | spin_lock(&io_lock); |
123 | ||
9325fa36 | 124 | __raw_writel(0, WDTIM_CTRL(wdt_base)); /*stop counter */ |
99d2853a WVS |
125 | |
126 | spin_unlock(&io_lock); | |
9325fa36 VW |
127 | } |
128 | ||
129 | static int pnx4008_wdt_open(struct inode *inode, struct file *file) | |
130 | { | |
24fd1eda RK |
131 | int ret; |
132 | ||
9325fa36 VW |
133 | if (test_and_set_bit(WDT_IN_USE, &wdt_status)) |
134 | return -EBUSY; | |
135 | ||
136 | clear_bit(WDT_OK_TO_CLOSE, &wdt_status); | |
137 | ||
24fd1eda RK |
138 | ret = clk_enable(wdt_clk); |
139 | if (ret) { | |
140 | clear_bit(WDT_IN_USE, &wdt_status); | |
141 | return ret; | |
142 | } | |
143 | ||
9325fa36 VW |
144 | wdt_enable(); |
145 | ||
146 | return nonseekable_open(inode, file); | |
147 | } | |
148 | ||
84ca995c AC |
149 | static ssize_t pnx4008_wdt_write(struct file *file, const char *data, |
150 | size_t len, loff_t *ppos) | |
9325fa36 | 151 | { |
9325fa36 VW |
152 | if (len) { |
153 | if (!nowayout) { | |
154 | size_t i; | |
155 | ||
156 | clear_bit(WDT_OK_TO_CLOSE, &wdt_status); | |
157 | ||
158 | for (i = 0; i != len; i++) { | |
159 | char c; | |
160 | ||
161 | if (get_user(c, data + i)) | |
162 | return -EFAULT; | |
163 | if (c == 'V') | |
164 | set_bit(WDT_OK_TO_CLOSE, &wdt_status); | |
165 | } | |
166 | } | |
167 | wdt_enable(); | |
168 | } | |
169 | ||
170 | return len; | |
171 | } | |
172 | ||
84ca995c | 173 | static const struct watchdog_info ident = { |
9325fa36 VW |
174 | .options = WDIOF_CARDRESET | WDIOF_MAGICCLOSE | |
175 | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, | |
176 | .identity = "PNX4008 Watchdog", | |
177 | }; | |
178 | ||
7275fc8c WVS |
179 | static long pnx4008_wdt_ioctl(struct file *file, unsigned int cmd, |
180 | unsigned long arg) | |
9325fa36 | 181 | { |
f311896a | 182 | int ret = -ENOTTY; |
9325fa36 VW |
183 | int time; |
184 | ||
185 | switch (cmd) { | |
186 | case WDIOC_GETSUPPORT: | |
187 | ret = copy_to_user((struct watchdog_info *)arg, &ident, | |
188 | sizeof(ident)) ? -EFAULT : 0; | |
189 | break; | |
190 | ||
191 | case WDIOC_GETSTATUS: | |
192 | ret = put_user(0, (int *)arg); | |
193 | break; | |
194 | ||
195 | case WDIOC_GETBOOTSTATUS: | |
196 | ret = put_user(boot_status, (int *)arg); | |
197 | break; | |
198 | ||
0c06090c WVS |
199 | case WDIOC_KEEPALIVE: |
200 | wdt_enable(); | |
201 | ret = 0; | |
202 | break; | |
203 | ||
9325fa36 VW |
204 | case WDIOC_SETTIMEOUT: |
205 | ret = get_user(time, (int *)arg); | |
206 | if (ret) | |
207 | break; | |
208 | ||
209 | if (time <= 0 || time > MAX_HEARTBEAT) { | |
210 | ret = -EINVAL; | |
211 | break; | |
212 | } | |
213 | ||
214 | heartbeat = time; | |
215 | wdt_enable(); | |
216 | /* Fall through */ | |
217 | ||
218 | case WDIOC_GETTIMEOUT: | |
219 | ret = put_user(heartbeat, (int *)arg); | |
220 | break; | |
9325fa36 VW |
221 | } |
222 | return ret; | |
223 | } | |
224 | ||
225 | static int pnx4008_wdt_release(struct inode *inode, struct file *file) | |
226 | { | |
227 | if (!test_bit(WDT_OK_TO_CLOSE, &wdt_status)) | |
228 | printk(KERN_WARNING "WATCHDOG: Device closed unexpectdly\n"); | |
229 | ||
230 | wdt_disable(); | |
24fd1eda | 231 | clk_disable(wdt_clk); |
9325fa36 VW |
232 | clear_bit(WDT_IN_USE, &wdt_status); |
233 | clear_bit(WDT_OK_TO_CLOSE, &wdt_status); | |
234 | ||
235 | return 0; | |
236 | } | |
237 | ||
2b8693c0 | 238 | static const struct file_operations pnx4008_wdt_fops = { |
9325fa36 VW |
239 | .owner = THIS_MODULE, |
240 | .llseek = no_llseek, | |
241 | .write = pnx4008_wdt_write, | |
84ca995c | 242 | .unlocked_ioctl = pnx4008_wdt_ioctl, |
9325fa36 VW |
243 | .open = pnx4008_wdt_open, |
244 | .release = pnx4008_wdt_release, | |
245 | }; | |
246 | ||
247 | static struct miscdevice pnx4008_wdt_miscdev = { | |
248 | .minor = WATCHDOG_MINOR, | |
249 | .name = "watchdog", | |
250 | .fops = &pnx4008_wdt_fops, | |
251 | }; | |
252 | ||
b6bf291f | 253 | static int __devinit pnx4008_wdt_probe(struct platform_device *pdev) |
9325fa36 VW |
254 | { |
255 | int ret = 0, size; | |
256 | struct resource *res; | |
257 | ||
258 | if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT) | |
259 | heartbeat = DEFAULT_HEARTBEAT; | |
260 | ||
261 | printk(KERN_INFO MODULE_NAME | |
262 | "PNX4008 Watchdog Timer: heartbeat %d sec\n", heartbeat); | |
263 | ||
264 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
265 | if (res == NULL) { | |
266 | printk(KERN_INFO MODULE_NAME | |
267 | "failed to get memory region resouce\n"); | |
268 | return -ENOENT; | |
269 | } | |
270 | ||
b782a563 | 271 | size = resource_size(res); |
9325fa36 VW |
272 | wdt_mem = request_mem_region(res->start, size, pdev->name); |
273 | ||
274 | if (wdt_mem == NULL) { | |
275 | printk(KERN_INFO MODULE_NAME "failed to get memory region\n"); | |
276 | return -ENOENT; | |
277 | } | |
278 | wdt_base = (void __iomem *)IO_ADDRESS(res->start); | |
279 | ||
9bb787f4 | 280 | wdt_clk = clk_get(&pdev->dev, NULL); |
9cd44619 AM |
281 | if (IS_ERR(wdt_clk)) { |
282 | ret = PTR_ERR(wdt_clk); | |
9325fa36 VW |
283 | release_resource(wdt_mem); |
284 | kfree(wdt_mem); | |
285 | goto out; | |
24fd1eda RK |
286 | } |
287 | ||
288 | ret = clk_enable(wdt_clk); | |
289 | if (ret) { | |
290 | release_resource(wdt_mem); | |
291 | kfree(wdt_mem); | |
292 | goto out; | |
293 | } | |
9325fa36 VW |
294 | |
295 | ret = misc_register(&pnx4008_wdt_miscdev); | |
296 | if (ret < 0) { | |
297 | printk(KERN_ERR MODULE_NAME "cannot register misc device\n"); | |
298 | release_resource(wdt_mem); | |
299 | kfree(wdt_mem); | |
24fd1eda RK |
300 | clk_disable(wdt_clk); |
301 | clk_put(wdt_clk); | |
9325fa36 VW |
302 | } else { |
303 | boot_status = (__raw_readl(WDTIM_RES(wdt_base)) & WDOG_RESET) ? | |
304 | WDIOF_CARDRESET : 0; | |
305 | wdt_disable(); /*disable for now */ | |
24fd1eda | 306 | clk_disable(wdt_clk); |
9325fa36 VW |
307 | set_bit(WDT_DEVICE_INITED, &wdt_status); |
308 | } | |
309 | ||
310 | out: | |
311 | return ret; | |
312 | } | |
313 | ||
b6bf291f | 314 | static int __devexit pnx4008_wdt_remove(struct platform_device *pdev) |
9325fa36 | 315 | { |
f6764497 | 316 | misc_deregister(&pnx4008_wdt_miscdev); |
24fd1eda RK |
317 | |
318 | clk_disable(wdt_clk); | |
319 | clk_put(wdt_clk); | |
320 | ||
f6764497 WVS |
321 | if (wdt_mem) { |
322 | release_resource(wdt_mem); | |
323 | kfree(wdt_mem); | |
324 | wdt_mem = NULL; | |
325 | } | |
9325fa36 VW |
326 | return 0; |
327 | } | |
328 | ||
329 | static struct platform_driver platform_wdt_driver = { | |
330 | .driver = { | |
1508c995 | 331 | .name = "pnx4008-watchdog", |
f37d193c | 332 | .owner = THIS_MODULE, |
9325fa36 VW |
333 | }, |
334 | .probe = pnx4008_wdt_probe, | |
b6bf291f | 335 | .remove = __devexit_p(pnx4008_wdt_remove), |
9325fa36 VW |
336 | }; |
337 | ||
338 | static int __init pnx4008_wdt_init(void) | |
339 | { | |
340 | return platform_driver_register(&platform_wdt_driver); | |
341 | } | |
342 | ||
343 | static void __exit pnx4008_wdt_exit(void) | |
344 | { | |
bb0a38d8 | 345 | platform_driver_unregister(&platform_wdt_driver); |
9325fa36 VW |
346 | } |
347 | ||
348 | module_init(pnx4008_wdt_init); | |
349 | module_exit(pnx4008_wdt_exit); | |
350 | ||
351 | MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>"); | |
352 | MODULE_DESCRIPTION("PNX4008 Watchdog Driver"); | |
353 | ||
354 | module_param(heartbeat, int, 0); | |
355 | MODULE_PARM_DESC(heartbeat, | |
356 | "Watchdog heartbeat period in seconds from 1 to " | |
357 | __MODULE_STRING(MAX_HEARTBEAT) ", default " | |
358 | __MODULE_STRING(DEFAULT_HEARTBEAT)); | |
359 | ||
360 | module_param(nowayout, int, 0); | |
361 | MODULE_PARM_DESC(nowayout, | |
362 | "Set to 1 to keep watchdog running after device release"); | |
363 | ||
364 | MODULE_LICENSE("GPL"); | |
365 | MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); | |
1508c995 | 366 | MODULE_ALIAS("platform:pnx4008-watchdog"); |