[deliverable/linux.git] / drivers / watchdog / pnx4008_wdt.c

/*
 * drivers/char/watchdog/pnx4008_wdt.c
 *
 * Watchdog driver for PNX4008 board
 *
 * Authors: Dmitry Chigirev <source@mvista.com>,
 *	    Vitaly Wool <vitalywool@gmail.com>
 * Based on sa1100 driver,
 * Copyright (C) 2000 Oleg Drokin <green@crimea.edu>
 *
 * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
 * the terms of the GNU General Public License version 2. This program
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 */

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/fs.h>
#include <linux/miscdevice.h>
#include <linux/watchdog.h>
#include <linux/init.h>
#include <linux/bitops.h>
#include <linux/ioport.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/spinlock.h>
#include <linux/uaccess.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <mach/hardware.h>

#define MODULE_NAME "PNX4008-WDT: "

/* WatchDog Timer - Chapter 23 Page 207 */

#define DEFAULT_HEARTBEAT 19
#define MAX_HEARTBEAT     60

/* Watchdog timer register set definition */
#define WDTIM_INT(p)     ((p) + 0x0)
#define WDTIM_CTRL(p)    ((p) + 0x4)
#define WDTIM_COUNTER(p) ((p) + 0x8)
#define WDTIM_MCTRL(p)   ((p) + 0xC)
#define WDTIM_MATCH0(p)  ((p) + 0x10)
#define WDTIM_EMR(p)     ((p) + 0x14)
#define WDTIM_PULSE(p)   ((p) + 0x18)
#define WDTIM_RES(p)     ((p) + 0x1C)

/* WDTIM_INT bit definitions */
#define MATCH_INT      1

/* WDTIM_CTRL bit definitions */
#define COUNT_ENAB     1
#define RESET_COUNT    (1 << 1)
#define DEBUG_EN       (1 << 2)

/* WDTIM_MCTRL bit definitions */
#define MR0_INT        1
#undef  RESET_COUNT0
#define RESET_COUNT0   (1 << 2)
#define STOP_COUNT0    (1 << 2)
#define M_RES1         (1 << 3)
#define M_RES2         (1 << 4)
#define RESFRC1        (1 << 5)
#define RESFRC2        (1 << 6)

/* WDTIM_EMR bit definitions */
#define EXT_MATCH0      1
#define MATCH_OUTPUT_HIGH (2 << 4)	/*a MATCH_CTRL setting */

/* WDTIM_RES bit definitions */
#define WDOG_RESET      1	/* read only */

#define WDOG_COUNTER_RATE 13000000	/*the counter clock is 13 MHz fixed */

static int nowayout = WATCHDOG_NOWAYOUT;
static int heartbeat = DEFAULT_HEARTBEAT;

static DEFINE_SPINLOCK(io_lock);
static unsigned long wdt_status;
#define WDT_IN_USE        0
#define WDT_OK_TO_CLOSE   1

static unsigned long boot_status;

static void __iomem	*wdt_base;
struct clk		*wdt_clk;

static void wdt_enable(void)
{
	spin_lock(&io_lock);

	/* stop counter, initiate counter reset */
	writel(RESET_COUNT, WDTIM_CTRL(wdt_base));
	/*wait for reset to complete. 100% guarantee event */
	while (readl(WDTIM_COUNTER(wdt_base)))
		cpu_relax();
	/* internal and external reset, stop after that */
	writel(M_RES2 | STOP_COUNT0 | RESET_COUNT0, WDTIM_MCTRL(wdt_base));
	/* configure match output */
	writel(MATCH_OUTPUT_HIGH, WDTIM_EMR(wdt_base));
	/* clear interrupt, just in case */
	writel(MATCH_INT, WDTIM_INT(wdt_base));
	/* the longest pulse period 65541/(13*10^6) seconds ~ 5 ms. */
	writel(0xFFFF, WDTIM_PULSE(wdt_base));
	writel(heartbeat * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base));
	/*enable counter, stop when debugger active */
	writel(COUNT_ENAB | DEBUG_EN, WDTIM_CTRL(wdt_base));

	spin_unlock(&io_lock);
}

static void wdt_disable(void)
{
	spin_lock(&io_lock);

	writel(0, WDTIM_CTRL(wdt_base));	/*stop counter */

	spin_unlock(&io_lock);
}

static int pnx4008_wdt_open(struct inode *inode, struct file *file)
{
	int ret;

	if (test_and_set_bit(WDT_IN_USE, &wdt_status))
		return -EBUSY;

	clear_bit(WDT_OK_TO_CLOSE, &wdt_status);

	ret = clk_enable(wdt_clk);
	if (ret) {
		clear_bit(WDT_IN_USE, &wdt_status);
		return ret;
	}

	wdt_enable();

	return nonseekable_open(inode, file);
}

static ssize_t pnx4008_wdt_write(struct file *file, const char *data,
					size_t len, loff_t *ppos)
{
	if (len) {
		if (!nowayout) {
			size_t i;

			clear_bit(WDT_OK_TO_CLOSE, &wdt_status);

			for (i = 0; i != len; i++) {
				char c;

				if (get_user(c, data + i))
					return -EFAULT;
				if (c == 'V')
					set_bit(WDT_OK_TO_CLOSE, &wdt_status);
			}
		}
		wdt_enable();
	}

	return len;
}

static const struct watchdog_info ident = {
	.options = WDIOF_CARDRESET | WDIOF_MAGICCLOSE |
	    WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
	.identity = "PNX4008 Watchdog",
};

static long pnx4008_wdt_ioctl(struct file *file, unsigned int cmd,
				unsigned long arg)
{
	int ret = -ENOTTY;
	int time;

	switch (cmd) {
	case WDIOC_GETSUPPORT:
		ret = copy_to_user((struct watchdog_info *)arg, &ident,
				   sizeof(ident)) ? -EFAULT : 0;
		break;

	case WDIOC_GETSTATUS:
		ret = put_user(0, (int *)arg);
		break;

	case WDIOC_GETBOOTSTATUS:
		ret = put_user(boot_status, (int *)arg);
		break;

	case WDIOC_KEEPALIVE:
		wdt_enable();
		ret = 0;
		break;

	case WDIOC_SETTIMEOUT:
		ret = get_user(time, (int *)arg);
		if (ret)
			break;

		if (time <= 0 || time > MAX_HEARTBEAT) {
			ret = -EINVAL;
			break;
		}

		heartbeat = time;
		wdt_enable();
		/* Fall through */

	case WDIOC_GETTIMEOUT:
		ret = put_user(heartbeat, (int *)arg);
		break;
	}
	return ret;
}

static int pnx4008_wdt_release(struct inode *inode, struct file *file)
{
	if (!test_bit(WDT_OK_TO_CLOSE, &wdt_status))
		printk(KERN_WARNING "WATCHDOG: Device closed unexpectedly\n");

	wdt_disable();
	clk_disable(wdt_clk);
	clear_bit(WDT_IN_USE, &wdt_status);
	clear_bit(WDT_OK_TO_CLOSE, &wdt_status);

	return 0;
}

static const struct file_operations pnx4008_wdt_fops = {
	.owner = THIS_MODULE,
	.llseek = no_llseek,
	.write = pnx4008_wdt_write,
	.unlocked_ioctl = pnx4008_wdt_ioctl,
	.open = pnx4008_wdt_open,
	.release = pnx4008_wdt_release,
};

static struct miscdevice pnx4008_wdt_miscdev = {
	.minor = WATCHDOG_MINOR,
	.name = "watchdog",
	.fops = &pnx4008_wdt_fops,
};

static int __devinit pnx4008_wdt_probe(struct platform_device *pdev)
{
	struct resource *r;
	int ret = 0;

	if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT)
		heartbeat = DEFAULT_HEARTBEAT;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	wdt_base = devm_request_and_ioremap(&pdev->dev, r);
	if (!wdt_base)
		return -EADDRINUSE;

	wdt_clk = clk_get(&pdev->dev, NULL);
	if (IS_ERR(wdt_clk))
		return PTR_ERR(wdt_clk);

	ret = clk_enable(wdt_clk);
	if (ret)
		goto out;

	boot_status = (readl(WDTIM_RES(wdt_base)) & WDOG_RESET) ?
			WDIOF_CARDRESET : 0;
	wdt_disable();		/*disable for now */
	clk_disable(wdt_clk);

	ret = misc_register(&pnx4008_wdt_miscdev);
	if (ret < 0) {
		dev_err(&pdev->dev, "cannot register misc device\n");
		goto out;
	}

	dev_info(&pdev->dev, "PNX4008 Watchdog Timer: heartbeat %d sec\n",
			heartbeat);

	return 0;

out:
	clk_put(wdt_clk);
	return ret;
}

static int __devexit pnx4008_wdt_remove(struct platform_device *pdev)
{
	misc_deregister(&pnx4008_wdt_miscdev);

	clk_disable(wdt_clk);
	clk_put(wdt_clk);

	return 0;
}

static struct platform_driver platform_wdt_driver = {
	.driver = {
		.name = "pnx4008-watchdog",
		.owner	= THIS_MODULE,
	},
	.probe = pnx4008_wdt_probe,
	.remove = __devexit_p(pnx4008_wdt_remove),
};

module_platform_driver(platform_wdt_driver);

MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
MODULE_DESCRIPTION("PNX4008 Watchdog Driver");

module_param(heartbeat, int, 0);
MODULE_PARM_DESC(heartbeat,
		 "Watchdog heartbeat period in seconds from 1 to "
		 __MODULE_STRING(MAX_HEARTBEAT) ", default "
		 __MODULE_STRING(DEFAULT_HEARTBEAT));

module_param(nowayout, int, 0);
MODULE_PARM_DESC(nowayout,
		 "Set to 1 to keep watchdog running after device release");

MODULE_LICENSE("GPL");
MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
MODULE_ALIAS("platform:pnx4008-watchdog");
Commit	Line	Data
9325fa36 VW	1	/*
	2	* drivers/char/watchdog/pnx4008_wdt.c
	3	*
	4	* Watchdog driver for PNX4008 board
	5	*
	6	* Authors: Dmitry Chigirev <source@mvista.com>,
5f3b2756	7	* Vitaly Wool <vitalywool@gmail.com>
9325fa36 VW	8	* Based on sa1100 driver,
	9	* Copyright (C) 2000 Oleg Drokin <green@crimea.edu>
	10	*
	11	* 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
	12	* the terms of the GNU General Public License version 2. This program
	13	* is licensed "as is" without any warranty of any kind, whether express
	14	* or implied.
	15	*/
	16
9325fa36 VW	17	#include <linux/module.h>
	18	#include <linux/moduleparam.h>
	19	#include <linux/types.h>
	20	#include <linux/kernel.h>
	21	#include <linux/fs.h>
	22	#include <linux/miscdevice.h>
	23	#include <linux/watchdog.h>
	24	#include <linux/init.h>
	25	#include <linux/bitops.h>
	26	#include <linux/ioport.h>
	27	#include <linux/device.h>
	28	#include <linux/platform_device.h>
	29	#include <linux/clk.h>
99d2853a	30	#include <linux/spinlock.h>
84ca995c AC	31	#include <linux/uaccess.h>
84ca995c AC	32	#include <linux/io.h>
5a0e3ad6	33	#include <linux/slab.h>
a09e64fb	34	#include <mach/hardware.h>
9325fa36 VW	35
	36	#define MODULE_NAME "PNX4008-WDT: "
	37
	38	/* WatchDog Timer - Chapter 23 Page 207 */
	39
	40	#define DEFAULT_HEARTBEAT 19
	41	#define MAX_HEARTBEAT 60
	42
	43	/* Watchdog timer register set definition */
	44	#define WDTIM_INT(p) ((p) + 0x0)
	45	#define WDTIM_CTRL(p) ((p) + 0x4)
	46	#define WDTIM_COUNTER(p) ((p) + 0x8)
	47	#define WDTIM_MCTRL(p) ((p) + 0xC)
	48	#define WDTIM_MATCH0(p) ((p) + 0x10)
	49	#define WDTIM_EMR(p) ((p) + 0x14)
	50	#define WDTIM_PULSE(p) ((p) + 0x18)
	51	#define WDTIM_RES(p) ((p) + 0x1C)
	52
	53	/* WDTIM_INT bit definitions */
	54	#define MATCH_INT 1
	55
	56	/* WDTIM_CTRL bit definitions */
	57	#define COUNT_ENAB 1
143a2e54 WVS	58	#define RESET_COUNT (1 << 1)
143a2e54 WVS	59	#define DEBUG_EN (1 << 2)
9325fa36 VW	60
	61	/* WDTIM_MCTRL bit definitions */
	62	#define MR0_INT 1
	63	#undef RESET_COUNT0
143a2e54 WVS	64	#define RESET_COUNT0 (1 << 2)
	65	#define STOP_COUNT0 (1 << 2)
	66	#define M_RES1 (1 << 3)
	67	#define M_RES2 (1 << 4)
	68	#define RESFRC1 (1 << 5)
	69	#define RESFRC2 (1 << 6)
9325fa36 VW	70
	71	/* WDTIM_EMR bit definitions */
	72	#define EXT_MATCH0 1
143a2e54	73	#define MATCH_OUTPUT_HIGH (2 << 4) /a MATCH_CTRL setting /
9325fa36 VW	74
	75	/* WDTIM_RES bit definitions */
	76	#define WDOG_RESET 1 /* read only */
	77
	78	#define WDOG_COUNTER_RATE 13000000 /the counter clock is 13 MHz fixed /
	79
28981727	80	static int nowayout = WATCHDOG_NOWAYOUT;
9325fa36 VW	81	static int heartbeat = DEFAULT_HEARTBEAT;
9325fa36 VW	82
c7dfd0cc	83	static DEFINE_SPINLOCK(io_lock);
9325fa36 VW	84	static unsigned long wdt_status;
	85	#define WDT_IN_USE 0
	86	#define WDT_OK_TO_CLOSE 1
9325fa36 VW	87
	88	static unsigned long boot_status;
	89
9325fa36 VW	90	static void __iomem *wdt_base;
	91	struct clk *wdt_clk;
	92
	93	static void wdt_enable(void)
	94	{
99d2853a WVS	95	spin_lock(&io_lock);
99d2853a WVS	96
9325fa36	97	/* stop counter, initiate counter reset */
7cbc3535	98	writel(RESET_COUNT, WDTIM_CTRL(wdt_base));
9325fa36	99	/wait for reset to complete. 100% guarantee event /
7cbc3535	100	while (readl(WDTIM_COUNTER(wdt_base)))
65a64ec3	101	cpu_relax();
9325fa36	102	/* internal and external reset, stop after that */
7cbc3535	103	writel(M_RES2 \| STOP_COUNT0 \| RESET_COUNT0, WDTIM_MCTRL(wdt_base));
9325fa36	104	/* configure match output */
7cbc3535	105	writel(MATCH_OUTPUT_HIGH, WDTIM_EMR(wdt_base));
9325fa36	106	/* clear interrupt, just in case */
7cbc3535	107	writel(MATCH_INT, WDTIM_INT(wdt_base));
9325fa36	108	/* the longest pulse period 65541/(1310^6) seconds ~ 5 ms. /
7cbc3535 WS	109	writel(0xFFFF, WDTIM_PULSE(wdt_base));
7cbc3535 WS	110	writel(heartbeat * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base));
9325fa36	111	/enable counter, stop when debugger active /
7cbc3535	112	writel(COUNT_ENAB \| DEBUG_EN, WDTIM_CTRL(wdt_base));
99d2853a WVS	113
99d2853a WVS	114	spin_unlock(&io_lock);
9325fa36 VW	115	}
	116
	117	static void wdt_disable(void)
	118	{
99d2853a WVS	119	spin_lock(&io_lock);
99d2853a WVS	120
7cbc3535	121	writel(0, WDTIM_CTRL(wdt_base)); /stop counter /
99d2853a WVS	122
99d2853a WVS	123	spin_unlock(&io_lock);
9325fa36 VW	124	}
	125
	126	static int pnx4008_wdt_open(struct inode inode, struct file file)
	127	{
24fd1eda RK	128	int ret;
24fd1eda RK	129
9325fa36 VW	130	if (test_and_set_bit(WDT_IN_USE, &wdt_status))
	131	return -EBUSY;
	132
	133	clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
	134
24fd1eda RK	135	ret = clk_enable(wdt_clk);
	136	if (ret) {
	137	clear_bit(WDT_IN_USE, &wdt_status);
	138	return ret;
	139	}
	140
9325fa36 VW	141	wdt_enable();
	142
	143	return nonseekable_open(inode, file);
	144	}
	145
84ca995c AC	146	static ssize_t pnx4008_wdt_write(struct file file, const char data,
84ca995c AC	147	size_t len, loff_t *ppos)
9325fa36	148	{
9325fa36 VW	149	if (len) {
	150	if (!nowayout) {
	151	size_t i;
	152
	153	clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
	154
	155	for (i = 0; i != len; i++) {
	156	char c;
	157
	158	if (get_user(c, data + i))
	159	return -EFAULT;
	160	if (c == 'V')
	161	set_bit(WDT_OK_TO_CLOSE, &wdt_status);
	162	}
	163	}
	164	wdt_enable();
	165	}
	166
	167	return len;
	168	}
	169
84ca995c	170	static const struct watchdog_info ident = {
9325fa36 VW	171	.options = WDIOF_CARDRESET \| WDIOF_MAGICCLOSE \|
	172	WDIOF_SETTIMEOUT \| WDIOF_KEEPALIVEPING,
	173	.identity = "PNX4008 Watchdog",
	174	};
	175
7275fc8c WVS	176	static long pnx4008_wdt_ioctl(struct file *file, unsigned int cmd,
7275fc8c WVS	177	unsigned long arg)
9325fa36	178	{
f311896a	179	int ret = -ENOTTY;
9325fa36 VW	180	int time;
	181
	182	switch (cmd) {
	183	case WDIOC_GETSUPPORT:
	184	ret = copy_to_user((struct watchdog_info *)arg, &ident,
	185	sizeof(ident)) ? -EFAULT : 0;
	186	break;
	187
	188	case WDIOC_GETSTATUS:
	189	ret = put_user(0, (int *)arg);
	190	break;
	191
	192	case WDIOC_GETBOOTSTATUS:
	193	ret = put_user(boot_status, (int *)arg);
	194	break;
	195
0c06090c WVS	196	case WDIOC_KEEPALIVE:
	197	wdt_enable();
	198	ret = 0;
	199	break;
	200
9325fa36 VW	201	case WDIOC_SETTIMEOUT:
	202	ret = get_user(time, (int *)arg);
	203	if (ret)
	204	break;
	205
	206	if (time <= 0 \|\| time > MAX_HEARTBEAT) {
	207	ret = -EINVAL;
	208	break;
	209	}
	210
	211	heartbeat = time;
	212	wdt_enable();
	213	/* Fall through */
	214
	215	case WDIOC_GETTIMEOUT:
	216	ret = put_user(heartbeat, (int *)arg);
	217	break;
9325fa36 VW	218	}
	219	return ret;
	220	}
	221
	222	static int pnx4008_wdt_release(struct inode inode, struct file file)
	223	{
	224	if (!test_bit(WDT_OK_TO_CLOSE, &wdt_status))
b1785dfd	225	printk(KERN_WARNING "WATCHDOG: Device closed unexpectedly\n");
9325fa36 VW	226
9325fa36 VW	227	wdt_disable();
24fd1eda	228	clk_disable(wdt_clk);
9325fa36 VW	229	clear_bit(WDT_IN_USE, &wdt_status);
	230	clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
	231
	232	return 0;
	233	}
	234
2b8693c0	235	static const struct file_operations pnx4008_wdt_fops = {
9325fa36 VW	236	.owner = THIS_MODULE,
	237	.llseek = no_llseek,
	238	.write = pnx4008_wdt_write,
84ca995c	239	.unlocked_ioctl = pnx4008_wdt_ioctl,
9325fa36 VW	240	.open = pnx4008_wdt_open,
	241	.release = pnx4008_wdt_release,
	242	};
	243
	244	static struct miscdevice pnx4008_wdt_miscdev = {
	245	.minor = WATCHDOG_MINOR,
	246	.name = "watchdog",
	247	.fops = &pnx4008_wdt_fops,
	248	};
	249
b6bf291f	250	static int __devinit pnx4008_wdt_probe(struct platform_device *pdev)
9325fa36	251	{
19f505f0 WS	252	struct resource *r;
19f505f0 WS	253	int ret = 0;
9325fa36 VW	254
	255	if (heartbeat < 1 \|\| heartbeat > MAX_HEARTBEAT)
	256	heartbeat = DEFAULT_HEARTBEAT;
	257
19f505f0 WS	258	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	259	wdt_base = devm_request_and_ioremap(&pdev->dev, r);
	260	if (!wdt_base)
	261	return -EADDRINUSE;
9325fa36	262
9bb787f4	263	wdt_clk = clk_get(&pdev->dev, NULL);
19f505f0 WS	264	if (IS_ERR(wdt_clk))
19f505f0 WS	265	return PTR_ERR(wdt_clk);
24fd1eda RK	266
24fd1eda RK	267	ret = clk_enable(wdt_clk);
19f505f0	268	if (ret)
24fd1eda	269	goto out;
19f505f0	270
7cbc3535 WS	271	boot_status = (readl(WDTIM_RES(wdt_base)) & WDOG_RESET) ?
7cbc3535 WS	272	WDIOF_CARDRESET : 0;
19f505f0 WS	273	wdt_disable(); /disable for now /
19f505f0 WS	274	clk_disable(wdt_clk);
9325fa36 VW	275
	276	ret = misc_register(&pnx4008_wdt_miscdev);
	277	if (ret < 0) {
19f505f0 WS	278	dev_err(&pdev->dev, "cannot register misc device\n");
19f505f0 WS	279	goto out;
9325fa36 VW	280	}
9325fa36 VW	281
19f505f0 WS	282	dev_info(&pdev->dev, "PNX4008 Watchdog Timer: heartbeat %d sec\n",
	283	heartbeat);
	284
	285	return 0;
	286
9325fa36	287	out:
19f505f0	288	clk_put(wdt_clk);
9325fa36 VW	289	return ret;
	290	}
	291
b6bf291f	292	static int __devexit pnx4008_wdt_remove(struct platform_device *pdev)
9325fa36	293	{
f6764497	294	misc_deregister(&pnx4008_wdt_miscdev);
24fd1eda RK	295
	296	clk_disable(wdt_clk);
	297	clk_put(wdt_clk);
	298
9325fa36 VW	299	return 0;
	300	}
	301
	302	static struct platform_driver platform_wdt_driver = {
	303	.driver = {
1508c995	304	.name = "pnx4008-watchdog",
f37d193c	305	.owner = THIS_MODULE,
9325fa36 VW	306	},
9325fa36 VW	307	.probe = pnx4008_wdt_probe,
b6bf291f	308	.remove = __devexit_p(pnx4008_wdt_remove),
9325fa36 VW	309	};
9325fa36 VW	310
b8ec6118	311	module_platform_driver(platform_wdt_driver);
9325fa36 VW	312
	313	MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
	314	MODULE_DESCRIPTION("PNX4008 Watchdog Driver");
	315
	316	module_param(heartbeat, int, 0);
	317	MODULE_PARM_DESC(heartbeat,
	318	"Watchdog heartbeat period in seconds from 1 to "
	319	__MODULE_STRING(MAX_HEARTBEAT) ", default "
	320	__MODULE_STRING(DEFAULT_HEARTBEAT));
	321
	322	module_param(nowayout, int, 0);
	323	MODULE_PARM_DESC(nowayout,
	324	"Set to 1 to keep watchdog running after device release");
	325
	326	MODULE_LICENSE("GPL");
	327	MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
1508c995	328	MODULE_ALIAS("platform:pnx4008-watchdog");