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1094ebe9 JC |
1 | /* Copyright (c) 2014, The Linux Foundation. All rights reserved. |
2 | * | |
3 | * This program is free software; you can redistribute it and/or modify | |
4 | * it under the terms of the GNU General Public License version 2 and | |
5 | * only version 2 as published by the Free Software Foundation. | |
6 | * | |
7 | * This program is distributed in the hope that it will be useful, | |
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
10 | * GNU General Public License for more details. | |
11 | * | |
12 | */ | |
13 | #include <linux/clk.h> | |
05e487d9 | 14 | #include <linux/delay.h> |
1094ebe9 JC |
15 | #include <linux/io.h> |
16 | #include <linux/kernel.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/of.h> | |
19 | #include <linux/platform_device.h> | |
20 | #include <linux/watchdog.h> | |
f0d9d0f4 | 21 | #include <linux/of_device.h> |
1094ebe9 | 22 | |
f0d9d0f4 MM |
23 | enum wdt_reg { |
24 | WDT_RST, | |
25 | WDT_EN, | |
26 | WDT_STS, | |
10073a20 | 27 | WDT_BARK_TIME, |
f0d9d0f4 MM |
28 | WDT_BITE_TIME, |
29 | }; | |
30 | ||
31 | static const u32 reg_offset_data_apcs_tmr[] = { | |
32 | [WDT_RST] = 0x38, | |
33 | [WDT_EN] = 0x40, | |
34 | [WDT_STS] = 0x44, | |
10073a20 | 35 | [WDT_BARK_TIME] = 0x4C, |
f0d9d0f4 MM |
36 | [WDT_BITE_TIME] = 0x5C, |
37 | }; | |
38 | ||
39 | static const u32 reg_offset_data_kpss[] = { | |
40 | [WDT_RST] = 0x4, | |
41 | [WDT_EN] = 0x8, | |
42 | [WDT_STS] = 0xC, | |
10073a20 | 43 | [WDT_BARK_TIME] = 0x10, |
f0d9d0f4 MM |
44 | [WDT_BITE_TIME] = 0x14, |
45 | }; | |
1094ebe9 JC |
46 | |
47 | struct qcom_wdt { | |
48 | struct watchdog_device wdd; | |
49 | struct clk *clk; | |
50 | unsigned long rate; | |
51 | void __iomem *base; | |
f0d9d0f4 | 52 | const u32 *layout; |
1094ebe9 JC |
53 | }; |
54 | ||
f0d9d0f4 MM |
55 | static void __iomem *wdt_addr(struct qcom_wdt *wdt, enum wdt_reg reg) |
56 | { | |
57 | return wdt->base + wdt->layout[reg]; | |
58 | } | |
59 | ||
1094ebe9 JC |
60 | static inline |
61 | struct qcom_wdt *to_qcom_wdt(struct watchdog_device *wdd) | |
62 | { | |
63 | return container_of(wdd, struct qcom_wdt, wdd); | |
64 | } | |
65 | ||
66 | static int qcom_wdt_start(struct watchdog_device *wdd) | |
67 | { | |
68 | struct qcom_wdt *wdt = to_qcom_wdt(wdd); | |
69 | ||
f0d9d0f4 MM |
70 | writel(0, wdt_addr(wdt, WDT_EN)); |
71 | writel(1, wdt_addr(wdt, WDT_RST)); | |
10073a20 | 72 | writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME)); |
f0d9d0f4 MM |
73 | writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME)); |
74 | writel(1, wdt_addr(wdt, WDT_EN)); | |
1094ebe9 JC |
75 | return 0; |
76 | } | |
77 | ||
78 | static int qcom_wdt_stop(struct watchdog_device *wdd) | |
79 | { | |
80 | struct qcom_wdt *wdt = to_qcom_wdt(wdd); | |
81 | ||
f0d9d0f4 | 82 | writel(0, wdt_addr(wdt, WDT_EN)); |
1094ebe9 JC |
83 | return 0; |
84 | } | |
85 | ||
86 | static int qcom_wdt_ping(struct watchdog_device *wdd) | |
87 | { | |
88 | struct qcom_wdt *wdt = to_qcom_wdt(wdd); | |
89 | ||
f0d9d0f4 | 90 | writel(1, wdt_addr(wdt, WDT_RST)); |
1094ebe9 JC |
91 | return 0; |
92 | } | |
93 | ||
94 | static int qcom_wdt_set_timeout(struct watchdog_device *wdd, | |
95 | unsigned int timeout) | |
96 | { | |
97 | wdd->timeout = timeout; | |
98 | return qcom_wdt_start(wdd); | |
99 | } | |
100 | ||
4d8b229d GR |
101 | static int qcom_wdt_restart(struct watchdog_device *wdd, unsigned long action, |
102 | void *data) | |
05e487d9 | 103 | { |
80969a68 | 104 | struct qcom_wdt *wdt = to_qcom_wdt(wdd); |
05e487d9 JC |
105 | u32 timeout; |
106 | ||
107 | /* | |
108 | * Trigger watchdog bite: | |
109 | * Setup BITE_TIME to be 128ms, and enable WDT. | |
110 | */ | |
111 | timeout = 128 * wdt->rate / 1000; | |
112 | ||
f0d9d0f4 MM |
113 | writel(0, wdt_addr(wdt, WDT_EN)); |
114 | writel(1, wdt_addr(wdt, WDT_RST)); | |
10073a20 | 115 | writel(timeout, wdt_addr(wdt, WDT_BARK_TIME)); |
f0d9d0f4 MM |
116 | writel(timeout, wdt_addr(wdt, WDT_BITE_TIME)); |
117 | writel(1, wdt_addr(wdt, WDT_EN)); | |
05e487d9 JC |
118 | |
119 | /* | |
120 | * Actually make sure the above sequence hits hardware before sleeping. | |
121 | */ | |
122 | wmb(); | |
123 | ||
124 | msleep(150); | |
80969a68 | 125 | return 0; |
05e487d9 JC |
126 | } |
127 | ||
80969a68 DR |
128 | static const struct watchdog_ops qcom_wdt_ops = { |
129 | .start = qcom_wdt_start, | |
130 | .stop = qcom_wdt_stop, | |
131 | .ping = qcom_wdt_ping, | |
132 | .set_timeout = qcom_wdt_set_timeout, | |
133 | .restart = qcom_wdt_restart, | |
134 | .owner = THIS_MODULE, | |
135 | }; | |
136 | ||
137 | static const struct watchdog_info qcom_wdt_info = { | |
138 | .options = WDIOF_KEEPALIVEPING | |
139 | | WDIOF_MAGICCLOSE | |
b6ef36d2 GR |
140 | | WDIOF_SETTIMEOUT |
141 | | WDIOF_CARDRESET, | |
80969a68 DR |
142 | .identity = KBUILD_MODNAME, |
143 | }; | |
144 | ||
1094ebe9 JC |
145 | static int qcom_wdt_probe(struct platform_device *pdev) |
146 | { | |
147 | struct qcom_wdt *wdt; | |
148 | struct resource *res; | |
0dfd582e | 149 | struct device_node *np = pdev->dev.of_node; |
f0d9d0f4 | 150 | const u32 *regs; |
0dfd582e | 151 | u32 percpu_offset; |
1094ebe9 JC |
152 | int ret; |
153 | ||
f0d9d0f4 MM |
154 | regs = of_device_get_match_data(&pdev->dev); |
155 | if (!regs) { | |
156 | dev_err(&pdev->dev, "Unsupported QCOM WDT module\n"); | |
157 | return -ENODEV; | |
158 | } | |
159 | ||
1094ebe9 JC |
160 | wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL); |
161 | if (!wdt) | |
162 | return -ENOMEM; | |
163 | ||
164 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
0dfd582e MO |
165 | |
166 | /* We use CPU0's DGT for the watchdog */ | |
167 | if (of_property_read_u32(np, "cpu-offset", &percpu_offset)) | |
168 | percpu_offset = 0; | |
169 | ||
170 | res->start += percpu_offset; | |
171 | res->end += percpu_offset; | |
172 | ||
1094ebe9 JC |
173 | wdt->base = devm_ioremap_resource(&pdev->dev, res); |
174 | if (IS_ERR(wdt->base)) | |
175 | return PTR_ERR(wdt->base); | |
176 | ||
177 | wdt->clk = devm_clk_get(&pdev->dev, NULL); | |
178 | if (IS_ERR(wdt->clk)) { | |
179 | dev_err(&pdev->dev, "failed to get input clock\n"); | |
180 | return PTR_ERR(wdt->clk); | |
181 | } | |
182 | ||
183 | ret = clk_prepare_enable(wdt->clk); | |
184 | if (ret) { | |
185 | dev_err(&pdev->dev, "failed to setup clock\n"); | |
186 | return ret; | |
187 | } | |
188 | ||
189 | /* | |
190 | * We use the clock rate to calculate the max timeout, so ensure it's | |
191 | * not zero to avoid a divide-by-zero exception. | |
192 | * | |
193 | * WATCHDOG_CORE assumes units of seconds, if the WDT is clocked such | |
194 | * that it would bite before a second elapses it's usefulness is | |
195 | * limited. Bail if this is the case. | |
196 | */ | |
197 | wdt->rate = clk_get_rate(wdt->clk); | |
198 | if (wdt->rate == 0 || | |
199 | wdt->rate > 0x10000000U) { | |
200 | dev_err(&pdev->dev, "invalid clock rate\n"); | |
201 | ret = -EINVAL; | |
202 | goto err_clk_unprepare; | |
203 | } | |
204 | ||
1094ebe9 JC |
205 | wdt->wdd.info = &qcom_wdt_info; |
206 | wdt->wdd.ops = &qcom_wdt_ops; | |
207 | wdt->wdd.min_timeout = 1; | |
208 | wdt->wdd.max_timeout = 0x10000000U / wdt->rate; | |
6551881c | 209 | wdt->wdd.parent = &pdev->dev; |
f0d9d0f4 | 210 | wdt->layout = regs; |
1094ebe9 | 211 | |
b6ef36d2 GR |
212 | if (readl(wdt->base + WDT_STS) & 1) |
213 | wdt->wdd.bootstatus = WDIOF_CARDRESET; | |
214 | ||
1094ebe9 JC |
215 | /* |
216 | * If 'timeout-sec' unspecified in devicetree, assume a 30 second | |
217 | * default, unless the max timeout is less than 30 seconds, then use | |
218 | * the max instead. | |
219 | */ | |
220 | wdt->wdd.timeout = min(wdt->wdd.max_timeout, 30U); | |
221 | watchdog_init_timeout(&wdt->wdd, 0, &pdev->dev); | |
222 | ||
223 | ret = watchdog_register_device(&wdt->wdd); | |
224 | if (ret) { | |
225 | dev_err(&pdev->dev, "failed to register watchdog\n"); | |
226 | goto err_clk_unprepare; | |
227 | } | |
228 | ||
229 | platform_set_drvdata(pdev, wdt); | |
230 | return 0; | |
231 | ||
232 | err_clk_unprepare: | |
233 | clk_disable_unprepare(wdt->clk); | |
234 | return ret; | |
235 | } | |
236 | ||
237 | static int qcom_wdt_remove(struct platform_device *pdev) | |
238 | { | |
239 | struct qcom_wdt *wdt = platform_get_drvdata(pdev); | |
240 | ||
241 | watchdog_unregister_device(&wdt->wdd); | |
242 | clk_disable_unprepare(wdt->clk); | |
243 | return 0; | |
244 | } | |
245 | ||
246 | static const struct of_device_id qcom_wdt_of_table[] = { | |
f0d9d0f4 MM |
247 | { .compatible = "qcom,kpss-timer", .data = reg_offset_data_apcs_tmr }, |
248 | { .compatible = "qcom,scss-timer", .data = reg_offset_data_apcs_tmr }, | |
249 | { .compatible = "qcom,kpss-wdt", .data = reg_offset_data_kpss }, | |
1094ebe9 JC |
250 | { }, |
251 | }; | |
252 | MODULE_DEVICE_TABLE(of, qcom_wdt_of_table); | |
253 | ||
254 | static struct platform_driver qcom_watchdog_driver = { | |
255 | .probe = qcom_wdt_probe, | |
256 | .remove = qcom_wdt_remove, | |
257 | .driver = { | |
258 | .name = KBUILD_MODNAME, | |
259 | .of_match_table = qcom_wdt_of_table, | |
260 | }, | |
261 | }; | |
262 | module_platform_driver(qcom_watchdog_driver); | |
263 | ||
264 | MODULE_DESCRIPTION("QCOM KPSS Watchdog Driver"); | |
265 | MODULE_LICENSE("GPL v2"); |