[deliverable/linux.git] / drivers / watchdog / rc32434_wdt.c

/*
 *  IDT Interprise 79RC32434 watchdog driver
 *
 *  Copyright (C) 2006, Ondrej Zajicek <santiago@crfreenet.org>
 *  Copyright (C) 2008, Florian Fainelli <florian@openwrt.org>
 *
 *  based on
 *  SoftDog 0.05:	A Software Watchdog Device
 *
 *  (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>,
 *					All Rights Reserved.
 *
 *  This program is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU General Public License
 *  as published by the Free Software Foundation; either version
 *  2 of the License, or (at your option) any later version.
 *
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/module.h>		/* For module specific items */
#include <linux/moduleparam.h>		/* For new moduleparam's */
#include <linux/types.h>		/* For standard types (like size_t) */
#include <linux/errno.h>		/* For the -ENODEV/... values */
#include <linux/kernel.h>		/* For printk/panic/... */
#include <linux/fs.h>			/* For file operations */
#include <linux/miscdevice.h>		/* For MODULE_ALIAS_MISCDEV
							(WATCHDOG_MINOR) */
#include <linux/watchdog.h>		/* For the watchdog specific items */
#include <linux/init.h>			/* For __init/__exit/... */
#include <linux/platform_device.h>	/* For platform_driver framework */
#include <linux/spinlock.h>		/* For spin_lock/spin_unlock/... */
#include <linux/uaccess.h>		/* For copy_to_user/put_user/... */
#include <linux/io.h>			/* For devm_ioremap_nocache */

#include <asm/mach-rc32434/integ.h>	/* For the Watchdog registers */

#define VERSION "1.0"

static struct {
	unsigned long inuse;
	spinlock_t io_lock;
} rc32434_wdt_device;

static struct integ __iomem *wdt_reg;

static int expect_close;

/* Board internal clock speed in Hz,
 * the watchdog timer ticks at. */
extern unsigned int idt_cpu_freq;

/* translate wtcompare value to seconds and vice versa */
#define WTCOMP2SEC(x)	(x / idt_cpu_freq)
#define SEC2WTCOMP(x)	(x * idt_cpu_freq)

/* Use a default timeout of 20s. This should be
 * safe for CPU clock speeds up to 400MHz, as
 * ((2 ^ 32) - 1) / (400MHz / 2) = 21s.  */
#define WATCHDOG_TIMEOUT 20

static int timeout = WATCHDOG_TIMEOUT;
module_param(timeout, int, 0);
MODULE_PARM_DESC(timeout, "Watchdog timeout value, in seconds (default="
		__MODULE_STRING(WATCHDOG_TIMEOUT) ")");

static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

/* apply or and nand masks to data read from addr and write back */
#define SET_BITS(addr, or, nand) \
	writel((readl(&addr) | or) & ~nand, &addr)

static int rc32434_wdt_set(int new_timeout)
{
	int max_to = WTCOMP2SEC((u32)-1);

	if (new_timeout < 0 || new_timeout > max_to) {
		pr_err("timeout value must be between 0 and %d\n", max_to);
		return -EINVAL;
	}
	timeout = new_timeout;
	spin_lock(&rc32434_wdt_device.io_lock);
	writel(SEC2WTCOMP(timeout), &wdt_reg->wtcompare);
	spin_unlock(&rc32434_wdt_device.io_lock);

	return 0;
}

static void rc32434_wdt_start(void)
{
	u32 or, nand;

	spin_lock(&rc32434_wdt_device.io_lock);

	/* zero the counter before enabling */
	writel(0, &wdt_reg->wtcount);

	/* don't generate a non-maskable interrupt,
	 * do a warm reset instead */
	nand = 1 << RC32434_ERR_WNE;
	or = 1 << RC32434_ERR_WRE;

	/* reset the ERRCS timeout bit in case it's set */
	nand |= 1 << RC32434_ERR_WTO;

	SET_BITS(wdt_reg->errcs, or, nand);

	/* set the timeout (either default or based on module param) */
	rc32434_wdt_set(timeout);

	/* reset WTC timeout bit and enable WDT */
	nand = 1 << RC32434_WTC_TO;
	or = 1 << RC32434_WTC_EN;

	SET_BITS(wdt_reg->wtc, or, nand);

	spin_unlock(&rc32434_wdt_device.io_lock);
	pr_info("Started watchdog timer\n");
}

static void rc32434_wdt_stop(void)
{
	spin_lock(&rc32434_wdt_device.io_lock);

	/* Disable WDT */
	SET_BITS(wdt_reg->wtc, 0, 1 << RC32434_WTC_EN);

	spin_unlock(&rc32434_wdt_device.io_lock);
	pr_info("Stopped watchdog timer\n");
}

static void rc32434_wdt_ping(void)
{
	spin_lock(&rc32434_wdt_device.io_lock);
	writel(0, &wdt_reg->wtcount);
	spin_unlock(&rc32434_wdt_device.io_lock);
}

static int rc32434_wdt_open(struct inode *inode, struct file *file)
{
	if (test_and_set_bit(0, &rc32434_wdt_device.inuse))
		return -EBUSY;

	if (nowayout)
		__module_get(THIS_MODULE);

	rc32434_wdt_start();
	rc32434_wdt_ping();

	return nonseekable_open(inode, file);
}

static int rc32434_wdt_release(struct inode *inode, struct file *file)
{
	if (expect_close == 42) {
		rc32434_wdt_stop();
		module_put(THIS_MODULE);
	} else {
		pr_crit("device closed unexpectedly. WDT will not stop!\n");
		rc32434_wdt_ping();
	}
	clear_bit(0, &rc32434_wdt_device.inuse);
	return 0;
}

static ssize_t rc32434_wdt_write(struct file *file, const char *data,
				size_t len, loff_t *ppos)
{
	if (len) {
		if (!nowayout) {
			size_t i;

			/* In case it was set long ago */
			expect_close = 0;

			for (i = 0; i != len; i++) {
				char c;
				if (get_user(c, data + i))
					return -EFAULT;
				if (c == 'V')
					expect_close = 42;
			}
		}
		rc32434_wdt_ping();
		return len;
	}
	return 0;
}

static long rc32434_wdt_ioctl(struct file *file, unsigned int cmd,
				unsigned long arg)
{
	void __user *argp = (void __user *)arg;
	int new_timeout;
	unsigned int value;
	static const struct watchdog_info ident = {
		.options =		WDIOF_SETTIMEOUT |
					WDIOF_KEEPALIVEPING |
					WDIOF_MAGICCLOSE,
		.identity =		"RC32434_WDT Watchdog",
	};
	switch (cmd) {
	case WDIOC_GETSUPPORT:
		if (copy_to_user(argp, &ident, sizeof(ident)))
			return -EFAULT;
		break;
	case WDIOC_GETSTATUS:
	case WDIOC_GETBOOTSTATUS:
		value = 0;
		if (copy_to_user(argp, &value, sizeof(int)))
			return -EFAULT;
		break;
	case WDIOC_SETOPTIONS:
		if (copy_from_user(&value, argp, sizeof(int)))
			return -EFAULT;
		switch (value) {
		case WDIOS_ENABLECARD:
			rc32434_wdt_start();
			break;
		case WDIOS_DISABLECARD:
			rc32434_wdt_stop();
			break;
		default:
			return -EINVAL;
		}
		break;
	case WDIOC_KEEPALIVE:
		rc32434_wdt_ping();
		break;
	case WDIOC_SETTIMEOUT:
		if (copy_from_user(&new_timeout, argp, sizeof(int)))
			return -EFAULT;
		if (rc32434_wdt_set(new_timeout))
			return -EINVAL;
		/* Fall through */
	case WDIOC_GETTIMEOUT:
		return copy_to_user(argp, &timeout, sizeof(int));
	default:
		return -ENOTTY;
	}

	return 0;
}

static const struct file_operations rc32434_wdt_fops = {
	.owner		= THIS_MODULE,
	.llseek		= no_llseek,
	.write		= rc32434_wdt_write,
	.unlocked_ioctl	= rc32434_wdt_ioctl,
	.open		= rc32434_wdt_open,
	.release	= rc32434_wdt_release,
};

static struct miscdevice rc32434_wdt_miscdev = {
	.minor	= WATCHDOG_MINOR,
	.name	= "watchdog",
	.fops	= &rc32434_wdt_fops,
};

static int rc32434_wdt_probe(struct platform_device *pdev)
{
	int ret;
	struct resource *r;

	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rb532_wdt_res");
	if (!r) {
		pr_err("failed to retrieve resources\n");
		return -ENODEV;
	}

	wdt_reg = devm_ioremap_nocache(&pdev->dev, r->start, resource_size(r));
	if (!wdt_reg) {
		pr_err("failed to remap I/O resources\n");
		return -ENXIO;
	}

	spin_lock_init(&rc32434_wdt_device.io_lock);

	/* Make sure the watchdog is not running */
	rc32434_wdt_stop();

	/* Check that the heartbeat value is within it's range;
	 * if not reset to the default */
	if (rc32434_wdt_set(timeout)) {
		rc32434_wdt_set(WATCHDOG_TIMEOUT);
		pr_info("timeout value must be between 0 and %d\n",
			WTCOMP2SEC((u32)-1));
	}

	ret = misc_register(&rc32434_wdt_miscdev);
	if (ret < 0) {
		pr_err("failed to register watchdog device\n");
		return ret;
	}

	pr_info("Watchdog Timer version " VERSION ", timer margin: %d sec\n",
		timeout);

	return 0;
}

static int rc32434_wdt_remove(struct platform_device *pdev)
{
	misc_deregister(&rc32434_wdt_miscdev);
	return 0;
}

static void rc32434_wdt_shutdown(struct platform_device *pdev)
{
	rc32434_wdt_stop();
}

static struct platform_driver rc32434_wdt_driver = {
	.probe		= rc32434_wdt_probe,
	.remove		= rc32434_wdt_remove,
	.shutdown	= rc32434_wdt_shutdown,
	.driver		= {
			.name = "rc32434_wdt",
	}
};

module_platform_driver(rc32434_wdt_driver);

MODULE_AUTHOR("Ondrej Zajicek <santiago@crfreenet.org>,"
		"Florian Fainelli <florian@openwrt.org>");
MODULE_DESCRIPTION("Driver for the IDT RC32434 SoC watchdog");
MODULE_LICENSE("GPL");
MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
Commit	Line	Data
03ec5856 FF	1	/*
	2	* IDT Interprise 79RC32434 watchdog driver
	3	*
	4	* Copyright (C) 2006, Ondrej Zajicek <santiago@crfreenet.org>
	5	* Copyright (C) 2008, Florian Fainelli <florian@openwrt.org>
	6	*
	7	* based on
	8	* SoftDog 0.05: A Software Watchdog Device
	9	*
29fa0586 AC	10	* (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>,
29fa0586 AC	11	* All Rights Reserved.
03ec5856 FF	12	*
	13	* This program is free software; you can redistribute it and/or
	14	* modify it under the terms of the GNU General Public License
	15	* as published by the Free Software Foundation; either version
	16	* 2 of the License, or (at your option) any later version.
	17	*
	18	*/
	19
27c766aa JP	20	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27c766aa JP	21
9b655e07 PS	22	#include <linux/module.h> /* For module specific items */
	23	#include <linux/moduleparam.h> /* For new moduleparam's */
	24	#include <linux/types.h> /* For standard types (like size_t) */
	25	#include <linux/errno.h> /* For the -ENODEV/... values */
	26	#include <linux/kernel.h> /* For printk/panic/... */
	27	#include <linux/fs.h> /* For file operations */
	28	#include <linux/miscdevice.h> /* For MODULE_ALIAS_MISCDEV
	29	(WATCHDOG_MINOR) */
	30	#include <linux/watchdog.h> /* For the watchdog specific items */
	31	#include <linux/init.h> /* For __init/__exit/... */
	32	#include <linux/platform_device.h> /* For platform_driver framework */
e455b6b4	33	#include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */
9b655e07	34	#include <linux/uaccess.h> /* For copy_to_user/put_user/... */
52ccc5ac	35	#include <linux/io.h> /* For devm_ioremap_nocache */
9b655e07 PS	36
	37	#include <asm/mach-rc32434/integ.h> /* For the Watchdog registers */
	38
f296b143	39	#define VERSION "1.0"
03ec5856 FF	40
03ec5856 FF	41	static struct {
03ec5856	42	unsigned long inuse;
e455b6b4	43	spinlock_t io_lock;
03ec5856 FF	44	} rc32434_wdt_device;
	45
	46	static struct integ __iomem *wdt_reg;
03ec5856 FF	47
03ec5856 FF	48	static int expect_close;
0af98d37 PS	49
	50	/* Board internal clock speed in Hz,
	51	* the watchdog timer ticks at. */
	52	extern unsigned int idt_cpu_freq;
	53
	54	/* translate wtcompare value to seconds and vice versa */
	55	#define WTCOMP2SEC(x) (x / idt_cpu_freq)
	56	#define SEC2WTCOMP(x) (x * idt_cpu_freq)
	57
	58	/* Use a default timeout of 20s. This should be
	59	* safe for CPU clock speeds up to 400MHz, as
	60	* ((2 ^ 32) - 1) / (400MHz / 2) = 21s. */
	61	#define WATCHDOG_TIMEOUT 20
	62
	63	static int timeout = WATCHDOG_TIMEOUT;
08eb2e0c PS	64	module_param(timeout, int, 0);
08eb2e0c PS	65	MODULE_PARM_DESC(timeout, "Watchdog timeout value, in seconds (default="
810a90ae	66	__MODULE_STRING(WATCHDOG_TIMEOUT) ")");
03ec5856	67
86a1e189 WVS	68	static bool nowayout = WATCHDOG_NOWAYOUT;
86a1e189 WVS	69	module_param(nowayout, bool, 0);
03ec5856 FF	70	MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
	71	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
	72
0af98d37 PS	73	/* apply or and nand masks to data read from addr and write back */
	74	#define SET_BITS(addr, or, nand) \
	75	writel((readl(&addr) \| or) & ~nand, &addr)
03ec5856	76
08eb2e0c PS	77	static int rc32434_wdt_set(int new_timeout)
	78	{
	79	int max_to = WTCOMP2SEC((u32)-1);
	80
	81	if (new_timeout < 0 \|\| new_timeout > max_to) {
27c766aa	82	pr_err("timeout value must be between 0 and %d\n", max_to);
08eb2e0c PS	83	return -EINVAL;
	84	}
	85	timeout = new_timeout;
e455b6b4	86	spin_lock(&rc32434_wdt_device.io_lock);
08eb2e0c	87	writel(SEC2WTCOMP(timeout), &wdt_reg->wtcompare);
e455b6b4	88	spin_unlock(&rc32434_wdt_device.io_lock);
08eb2e0c PS	89
	90	return 0;
	91	}
	92
03ec5856 FF	93	static void rc32434_wdt_start(void)
03ec5856 FF	94	{
0af98d37	95	u32 or, nand;
03ec5856	96
e455b6b4 WVS	97	spin_lock(&rc32434_wdt_device.io_lock);
e455b6b4 WVS	98
0af98d37 PS	99	/* zero the counter before enabling */
0af98d37 PS	100	writel(0, &wdt_reg->wtcount);
03ec5856	101
0af98d37 PS	102	/* don't generate a non-maskable interrupt,
	103	* do a warm reset instead */
	104	nand = 1 << RC32434_ERR_WNE;
	105	or = 1 << RC32434_ERR_WRE;
03ec5856	106
0af98d37 PS	107	/* reset the ERRCS timeout bit in case it's set */
0af98d37 PS	108	nand \|= 1 << RC32434_ERR_WTO;
03ec5856	109
0af98d37	110	SET_BITS(wdt_reg->errcs, or, nand);
03ec5856	111
08eb2e0c PS	112	/* set the timeout (either default or based on module param) */
	113	rc32434_wdt_set(timeout);
	114
0af98d37 PS	115	/* reset WTC timeout bit and enable WDT */
	116	nand = 1 << RC32434_WTC_TO;
	117	or = 1 << RC32434_WTC_EN;
03ec5856	118
0af98d37	119	SET_BITS(wdt_reg->wtc, or, nand);
9b655e07	120
e455b6b4	121	spin_unlock(&rc32434_wdt_device.io_lock);
27c766aa	122	pr_info("Started watchdog timer\n");
0af98d37	123	}
03ec5856	124
0af98d37 PS	125	static void rc32434_wdt_stop(void)
0af98d37 PS	126	{
e455b6b4 WVS	127	spin_lock(&rc32434_wdt_device.io_lock);
e455b6b4 WVS	128
0af98d37 PS	129	/* Disable WDT */
0af98d37 PS	130	SET_BITS(wdt_reg->wtc, 0, 1 << RC32434_WTC_EN);
9b655e07	131
e455b6b4	132	spin_unlock(&rc32434_wdt_device.io_lock);
27c766aa	133	pr_info("Stopped watchdog timer\n");
03ec5856 FF	134	}
03ec5856 FF	135
0af98d37	136	static void rc32434_wdt_ping(void)
03ec5856	137	{
e455b6b4	138	spin_lock(&rc32434_wdt_device.io_lock);
03ec5856	139	writel(0, &wdt_reg->wtcount);
e455b6b4	140	spin_unlock(&rc32434_wdt_device.io_lock);
03ec5856 FF	141	}
	142
	143	static int rc32434_wdt_open(struct inode inode, struct file file)
	144	{
	145	if (test_and_set_bit(0, &rc32434_wdt_device.inuse))
	146	return -EBUSY;
	147
	148	if (nowayout)
	149	__module_get(THIS_MODULE);
	150
0af98d37 PS	151	rc32434_wdt_start();
	152	rc32434_wdt_ping();
	153
03ec5856 FF	154	return nonseekable_open(inode, file);
	155	}
	156
	157	static int rc32434_wdt_release(struct inode inode, struct file file)
	158	{
0af98d37	159	if (expect_close == 42) {
03ec5856	160	rc32434_wdt_stop();
03ec5856	161	module_put(THIS_MODULE);
0af98d37	162	} else {
27c766aa	163	pr_crit("device closed unexpectedly. WDT will not stop!\n");
0af98d37 PS	164	rc32434_wdt_ping();
0af98d37 PS	165	}
03ec5856 FF	166	clear_bit(0, &rc32434_wdt_device.inuse);
	167	return 0;
	168	}
	169
	170	static ssize_t rc32434_wdt_write(struct file file, const char data,
	171	size_t len, loff_t *ppos)
	172	{
	173	if (len) {
	174	if (!nowayout) {
	175	size_t i;
	176
	177	/* In case it was set long ago */
	178	expect_close = 0;
	179
	180	for (i = 0; i != len; i++) {
	181	char c;
	182	if (get_user(c, data + i))
	183	return -EFAULT;
	184	if (c == 'V')
0af98d37	185	expect_close = 42;
03ec5856 FF	186	}
03ec5856 FF	187	}
0af98d37	188	rc32434_wdt_ping();
03ec5856 FF	189	return len;
	190	}
	191	return 0;
	192	}
	193
7275fc8c WVS	194	static long rc32434_wdt_ioctl(struct file *file, unsigned int cmd,
7275fc8c WVS	195	unsigned long arg)
03ec5856 FF	196	{
	197	void __user argp = (void __user )arg;
	198	int new_timeout;
	199	unsigned int value;
42747d71	200	static const struct watchdog_info ident = {
03ec5856 FF	201	.options = WDIOF_SETTIMEOUT \|
	202	WDIOF_KEEPALIVEPING \|
	203	WDIOF_MAGICCLOSE,
	204	.identity = "RC32434_WDT Watchdog",
	205	};
	206	switch (cmd) {
9b655e07 PS	207	case WDIOC_GETSUPPORT:
	208	if (copy_to_user(argp, &ident, sizeof(ident)))
	209	return -EFAULT;
03ec5856 FF	210	break;
	211	case WDIOC_GETSTATUS:
	212	case WDIOC_GETBOOTSTATUS:
0af98d37	213	value = 0;
03ec5856 FF	214	if (copy_to_user(argp, &value, sizeof(int)))
	215	return -EFAULT;
	216	break;
03ec5856 FF	217	case WDIOC_SETOPTIONS:
	218	if (copy_from_user(&value, argp, sizeof(int)))
	219	return -EFAULT;
	220	switch (value) {
	221	case WDIOS_ENABLECARD:
	222	rc32434_wdt_start();
	223	break;
	224	case WDIOS_DISABLECARD:
	225	rc32434_wdt_stop();
0af98d37	226	break;
03ec5856 FF	227	default:
	228	return -EINVAL;
	229	}
	230	break;
9b655e07 PS	231	case WDIOC_KEEPALIVE:
	232	rc32434_wdt_ping();
	233	break;
03ec5856 FF	234	case WDIOC_SETTIMEOUT:
	235	if (copy_from_user(&new_timeout, argp, sizeof(int)))
	236	return -EFAULT;
0af98d37	237	if (rc32434_wdt_set(new_timeout))
03ec5856	238	return -EINVAL;
0af98d37	239	/* Fall through */
03ec5856 FF	240	case WDIOC_GETTIMEOUT:
	241	return copy_to_user(argp, &timeout, sizeof(int));
	242	default:
	243	return -ENOTTY;
	244	}
	245
	246	return 0;
	247	}
	248
d5c26a59	249	static const struct file_operations rc32434_wdt_fops = {
03ec5856 FF	250	.owner = THIS_MODULE,
	251	.llseek = no_llseek,
	252	.write = rc32434_wdt_write,
7275fc8c	253	.unlocked_ioctl = rc32434_wdt_ioctl,
03ec5856 FF	254	.open = rc32434_wdt_open,
	255	.release = rc32434_wdt_release,
	256	};
	257
	258	static struct miscdevice rc32434_wdt_miscdev = {
	259	.minor = WATCHDOG_MINOR,
	260	.name = "watchdog",
	261	.fops = &rc32434_wdt_fops,
	262	};
	263
2d991a16	264	static int rc32434_wdt_probe(struct platform_device *pdev)
03ec5856 FF	265	{
	266	int ret;
	267	struct resource *r;
	268
0af98d37	269	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rb532_wdt_res");
03ec5856	270	if (!r) {
27c766aa	271	pr_err("failed to retrieve resources\n");
03ec5856 FF	272	return -ENODEV;
	273	}
	274
52ccc5ac	275	wdt_reg = devm_ioremap_nocache(&pdev->dev, r->start, resource_size(r));
03ec5856	276	if (!wdt_reg) {
27c766aa	277	pr_err("failed to remap I/O resources\n");
03ec5856 FF	278	return -ENXIO;
	279	}
	280
e455b6b4 WVS	281	spin_lock_init(&rc32434_wdt_device.io_lock);
e455b6b4 WVS	282
f296b143 WVS	283	/* Make sure the watchdog is not running */
	284	rc32434_wdt_stop();
	285
08eb2e0c PS	286	/* Check that the heartbeat value is within it's range;
	287	* if not reset to the default */
	288	if (rc32434_wdt_set(timeout)) {
	289	rc32434_wdt_set(WATCHDOG_TIMEOUT);
27c766aa	290	pr_info("timeout value must be between 0 and %d\n",
08eb2e0c PS	291	WTCOMP2SEC((u32)-1));
	292	}
	293
03ec5856	294	ret = misc_register(&rc32434_wdt_miscdev);
03ec5856	295	if (ret < 0) {
27c766aa	296	pr_err("failed to register watchdog device\n");
52ccc5ac	297	return ret;
03ec5856 FF	298	}
03ec5856 FF	299
27c766aa JP	300	pr_info("Watchdog Timer version " VERSION ", timer margin: %d sec\n",
27c766aa JP	301	timeout);
03ec5856 FF	302
03ec5856 FF	303	return 0;
03ec5856 FF	304	}
03ec5856 FF	305
4b12b896	306	static int rc32434_wdt_remove(struct platform_device *pdev)
03ec5856	307	{
03ec5856	308	misc_deregister(&rc32434_wdt_miscdev);
03ec5856 FF	309	return 0;
	310	}
	311
0aaae661 WVS	312	static void rc32434_wdt_shutdown(struct platform_device *pdev)
	313	{
	314	rc32434_wdt_stop();
	315	}
	316
9b655e07	317	static struct platform_driver rc32434_wdt_driver = {
0aaae661	318	.probe = rc32434_wdt_probe,
82268714	319	.remove = rc32434_wdt_remove,
0aaae661 WVS	320	.shutdown = rc32434_wdt_shutdown,
	321	.driver = {
	322	.name = "rc32434_wdt",
03ec5856 FF	323	}
	324	};
	325
b8ec6118	326	module_platform_driver(rc32434_wdt_driver);
03ec5856 FF	327
	328	MODULE_AUTHOR("Ondrej Zajicek <santiago@crfreenet.org>,"
	329	"Florian Fainelli <florian@openwrt.org>");
	330	MODULE_DESCRIPTION("Driver for the IDT RC32434 SoC watchdog");
	331	MODULE_LICENSE("GPL");
	332	MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);