Commit | Line | Data |
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1da177e4 LT |
1 | /* linux/drivers/char/watchdog/s3c2410_wdt.c |
2 | * | |
3 | * Copyright (c) 2004 Simtec Electronics | |
4 | * Ben Dooks <ben@simtec.co.uk> | |
5 | * | |
6 | * S3C2410 Watchdog Timer Support | |
7 | * | |
8 | * Based on, softdog.c by Alan Cox, | |
29fa0586 | 9 | * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk> |
1da177e4 LT |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
1da177e4 LT |
24 | */ |
25 | ||
27c766aa JP |
26 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
27 | ||
1da177e4 LT |
28 | #include <linux/module.h> |
29 | #include <linux/moduleparam.h> | |
1da177e4 LT |
30 | #include <linux/types.h> |
31 | #include <linux/timer.h> | |
25dc46e3 | 32 | #include <linux/miscdevice.h> /* for MODULE_ALIAS_MISCDEV */ |
1da177e4 | 33 | #include <linux/watchdog.h> |
1da177e4 | 34 | #include <linux/init.h> |
d052d1be | 35 | #include <linux/platform_device.h> |
1da177e4 | 36 | #include <linux/interrupt.h> |
f8ce2547 | 37 | #include <linux/clk.h> |
41dc8b72 AC |
38 | #include <linux/uaccess.h> |
39 | #include <linux/io.h> | |
e02f838e | 40 | #include <linux/cpufreq.h> |
5a0e3ad6 | 41 | #include <linux/slab.h> |
25dc46e3 | 42 | #include <linux/err.h> |
1da177e4 | 43 | |
a09e64fb | 44 | #include <mach/map.h> |
1da177e4 | 45 | |
b430708a BD |
46 | #undef S3C_VA_WATCHDOG |
47 | #define S3C_VA_WATCHDOG (0) | |
1da177e4 | 48 | |
180ee700 | 49 | #include <plat/regs-watchdog.h> |
1da177e4 | 50 | |
1da177e4 LT |
51 | #define CONFIG_S3C2410_WATCHDOG_ATBOOT (0) |
52 | #define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME (15) | |
53 | ||
86a1e189 | 54 | static bool nowayout = WATCHDOG_NOWAYOUT; |
1da177e4 LT |
55 | static int tmr_margin = CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME; |
56 | static int tmr_atboot = CONFIG_S3C2410_WATCHDOG_ATBOOT; | |
41dc8b72 AC |
57 | static int soft_noboot; |
58 | static int debug; | |
1da177e4 LT |
59 | |
60 | module_param(tmr_margin, int, 0); | |
61 | module_param(tmr_atboot, int, 0); | |
86a1e189 | 62 | module_param(nowayout, bool, 0); |
1da177e4 LT |
63 | module_param(soft_noboot, int, 0); |
64 | module_param(debug, int, 0); | |
65 | ||
76550d32 | 66 | MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. (default=" |
41dc8b72 AC |
67 | __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME) ")"); |
68 | MODULE_PARM_DESC(tmr_atboot, | |
69 | "Watchdog is started at boot time if set to 1, default=" | |
70 | __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_ATBOOT)); | |
71 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" | |
72 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
a77dba7e | 73 | MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, " |
76550d32 RD |
74 | "0 to reboot (default 0)"); |
75 | MODULE_PARM_DESC(debug, "Watchdog debug, set to >1 for debug (default 0)"); | |
1da177e4 | 76 | |
e8ef92b8 | 77 | static struct device *wdt_dev; /* platform device attached to */ |
1da177e4 LT |
78 | static struct resource *wdt_mem; |
79 | static struct resource *wdt_irq; | |
80 | static struct clk *wdt_clock; | |
81 | static void __iomem *wdt_base; | |
82 | static unsigned int wdt_count; | |
41dc8b72 | 83 | static DEFINE_SPINLOCK(wdt_lock); |
1da177e4 LT |
84 | |
85 | /* watchdog control routines */ | |
86 | ||
27c766aa JP |
87 | #define DBG(fmt, ...) \ |
88 | do { \ | |
89 | if (debug) \ | |
90 | pr_info(fmt, ##__VA_ARGS__); \ | |
91 | } while (0) | |
1da177e4 LT |
92 | |
93 | /* functions */ | |
94 | ||
25dc46e3 | 95 | static int s3c2410wdt_keepalive(struct watchdog_device *wdd) |
1da177e4 | 96 | { |
41dc8b72 | 97 | spin_lock(&wdt_lock); |
1da177e4 | 98 | writel(wdt_count, wdt_base + S3C2410_WTCNT); |
41dc8b72 | 99 | spin_unlock(&wdt_lock); |
25dc46e3 WS |
100 | |
101 | return 0; | |
1da177e4 LT |
102 | } |
103 | ||
41dc8b72 AC |
104 | static void __s3c2410wdt_stop(void) |
105 | { | |
106 | unsigned long wtcon; | |
107 | ||
108 | wtcon = readl(wdt_base + S3C2410_WTCON); | |
109 | wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN); | |
110 | writel(wtcon, wdt_base + S3C2410_WTCON); | |
111 | } | |
112 | ||
25dc46e3 | 113 | static int s3c2410wdt_stop(struct watchdog_device *wdd) |
41dc8b72 AC |
114 | { |
115 | spin_lock(&wdt_lock); | |
116 | __s3c2410wdt_stop(); | |
117 | spin_unlock(&wdt_lock); | |
25dc46e3 WS |
118 | |
119 | return 0; | |
1da177e4 LT |
120 | } |
121 | ||
25dc46e3 | 122 | static int s3c2410wdt_start(struct watchdog_device *wdd) |
1da177e4 LT |
123 | { |
124 | unsigned long wtcon; | |
125 | ||
41dc8b72 AC |
126 | spin_lock(&wdt_lock); |
127 | ||
128 | __s3c2410wdt_stop(); | |
1da177e4 LT |
129 | |
130 | wtcon = readl(wdt_base + S3C2410_WTCON); | |
131 | wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128; | |
132 | ||
133 | if (soft_noboot) { | |
134 | wtcon |= S3C2410_WTCON_INTEN; | |
135 | wtcon &= ~S3C2410_WTCON_RSTEN; | |
136 | } else { | |
137 | wtcon &= ~S3C2410_WTCON_INTEN; | |
138 | wtcon |= S3C2410_WTCON_RSTEN; | |
139 | } | |
140 | ||
141 | DBG("%s: wdt_count=0x%08x, wtcon=%08lx\n", | |
fa9363c5 | 142 | __func__, wdt_count, wtcon); |
1da177e4 LT |
143 | |
144 | writel(wdt_count, wdt_base + S3C2410_WTDAT); | |
145 | writel(wdt_count, wdt_base + S3C2410_WTCNT); | |
146 | writel(wtcon, wdt_base + S3C2410_WTCON); | |
41dc8b72 | 147 | spin_unlock(&wdt_lock); |
25dc46e3 WS |
148 | |
149 | return 0; | |
1da177e4 LT |
150 | } |
151 | ||
e02f838e BD |
152 | static inline int s3c2410wdt_is_running(void) |
153 | { | |
154 | return readl(wdt_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE; | |
155 | } | |
156 | ||
25dc46e3 | 157 | static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd, unsigned timeout) |
1da177e4 | 158 | { |
e02f838e | 159 | unsigned long freq = clk_get_rate(wdt_clock); |
1da177e4 LT |
160 | unsigned int count; |
161 | unsigned int divisor = 1; | |
162 | unsigned long wtcon; | |
163 | ||
164 | if (timeout < 1) | |
165 | return -EINVAL; | |
166 | ||
167 | freq /= 128; | |
168 | count = timeout * freq; | |
169 | ||
e02f838e | 170 | DBG("%s: count=%d, timeout=%d, freq=%lu\n", |
fa9363c5 | 171 | __func__, count, timeout, freq); |
1da177e4 LT |
172 | |
173 | /* if the count is bigger than the watchdog register, | |
174 | then work out what we need to do (and if) we can | |
175 | actually make this value | |
176 | */ | |
177 | ||
178 | if (count >= 0x10000) { | |
179 | for (divisor = 1; divisor <= 0x100; divisor++) { | |
180 | if ((count / divisor) < 0x10000) | |
181 | break; | |
182 | } | |
183 | ||
184 | if ((count / divisor) >= 0x10000) { | |
e8ef92b8 | 185 | dev_err(wdt_dev, "timeout %d too big\n", timeout); |
1da177e4 LT |
186 | return -EINVAL; |
187 | } | |
188 | } | |
189 | ||
1da177e4 | 190 | DBG("%s: timeout=%d, divisor=%d, count=%d (%08x)\n", |
fa9363c5 | 191 | __func__, timeout, divisor, count, count/divisor); |
1da177e4 LT |
192 | |
193 | count /= divisor; | |
194 | wdt_count = count; | |
195 | ||
196 | /* update the pre-scaler */ | |
197 | wtcon = readl(wdt_base + S3C2410_WTCON); | |
198 | wtcon &= ~S3C2410_WTCON_PRESCALE_MASK; | |
199 | wtcon |= S3C2410_WTCON_PRESCALE(divisor-1); | |
200 | ||
201 | writel(count, wdt_base + S3C2410_WTDAT); | |
202 | writel(wtcon, wdt_base + S3C2410_WTCON); | |
203 | ||
0197c1c4 WVS |
204 | wdd->timeout = timeout; |
205 | ||
1da177e4 LT |
206 | return 0; |
207 | } | |
208 | ||
a77dba7e | 209 | #define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE) |
1da177e4 | 210 | |
41dc8b72 | 211 | static const struct watchdog_info s3c2410_wdt_ident = { |
1da177e4 LT |
212 | .options = OPTIONS, |
213 | .firmware_version = 0, | |
214 | .identity = "S3C2410 Watchdog", | |
215 | }; | |
216 | ||
25dc46e3 WS |
217 | static struct watchdog_ops s3c2410wdt_ops = { |
218 | .owner = THIS_MODULE, | |
219 | .start = s3c2410wdt_start, | |
220 | .stop = s3c2410wdt_stop, | |
221 | .ping = s3c2410wdt_keepalive, | |
222 | .set_timeout = s3c2410wdt_set_heartbeat, | |
1da177e4 LT |
223 | }; |
224 | ||
25dc46e3 WS |
225 | static struct watchdog_device s3c2410_wdd = { |
226 | .info = &s3c2410_wdt_ident, | |
227 | .ops = &s3c2410wdt_ops, | |
1da177e4 LT |
228 | }; |
229 | ||
1da177e4 LT |
230 | /* interrupt handler code */ |
231 | ||
7d12e780 | 232 | static irqreturn_t s3c2410wdt_irq(int irqno, void *param) |
1da177e4 | 233 | { |
e8ef92b8 | 234 | dev_info(wdt_dev, "watchdog timer expired (irq)\n"); |
1da177e4 | 235 | |
25dc46e3 | 236 | s3c2410wdt_keepalive(&s3c2410_wdd); |
1da177e4 LT |
237 | return IRQ_HANDLED; |
238 | } | |
e02f838e BD |
239 | |
240 | ||
241 | #ifdef CONFIG_CPU_FREQ | |
242 | ||
243 | static int s3c2410wdt_cpufreq_transition(struct notifier_block *nb, | |
244 | unsigned long val, void *data) | |
245 | { | |
246 | int ret; | |
247 | ||
248 | if (!s3c2410wdt_is_running()) | |
249 | goto done; | |
250 | ||
251 | if (val == CPUFREQ_PRECHANGE) { | |
252 | /* To ensure that over the change we don't cause the | |
253 | * watchdog to trigger, we perform an keep-alive if | |
254 | * the watchdog is running. | |
255 | */ | |
256 | ||
25dc46e3 | 257 | s3c2410wdt_keepalive(&s3c2410_wdd); |
e02f838e | 258 | } else if (val == CPUFREQ_POSTCHANGE) { |
25dc46e3 | 259 | s3c2410wdt_stop(&s3c2410_wdd); |
e02f838e | 260 | |
25dc46e3 | 261 | ret = s3c2410wdt_set_heartbeat(&s3c2410_wdd, s3c2410_wdd.timeout); |
e02f838e BD |
262 | |
263 | if (ret >= 0) | |
25dc46e3 | 264 | s3c2410wdt_start(&s3c2410_wdd); |
e02f838e BD |
265 | else |
266 | goto err; | |
267 | } | |
268 | ||
269 | done: | |
270 | return 0; | |
271 | ||
272 | err: | |
25dc46e3 WS |
273 | dev_err(wdt_dev, "cannot set new value for timeout %d\n", |
274 | s3c2410_wdd.timeout); | |
e02f838e BD |
275 | return ret; |
276 | } | |
277 | ||
278 | static struct notifier_block s3c2410wdt_cpufreq_transition_nb = { | |
279 | .notifier_call = s3c2410wdt_cpufreq_transition, | |
280 | }; | |
281 | ||
282 | static inline int s3c2410wdt_cpufreq_register(void) | |
283 | { | |
284 | return cpufreq_register_notifier(&s3c2410wdt_cpufreq_transition_nb, | |
285 | CPUFREQ_TRANSITION_NOTIFIER); | |
286 | } | |
287 | ||
288 | static inline void s3c2410wdt_cpufreq_deregister(void) | |
289 | { | |
290 | cpufreq_unregister_notifier(&s3c2410wdt_cpufreq_transition_nb, | |
291 | CPUFREQ_TRANSITION_NOTIFIER); | |
292 | } | |
293 | ||
294 | #else | |
295 | static inline int s3c2410wdt_cpufreq_register(void) | |
296 | { | |
297 | return 0; | |
298 | } | |
299 | ||
300 | static inline void s3c2410wdt_cpufreq_deregister(void) | |
301 | { | |
302 | } | |
303 | #endif | |
304 | ||
a77dba7e | 305 | static int __devinit s3c2410wdt_probe(struct platform_device *pdev) |
1da177e4 | 306 | { |
e8ef92b8 | 307 | struct device *dev; |
46b814d6 | 308 | unsigned int wtcon; |
1da177e4 LT |
309 | int started = 0; |
310 | int ret; | |
311 | int size; | |
312 | ||
fa9363c5 | 313 | DBG("%s: probe=%p\n", __func__, pdev); |
1da177e4 | 314 | |
e8ef92b8 BD |
315 | dev = &pdev->dev; |
316 | wdt_dev = &pdev->dev; | |
317 | ||
f72401e9 JL |
318 | wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
319 | if (wdt_mem == NULL) { | |
e8ef92b8 | 320 | dev_err(dev, "no memory resource specified\n"); |
1da177e4 LT |
321 | return -ENOENT; |
322 | } | |
323 | ||
78d3e00b MH |
324 | wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
325 | if (wdt_irq == NULL) { | |
326 | dev_err(dev, "no irq resource specified\n"); | |
327 | ret = -ENOENT; | |
328 | goto err; | |
329 | } | |
330 | ||
331 | /* get the memory region for the watchdog timer */ | |
332 | ||
f72401e9 JL |
333 | size = resource_size(wdt_mem); |
334 | if (!request_mem_region(wdt_mem->start, size, pdev->name)) { | |
e8ef92b8 | 335 | dev_err(dev, "failed to get memory region\n"); |
78d3e00b MH |
336 | ret = -EBUSY; |
337 | goto err; | |
1da177e4 LT |
338 | } |
339 | ||
f72401e9 | 340 | wdt_base = ioremap(wdt_mem->start, size); |
b4253f8f | 341 | if (wdt_base == NULL) { |
e8ef92b8 | 342 | dev_err(dev, "failed to ioremap() region\n"); |
0b6dd8a6 BD |
343 | ret = -EINVAL; |
344 | goto err_req; | |
1da177e4 LT |
345 | } |
346 | ||
347 | DBG("probe: mapped wdt_base=%p\n", wdt_base); | |
348 | ||
3ae5eaec | 349 | wdt_clock = clk_get(&pdev->dev, "watchdog"); |
9cd44619 | 350 | if (IS_ERR(wdt_clock)) { |
e8ef92b8 | 351 | dev_err(dev, "failed to find watchdog clock source\n"); |
9cd44619 | 352 | ret = PTR_ERR(wdt_clock); |
78d3e00b | 353 | goto err_map; |
1da177e4 LT |
354 | } |
355 | ||
1da177e4 LT |
356 | clk_enable(wdt_clock); |
357 | ||
78d3e00b MH |
358 | ret = s3c2410wdt_cpufreq_register(); |
359 | if (ret < 0) { | |
27c766aa | 360 | pr_err("failed to register cpufreq\n"); |
e02f838e BD |
361 | goto err_clk; |
362 | } | |
363 | ||
1da177e4 LT |
364 | /* see if we can actually set the requested timer margin, and if |
365 | * not, try the default value */ | |
366 | ||
25dc46e3 WS |
367 | if (s3c2410wdt_set_heartbeat(&s3c2410_wdd, tmr_margin)) { |
368 | started = s3c2410wdt_set_heartbeat(&s3c2410_wdd, | |
41dc8b72 | 369 | CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME); |
1da177e4 | 370 | |
41dc8b72 AC |
371 | if (started == 0) |
372 | dev_info(dev, | |
373 | "tmr_margin value out of range, default %d used\n", | |
1da177e4 | 374 | CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME); |
41dc8b72 | 375 | else |
a77dba7e WVS |
376 | dev_info(dev, "default timer value is out of range, " |
377 | "cannot start\n"); | |
1da177e4 LT |
378 | } |
379 | ||
78d3e00b MH |
380 | ret = request_irq(wdt_irq->start, s3c2410wdt_irq, 0, pdev->name, pdev); |
381 | if (ret != 0) { | |
382 | dev_err(dev, "failed to install irq (%d)\n", ret); | |
383 | goto err_cpufreq; | |
384 | } | |
385 | ||
ff0b3cd4 WVS |
386 | watchdog_set_nowayout(&s3c2410_wdd, nowayout); |
387 | ||
25dc46e3 | 388 | ret = watchdog_register_device(&s3c2410_wdd); |
1da177e4 | 389 | if (ret) { |
25dc46e3 | 390 | dev_err(dev, "cannot register watchdog (%d)\n", ret); |
78d3e00b | 391 | goto err_irq; |
1da177e4 LT |
392 | } |
393 | ||
394 | if (tmr_atboot && started == 0) { | |
e8ef92b8 | 395 | dev_info(dev, "starting watchdog timer\n"); |
25dc46e3 | 396 | s3c2410wdt_start(&s3c2410_wdd); |
655516c8 BD |
397 | } else if (!tmr_atboot) { |
398 | /* if we're not enabling the watchdog, then ensure it is | |
399 | * disabled if it has been left running from the bootloader | |
400 | * or other source */ | |
401 | ||
25dc46e3 | 402 | s3c2410wdt_stop(&s3c2410_wdd); |
1da177e4 LT |
403 | } |
404 | ||
46b814d6 BD |
405 | /* print out a statement of readiness */ |
406 | ||
407 | wtcon = readl(wdt_base + S3C2410_WTCON); | |
408 | ||
e8ef92b8 | 409 | dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n", |
46b814d6 | 410 | (wtcon & S3C2410_WTCON_ENABLE) ? "" : "in", |
20403e84 DA |
411 | (wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis", |
412 | (wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis"); | |
41dc8b72 | 413 | |
1da177e4 | 414 | return 0; |
0b6dd8a6 | 415 | |
78d3e00b MH |
416 | err_irq: |
417 | free_irq(wdt_irq->start, pdev); | |
418 | ||
e02f838e BD |
419 | err_cpufreq: |
420 | s3c2410wdt_cpufreq_deregister(); | |
421 | ||
0b6dd8a6 BD |
422 | err_clk: |
423 | clk_disable(wdt_clock); | |
424 | clk_put(wdt_clock); | |
78d3e00b | 425 | wdt_clock = NULL; |
0b6dd8a6 BD |
426 | |
427 | err_map: | |
428 | iounmap(wdt_base); | |
429 | ||
430 | err_req: | |
f72401e9 | 431 | release_mem_region(wdt_mem->start, size); |
0b6dd8a6 | 432 | |
78d3e00b MH |
433 | err: |
434 | wdt_irq = NULL; | |
435 | wdt_mem = NULL; | |
0b6dd8a6 | 436 | return ret; |
1da177e4 LT |
437 | } |
438 | ||
a77dba7e | 439 | static int __devexit s3c2410wdt_remove(struct platform_device *dev) |
1da177e4 | 440 | { |
25dc46e3 | 441 | watchdog_unregister_device(&s3c2410_wdd); |
1da177e4 | 442 | |
78d3e00b MH |
443 | free_irq(wdt_irq->start, dev); |
444 | ||
9a372563 | 445 | s3c2410wdt_cpufreq_deregister(); |
1da177e4 | 446 | |
0b6dd8a6 BD |
447 | clk_disable(wdt_clock); |
448 | clk_put(wdt_clock); | |
449 | wdt_clock = NULL; | |
1da177e4 | 450 | |
e34477e9 | 451 | iounmap(wdt_base); |
9a372563 | 452 | |
f72401e9 | 453 | release_mem_region(wdt_mem->start, resource_size(wdt_mem)); |
78d3e00b | 454 | wdt_irq = NULL; |
9a372563 | 455 | wdt_mem = NULL; |
1da177e4 LT |
456 | return 0; |
457 | } | |
458 | ||
3ae5eaec | 459 | static void s3c2410wdt_shutdown(struct platform_device *dev) |
94f1e9f3 | 460 | { |
25dc46e3 | 461 | s3c2410wdt_stop(&s3c2410_wdd); |
94f1e9f3 BD |
462 | } |
463 | ||
af4bb822 BD |
464 | #ifdef CONFIG_PM |
465 | ||
466 | static unsigned long wtcon_save; | |
467 | static unsigned long wtdat_save; | |
468 | ||
3ae5eaec | 469 | static int s3c2410wdt_suspend(struct platform_device *dev, pm_message_t state) |
af4bb822 | 470 | { |
9480e307 RK |
471 | /* Save watchdog state, and turn it off. */ |
472 | wtcon_save = readl(wdt_base + S3C2410_WTCON); | |
473 | wtdat_save = readl(wdt_base + S3C2410_WTDAT); | |
af4bb822 | 474 | |
9480e307 | 475 | /* Note that WTCNT doesn't need to be saved. */ |
25dc46e3 | 476 | s3c2410wdt_stop(&s3c2410_wdd); |
af4bb822 BD |
477 | |
478 | return 0; | |
479 | } | |
480 | ||
3ae5eaec | 481 | static int s3c2410wdt_resume(struct platform_device *dev) |
af4bb822 | 482 | { |
9480e307 | 483 | /* Restore watchdog state. */ |
af4bb822 | 484 | |
9480e307 RK |
485 | writel(wtdat_save, wdt_base + S3C2410_WTDAT); |
486 | writel(wtdat_save, wdt_base + S3C2410_WTCNT); /* Reset count */ | |
487 | writel(wtcon_save, wdt_base + S3C2410_WTCON); | |
af4bb822 | 488 | |
27c766aa JP |
489 | pr_info("watchdog %sabled\n", |
490 | (wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis"); | |
af4bb822 BD |
491 | |
492 | return 0; | |
493 | } | |
494 | ||
495 | #else | |
496 | #define s3c2410wdt_suspend NULL | |
497 | #define s3c2410wdt_resume NULL | |
498 | #endif /* CONFIG_PM */ | |
499 | ||
9487a9cc TA |
500 | #ifdef CONFIG_OF |
501 | static const struct of_device_id s3c2410_wdt_match[] = { | |
502 | { .compatible = "samsung,s3c2410-wdt" }, | |
503 | {}, | |
504 | }; | |
505 | MODULE_DEVICE_TABLE(of, s3c2410_wdt_match); | |
506 | #else | |
507 | #define s3c2410_wdt_match NULL | |
508 | #endif | |
af4bb822 | 509 | |
3ae5eaec | 510 | static struct platform_driver s3c2410wdt_driver = { |
1da177e4 | 511 | .probe = s3c2410wdt_probe, |
a77dba7e | 512 | .remove = __devexit_p(s3c2410wdt_remove), |
94f1e9f3 | 513 | .shutdown = s3c2410wdt_shutdown, |
af4bb822 BD |
514 | .suspend = s3c2410wdt_suspend, |
515 | .resume = s3c2410wdt_resume, | |
3ae5eaec RK |
516 | .driver = { |
517 | .owner = THIS_MODULE, | |
518 | .name = "s3c2410-wdt", | |
9487a9cc | 519 | .of_match_table = s3c2410_wdt_match, |
3ae5eaec | 520 | }, |
1da177e4 LT |
521 | }; |
522 | ||
523 | ||
1da177e4 LT |
524 | static int __init watchdog_init(void) |
525 | { | |
ccd4144d | 526 | pr_info("S3C2410 Watchdog Timer, (c) 2004 Simtec Electronics\n"); |
27c766aa | 527 | |
3ae5eaec | 528 | return platform_driver_register(&s3c2410wdt_driver); |
1da177e4 LT |
529 | } |
530 | ||
531 | static void __exit watchdog_exit(void) | |
532 | { | |
3ae5eaec | 533 | platform_driver_unregister(&s3c2410wdt_driver); |
1da177e4 LT |
534 | } |
535 | ||
536 | module_init(watchdog_init); | |
537 | module_exit(watchdog_exit); | |
538 | ||
af4bb822 BD |
539 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, " |
540 | "Dimitry Andric <dimitry.andric@tomtom.com>"); | |
1da177e4 LT |
541 | MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver"); |
542 | MODULE_LICENSE("GPL"); | |
543 | MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); | |
f37d193c | 544 | MODULE_ALIAS("platform:s3c2410-wdt"); |