Commit | Line | Data |
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1da177e4 LT |
1 | /* linux/drivers/char/watchdog/s3c2410_wdt.c |
2 | * | |
3 | * Copyright (c) 2004 Simtec Electronics | |
4 | * Ben Dooks <ben@simtec.co.uk> | |
5 | * | |
6 | * S3C2410 Watchdog Timer Support | |
7 | * | |
8 | * Based on, softdog.c by Alan Cox, | |
29fa0586 | 9 | * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk> |
1da177e4 LT |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
1da177e4 LT |
24 | */ |
25 | ||
27c766aa JP |
26 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
27 | ||
1da177e4 LT |
28 | #include <linux/module.h> |
29 | #include <linux/moduleparam.h> | |
1da177e4 LT |
30 | #include <linux/types.h> |
31 | #include <linux/timer.h> | |
1da177e4 | 32 | #include <linux/watchdog.h> |
d052d1be | 33 | #include <linux/platform_device.h> |
1da177e4 | 34 | #include <linux/interrupt.h> |
f8ce2547 | 35 | #include <linux/clk.h> |
41dc8b72 AC |
36 | #include <linux/uaccess.h> |
37 | #include <linux/io.h> | |
e02f838e | 38 | #include <linux/cpufreq.h> |
5a0e3ad6 | 39 | #include <linux/slab.h> |
25dc46e3 | 40 | #include <linux/err.h> |
3016a552 | 41 | #include <linux/of.h> |
4f1f653a LKA |
42 | #include <linux/mfd/syscon.h> |
43 | #include <linux/regmap.h> | |
f286e133 | 44 | #include <linux/delay.h> |
1da177e4 | 45 | |
a8f5401a TF |
46 | #define S3C2410_WTCON 0x00 |
47 | #define S3C2410_WTDAT 0x04 | |
48 | #define S3C2410_WTCNT 0x08 | |
1da177e4 | 49 | |
882dec1f JMC |
50 | #define S3C2410_WTCNT_MAXCNT 0xffff |
51 | ||
a8f5401a TF |
52 | #define S3C2410_WTCON_RSTEN (1 << 0) |
53 | #define S3C2410_WTCON_INTEN (1 << 2) | |
54 | #define S3C2410_WTCON_ENABLE (1 << 5) | |
1da177e4 | 55 | |
a8f5401a TF |
56 | #define S3C2410_WTCON_DIV16 (0 << 3) |
57 | #define S3C2410_WTCON_DIV32 (1 << 3) | |
58 | #define S3C2410_WTCON_DIV64 (2 << 3) | |
59 | #define S3C2410_WTCON_DIV128 (3 << 3) | |
60 | ||
882dec1f JMC |
61 | #define S3C2410_WTCON_MAXDIV 0x80 |
62 | ||
a8f5401a TF |
63 | #define S3C2410_WTCON_PRESCALE(x) ((x) << 8) |
64 | #define S3C2410_WTCON_PRESCALE_MASK (0xff << 8) | |
882dec1f | 65 | #define S3C2410_WTCON_PRESCALE_MAX 0xff |
1da177e4 | 66 | |
1da177e4 LT |
67 | #define CONFIG_S3C2410_WATCHDOG_ATBOOT (0) |
68 | #define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME (15) | |
69 | ||
cffc9a60 | 70 | #define EXYNOS5_RST_STAT_REG_OFFSET 0x0404 |
4f1f653a LKA |
71 | #define EXYNOS5_WDT_DISABLE_REG_OFFSET 0x0408 |
72 | #define EXYNOS5_WDT_MASK_RESET_REG_OFFSET 0x040c | |
73 | #define QUIRK_HAS_PMU_CONFIG (1 << 0) | |
cffc9a60 DA |
74 | #define QUIRK_HAS_RST_STAT (1 << 1) |
75 | ||
76 | /* These quirks require that we have a PMU register map */ | |
77 | #define QUIRKS_HAVE_PMUREG (QUIRK_HAS_PMU_CONFIG | \ | |
78 | QUIRK_HAS_RST_STAT) | |
4f1f653a | 79 | |
86a1e189 | 80 | static bool nowayout = WATCHDOG_NOWAYOUT; |
c1fd5f64 | 81 | static int tmr_margin; |
1da177e4 | 82 | static int tmr_atboot = CONFIG_S3C2410_WATCHDOG_ATBOOT; |
41dc8b72 AC |
83 | static int soft_noboot; |
84 | static int debug; | |
1da177e4 LT |
85 | |
86 | module_param(tmr_margin, int, 0); | |
87 | module_param(tmr_atboot, int, 0); | |
86a1e189 | 88 | module_param(nowayout, bool, 0); |
1da177e4 LT |
89 | module_param(soft_noboot, int, 0); |
90 | module_param(debug, int, 0); | |
91 | ||
76550d32 | 92 | MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. (default=" |
41dc8b72 AC |
93 | __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME) ")"); |
94 | MODULE_PARM_DESC(tmr_atboot, | |
95 | "Watchdog is started at boot time if set to 1, default=" | |
96 | __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_ATBOOT)); | |
97 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" | |
98 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
a77dba7e | 99 | MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, " |
76550d32 RD |
100 | "0 to reboot (default 0)"); |
101 | MODULE_PARM_DESC(debug, "Watchdog debug, set to >1 for debug (default 0)"); | |
1da177e4 | 102 | |
4f1f653a LKA |
103 | /** |
104 | * struct s3c2410_wdt_variant - Per-variant config data | |
105 | * | |
106 | * @disable_reg: Offset in pmureg for the register that disables the watchdog | |
107 | * timer reset functionality. | |
108 | * @mask_reset_reg: Offset in pmureg for the register that masks the watchdog | |
109 | * timer reset functionality. | |
110 | * @mask_bit: Bit number for the watchdog timer in the disable register and the | |
111 | * mask reset register. | |
cffc9a60 DA |
112 | * @rst_stat_reg: Offset in pmureg for the register that has the reset status. |
113 | * @rst_stat_bit: Bit number in the rst_stat register indicating a watchdog | |
114 | * reset. | |
4f1f653a LKA |
115 | * @quirks: A bitfield of quirks. |
116 | */ | |
117 | ||
118 | struct s3c2410_wdt_variant { | |
119 | int disable_reg; | |
120 | int mask_reset_reg; | |
121 | int mask_bit; | |
cffc9a60 DA |
122 | int rst_stat_reg; |
123 | int rst_stat_bit; | |
4f1f653a LKA |
124 | u32 quirks; |
125 | }; | |
126 | ||
af4ea631 LKA |
127 | struct s3c2410_wdt { |
128 | struct device *dev; | |
129 | struct clk *clock; | |
130 | void __iomem *reg_base; | |
131 | unsigned int count; | |
132 | spinlock_t lock; | |
133 | unsigned long wtcon_save; | |
134 | unsigned long wtdat_save; | |
135 | struct watchdog_device wdt_device; | |
136 | struct notifier_block freq_transition; | |
4f1f653a LKA |
137 | struct s3c2410_wdt_variant *drv_data; |
138 | struct regmap *pmureg; | |
139 | }; | |
140 | ||
141 | static const struct s3c2410_wdt_variant drv_data_s3c2410 = { | |
142 | .quirks = 0 | |
143 | }; | |
144 | ||
145 | #ifdef CONFIG_OF | |
146 | static const struct s3c2410_wdt_variant drv_data_exynos5250 = { | |
147 | .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET, | |
148 | .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET, | |
149 | .mask_bit = 20, | |
cffc9a60 DA |
150 | .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, |
151 | .rst_stat_bit = 20, | |
152 | .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT, | |
4f1f653a LKA |
153 | }; |
154 | ||
155 | static const struct s3c2410_wdt_variant drv_data_exynos5420 = { | |
156 | .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET, | |
157 | .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET, | |
158 | .mask_bit = 0, | |
cffc9a60 DA |
159 | .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, |
160 | .rst_stat_bit = 9, | |
161 | .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT, | |
4f1f653a LKA |
162 | }; |
163 | ||
2b9366b6 NKC |
164 | static const struct s3c2410_wdt_variant drv_data_exynos7 = { |
165 | .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET, | |
166 | .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET, | |
5476b2b7 | 167 | .mask_bit = 23, |
2b9366b6 NKC |
168 | .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, |
169 | .rst_stat_bit = 23, /* A57 WDTRESET */ | |
170 | .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT, | |
171 | }; | |
172 | ||
4f1f653a LKA |
173 | static const struct of_device_id s3c2410_wdt_match[] = { |
174 | { .compatible = "samsung,s3c2410-wdt", | |
175 | .data = &drv_data_s3c2410 }, | |
176 | { .compatible = "samsung,exynos5250-wdt", | |
177 | .data = &drv_data_exynos5250 }, | |
178 | { .compatible = "samsung,exynos5420-wdt", | |
179 | .data = &drv_data_exynos5420 }, | |
2b9366b6 NKC |
180 | { .compatible = "samsung,exynos7-wdt", |
181 | .data = &drv_data_exynos7 }, | |
4f1f653a | 182 | {}, |
af4ea631 | 183 | }; |
4f1f653a LKA |
184 | MODULE_DEVICE_TABLE(of, s3c2410_wdt_match); |
185 | #endif | |
186 | ||
187 | static const struct platform_device_id s3c2410_wdt_ids[] = { | |
188 | { | |
189 | .name = "s3c2410-wdt", | |
190 | .driver_data = (unsigned long)&drv_data_s3c2410, | |
191 | }, | |
192 | {} | |
193 | }; | |
194 | MODULE_DEVICE_TABLE(platform, s3c2410_wdt_ids); | |
1da177e4 LT |
195 | |
196 | /* watchdog control routines */ | |
197 | ||
27c766aa JP |
198 | #define DBG(fmt, ...) \ |
199 | do { \ | |
200 | if (debug) \ | |
201 | pr_info(fmt, ##__VA_ARGS__); \ | |
202 | } while (0) | |
1da177e4 LT |
203 | |
204 | /* functions */ | |
205 | ||
882dec1f JMC |
206 | static inline unsigned int s3c2410wdt_max_timeout(struct clk *clock) |
207 | { | |
208 | unsigned long freq = clk_get_rate(clock); | |
209 | ||
210 | return S3C2410_WTCNT_MAXCNT / (freq / (S3C2410_WTCON_PRESCALE_MAX + 1) | |
211 | / S3C2410_WTCON_MAXDIV); | |
212 | } | |
213 | ||
af4ea631 LKA |
214 | static inline struct s3c2410_wdt *freq_to_wdt(struct notifier_block *nb) |
215 | { | |
216 | return container_of(nb, struct s3c2410_wdt, freq_transition); | |
217 | } | |
218 | ||
4f1f653a LKA |
219 | static int s3c2410wdt_mask_and_disable_reset(struct s3c2410_wdt *wdt, bool mask) |
220 | { | |
221 | int ret; | |
222 | u32 mask_val = 1 << wdt->drv_data->mask_bit; | |
223 | u32 val = 0; | |
224 | ||
225 | /* No need to do anything if no PMU CONFIG needed */ | |
226 | if (!(wdt->drv_data->quirks & QUIRK_HAS_PMU_CONFIG)) | |
227 | return 0; | |
228 | ||
229 | if (mask) | |
230 | val = mask_val; | |
231 | ||
232 | ret = regmap_update_bits(wdt->pmureg, | |
233 | wdt->drv_data->disable_reg, | |
234 | mask_val, val); | |
235 | if (ret < 0) | |
236 | goto error; | |
237 | ||
238 | ret = regmap_update_bits(wdt->pmureg, | |
239 | wdt->drv_data->mask_reset_reg, | |
240 | mask_val, val); | |
241 | error: | |
242 | if (ret < 0) | |
243 | dev_err(wdt->dev, "failed to update reg(%d)\n", ret); | |
244 | ||
245 | return ret; | |
246 | } | |
247 | ||
25dc46e3 | 248 | static int s3c2410wdt_keepalive(struct watchdog_device *wdd) |
1da177e4 | 249 | { |
af4ea631 LKA |
250 | struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); |
251 | ||
252 | spin_lock(&wdt->lock); | |
253 | writel(wdt->count, wdt->reg_base + S3C2410_WTCNT); | |
254 | spin_unlock(&wdt->lock); | |
25dc46e3 WS |
255 | |
256 | return 0; | |
1da177e4 LT |
257 | } |
258 | ||
af4ea631 | 259 | static void __s3c2410wdt_stop(struct s3c2410_wdt *wdt) |
41dc8b72 AC |
260 | { |
261 | unsigned long wtcon; | |
262 | ||
af4ea631 | 263 | wtcon = readl(wdt->reg_base + S3C2410_WTCON); |
41dc8b72 | 264 | wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN); |
af4ea631 | 265 | writel(wtcon, wdt->reg_base + S3C2410_WTCON); |
41dc8b72 AC |
266 | } |
267 | ||
25dc46e3 | 268 | static int s3c2410wdt_stop(struct watchdog_device *wdd) |
41dc8b72 | 269 | { |
af4ea631 LKA |
270 | struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); |
271 | ||
272 | spin_lock(&wdt->lock); | |
273 | __s3c2410wdt_stop(wdt); | |
274 | spin_unlock(&wdt->lock); | |
25dc46e3 WS |
275 | |
276 | return 0; | |
1da177e4 LT |
277 | } |
278 | ||
25dc46e3 | 279 | static int s3c2410wdt_start(struct watchdog_device *wdd) |
1da177e4 LT |
280 | { |
281 | unsigned long wtcon; | |
af4ea631 | 282 | struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); |
1da177e4 | 283 | |
af4ea631 | 284 | spin_lock(&wdt->lock); |
41dc8b72 | 285 | |
af4ea631 | 286 | __s3c2410wdt_stop(wdt); |
1da177e4 | 287 | |
af4ea631 | 288 | wtcon = readl(wdt->reg_base + S3C2410_WTCON); |
1da177e4 LT |
289 | wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128; |
290 | ||
291 | if (soft_noboot) { | |
292 | wtcon |= S3C2410_WTCON_INTEN; | |
293 | wtcon &= ~S3C2410_WTCON_RSTEN; | |
294 | } else { | |
295 | wtcon &= ~S3C2410_WTCON_INTEN; | |
296 | wtcon |= S3C2410_WTCON_RSTEN; | |
297 | } | |
298 | ||
af4ea631 LKA |
299 | DBG("%s: count=0x%08x, wtcon=%08lx\n", |
300 | __func__, wdt->count, wtcon); | |
1da177e4 | 301 | |
af4ea631 LKA |
302 | writel(wdt->count, wdt->reg_base + S3C2410_WTDAT); |
303 | writel(wdt->count, wdt->reg_base + S3C2410_WTCNT); | |
304 | writel(wtcon, wdt->reg_base + S3C2410_WTCON); | |
305 | spin_unlock(&wdt->lock); | |
25dc46e3 WS |
306 | |
307 | return 0; | |
1da177e4 LT |
308 | } |
309 | ||
af4ea631 | 310 | static inline int s3c2410wdt_is_running(struct s3c2410_wdt *wdt) |
e02f838e | 311 | { |
af4ea631 | 312 | return readl(wdt->reg_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE; |
e02f838e BD |
313 | } |
314 | ||
25dc46e3 | 315 | static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd, unsigned timeout) |
1da177e4 | 316 | { |
af4ea631 LKA |
317 | struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); |
318 | unsigned long freq = clk_get_rate(wdt->clock); | |
1da177e4 LT |
319 | unsigned int count; |
320 | unsigned int divisor = 1; | |
321 | unsigned long wtcon; | |
322 | ||
323 | if (timeout < 1) | |
324 | return -EINVAL; | |
325 | ||
17862440 | 326 | freq = DIV_ROUND_UP(freq, 128); |
1da177e4 LT |
327 | count = timeout * freq; |
328 | ||
e02f838e | 329 | DBG("%s: count=%d, timeout=%d, freq=%lu\n", |
fa9363c5 | 330 | __func__, count, timeout, freq); |
1da177e4 LT |
331 | |
332 | /* if the count is bigger than the watchdog register, | |
333 | then work out what we need to do (and if) we can | |
334 | actually make this value | |
335 | */ | |
336 | ||
337 | if (count >= 0x10000) { | |
17862440 | 338 | divisor = DIV_ROUND_UP(count, 0xffff); |
1da177e4 | 339 | |
17862440 | 340 | if (divisor > 0x100) { |
af4ea631 | 341 | dev_err(wdt->dev, "timeout %d too big\n", timeout); |
1da177e4 LT |
342 | return -EINVAL; |
343 | } | |
344 | } | |
345 | ||
1da177e4 | 346 | DBG("%s: timeout=%d, divisor=%d, count=%d (%08x)\n", |
17862440 | 347 | __func__, timeout, divisor, count, DIV_ROUND_UP(count, divisor)); |
1da177e4 | 348 | |
17862440 | 349 | count = DIV_ROUND_UP(count, divisor); |
af4ea631 | 350 | wdt->count = count; |
1da177e4 LT |
351 | |
352 | /* update the pre-scaler */ | |
af4ea631 | 353 | wtcon = readl(wdt->reg_base + S3C2410_WTCON); |
1da177e4 LT |
354 | wtcon &= ~S3C2410_WTCON_PRESCALE_MASK; |
355 | wtcon |= S3C2410_WTCON_PRESCALE(divisor-1); | |
356 | ||
af4ea631 LKA |
357 | writel(count, wdt->reg_base + S3C2410_WTDAT); |
358 | writel(wtcon, wdt->reg_base + S3C2410_WTCON); | |
1da177e4 | 359 | |
5f2430f5 | 360 | wdd->timeout = (count * divisor) / freq; |
0197c1c4 | 361 | |
1da177e4 LT |
362 | return 0; |
363 | } | |
364 | ||
4d8b229d GR |
365 | static int s3c2410wdt_restart(struct watchdog_device *wdd, unsigned long action, |
366 | void *data) | |
c71f5cd2 DR |
367 | { |
368 | struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); | |
369 | void __iomem *wdt_base = wdt->reg_base; | |
370 | ||
371 | /* disable watchdog, to be safe */ | |
372 | writel(0, wdt_base + S3C2410_WTCON); | |
373 | ||
374 | /* put initial values into count and data */ | |
375 | writel(0x80, wdt_base + S3C2410_WTCNT); | |
376 | writel(0x80, wdt_base + S3C2410_WTDAT); | |
377 | ||
378 | /* set the watchdog to go and reset... */ | |
379 | writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV16 | | |
380 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x20), | |
381 | wdt_base + S3C2410_WTCON); | |
382 | ||
383 | /* wait for reset to assert... */ | |
384 | mdelay(500); | |
385 | ||
386 | return 0; | |
387 | } | |
388 | ||
a77dba7e | 389 | #define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE) |
1da177e4 | 390 | |
41dc8b72 | 391 | static const struct watchdog_info s3c2410_wdt_ident = { |
1da177e4 LT |
392 | .options = OPTIONS, |
393 | .firmware_version = 0, | |
394 | .identity = "S3C2410 Watchdog", | |
395 | }; | |
396 | ||
25dc46e3 WS |
397 | static struct watchdog_ops s3c2410wdt_ops = { |
398 | .owner = THIS_MODULE, | |
399 | .start = s3c2410wdt_start, | |
400 | .stop = s3c2410wdt_stop, | |
401 | .ping = s3c2410wdt_keepalive, | |
402 | .set_timeout = s3c2410wdt_set_heartbeat, | |
c71f5cd2 | 403 | .restart = s3c2410wdt_restart, |
1da177e4 LT |
404 | }; |
405 | ||
25dc46e3 WS |
406 | static struct watchdog_device s3c2410_wdd = { |
407 | .info = &s3c2410_wdt_ident, | |
408 | .ops = &s3c2410wdt_ops, | |
c1fd5f64 | 409 | .timeout = CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME, |
1da177e4 LT |
410 | }; |
411 | ||
1da177e4 LT |
412 | /* interrupt handler code */ |
413 | ||
7d12e780 | 414 | static irqreturn_t s3c2410wdt_irq(int irqno, void *param) |
1da177e4 | 415 | { |
af4ea631 | 416 | struct s3c2410_wdt *wdt = platform_get_drvdata(param); |
1da177e4 | 417 | |
af4ea631 LKA |
418 | dev_info(wdt->dev, "watchdog timer expired (irq)\n"); |
419 | ||
420 | s3c2410wdt_keepalive(&wdt->wdt_device); | |
1da177e4 LT |
421 | return IRQ_HANDLED; |
422 | } | |
e02f838e | 423 | |
0f1dd98d | 424 | #ifdef CONFIG_ARM_S3C24XX_CPUFREQ |
e02f838e BD |
425 | |
426 | static int s3c2410wdt_cpufreq_transition(struct notifier_block *nb, | |
427 | unsigned long val, void *data) | |
428 | { | |
429 | int ret; | |
af4ea631 | 430 | struct s3c2410_wdt *wdt = freq_to_wdt(nb); |
e02f838e | 431 | |
af4ea631 | 432 | if (!s3c2410wdt_is_running(wdt)) |
e02f838e BD |
433 | goto done; |
434 | ||
435 | if (val == CPUFREQ_PRECHANGE) { | |
436 | /* To ensure that over the change we don't cause the | |
437 | * watchdog to trigger, we perform an keep-alive if | |
438 | * the watchdog is running. | |
439 | */ | |
440 | ||
af4ea631 | 441 | s3c2410wdt_keepalive(&wdt->wdt_device); |
e02f838e | 442 | } else if (val == CPUFREQ_POSTCHANGE) { |
af4ea631 | 443 | s3c2410wdt_stop(&wdt->wdt_device); |
e02f838e | 444 | |
af4ea631 LKA |
445 | ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device, |
446 | wdt->wdt_device.timeout); | |
e02f838e BD |
447 | |
448 | if (ret >= 0) | |
af4ea631 | 449 | s3c2410wdt_start(&wdt->wdt_device); |
e02f838e BD |
450 | else |
451 | goto err; | |
452 | } | |
453 | ||
454 | done: | |
455 | return 0; | |
456 | ||
457 | err: | |
af4ea631 LKA |
458 | dev_err(wdt->dev, "cannot set new value for timeout %d\n", |
459 | wdt->wdt_device.timeout); | |
e02f838e BD |
460 | return ret; |
461 | } | |
462 | ||
af4ea631 | 463 | static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt) |
e02f838e | 464 | { |
af4ea631 LKA |
465 | wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition; |
466 | ||
467 | return cpufreq_register_notifier(&wdt->freq_transition, | |
e02f838e BD |
468 | CPUFREQ_TRANSITION_NOTIFIER); |
469 | } | |
470 | ||
af4ea631 | 471 | static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt) |
e02f838e | 472 | { |
af4ea631 LKA |
473 | wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition; |
474 | ||
475 | cpufreq_unregister_notifier(&wdt->freq_transition, | |
e02f838e BD |
476 | CPUFREQ_TRANSITION_NOTIFIER); |
477 | } | |
478 | ||
479 | #else | |
af4ea631 LKA |
480 | |
481 | static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt) | |
e02f838e BD |
482 | { |
483 | return 0; | |
484 | } | |
485 | ||
af4ea631 | 486 | static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt) |
e02f838e BD |
487 | { |
488 | } | |
489 | #endif | |
490 | ||
cffc9a60 DA |
491 | static inline unsigned int s3c2410wdt_get_bootstatus(struct s3c2410_wdt *wdt) |
492 | { | |
493 | unsigned int rst_stat; | |
494 | int ret; | |
495 | ||
496 | if (!(wdt->drv_data->quirks & QUIRK_HAS_RST_STAT)) | |
497 | return 0; | |
498 | ||
499 | ret = regmap_read(wdt->pmureg, wdt->drv_data->rst_stat_reg, &rst_stat); | |
500 | if (ret) | |
501 | dev_warn(wdt->dev, "Couldn't get RST_STAT register\n"); | |
502 | else if (rst_stat & BIT(wdt->drv_data->rst_stat_bit)) | |
503 | return WDIOF_CARDRESET; | |
504 | ||
505 | return 0; | |
506 | } | |
507 | ||
4f1f653a LKA |
508 | /* s3c2410_get_wdt_driver_data */ |
509 | static inline struct s3c2410_wdt_variant * | |
510 | get_wdt_drv_data(struct platform_device *pdev) | |
511 | { | |
512 | if (pdev->dev.of_node) { | |
513 | const struct of_device_id *match; | |
514 | match = of_match_node(s3c2410_wdt_match, pdev->dev.of_node); | |
515 | return (struct s3c2410_wdt_variant *)match->data; | |
516 | } else { | |
517 | return (struct s3c2410_wdt_variant *) | |
518 | platform_get_device_id(pdev)->driver_data; | |
519 | } | |
520 | } | |
521 | ||
2d991a16 | 522 | static int s3c2410wdt_probe(struct platform_device *pdev) |
1da177e4 | 523 | { |
e8ef92b8 | 524 | struct device *dev; |
af4ea631 LKA |
525 | struct s3c2410_wdt *wdt; |
526 | struct resource *wdt_mem; | |
527 | struct resource *wdt_irq; | |
46b814d6 | 528 | unsigned int wtcon; |
1da177e4 LT |
529 | int started = 0; |
530 | int ret; | |
1da177e4 | 531 | |
fa9363c5 | 532 | DBG("%s: probe=%p\n", __func__, pdev); |
1da177e4 | 533 | |
e8ef92b8 | 534 | dev = &pdev->dev; |
e8ef92b8 | 535 | |
af4ea631 LKA |
536 | wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL); |
537 | if (!wdt) | |
538 | return -ENOMEM; | |
539 | ||
540 | wdt->dev = &pdev->dev; | |
541 | spin_lock_init(&wdt->lock); | |
542 | wdt->wdt_device = s3c2410_wdd; | |
1da177e4 | 543 | |
4f1f653a | 544 | wdt->drv_data = get_wdt_drv_data(pdev); |
cffc9a60 | 545 | if (wdt->drv_data->quirks & QUIRKS_HAVE_PMUREG) { |
4f1f653a LKA |
546 | wdt->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node, |
547 | "samsung,syscon-phandle"); | |
548 | if (IS_ERR(wdt->pmureg)) { | |
549 | dev_err(dev, "syscon regmap lookup failed.\n"); | |
550 | return PTR_ERR(wdt->pmureg); | |
551 | } | |
552 | } | |
553 | ||
78d3e00b MH |
554 | wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
555 | if (wdt_irq == NULL) { | |
556 | dev_err(dev, "no irq resource specified\n"); | |
557 | ret = -ENOENT; | |
558 | goto err; | |
559 | } | |
560 | ||
561 | /* get the memory region for the watchdog timer */ | |
bd5cc119 | 562 | wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
af4ea631 LKA |
563 | wdt->reg_base = devm_ioremap_resource(dev, wdt_mem); |
564 | if (IS_ERR(wdt->reg_base)) { | |
565 | ret = PTR_ERR(wdt->reg_base); | |
04ecc7dc | 566 | goto err; |
1da177e4 LT |
567 | } |
568 | ||
af4ea631 | 569 | DBG("probe: mapped reg_base=%p\n", wdt->reg_base); |
1da177e4 | 570 | |
af4ea631 LKA |
571 | wdt->clock = devm_clk_get(dev, "watchdog"); |
572 | if (IS_ERR(wdt->clock)) { | |
e8ef92b8 | 573 | dev_err(dev, "failed to find watchdog clock source\n"); |
af4ea631 | 574 | ret = PTR_ERR(wdt->clock); |
04ecc7dc | 575 | goto err; |
1da177e4 LT |
576 | } |
577 | ||
01b6af91 SK |
578 | ret = clk_prepare_enable(wdt->clock); |
579 | if (ret < 0) { | |
580 | dev_err(dev, "failed to enable clock\n"); | |
581 | return ret; | |
582 | } | |
1da177e4 | 583 | |
882dec1f JMC |
584 | wdt->wdt_device.min_timeout = 1; |
585 | wdt->wdt_device.max_timeout = s3c2410wdt_max_timeout(wdt->clock); | |
586 | ||
af4ea631 | 587 | ret = s3c2410wdt_cpufreq_register(wdt); |
78d3e00b | 588 | if (ret < 0) { |
3828924a | 589 | dev_err(dev, "failed to register cpufreq\n"); |
e02f838e BD |
590 | goto err_clk; |
591 | } | |
592 | ||
af4ea631 LKA |
593 | watchdog_set_drvdata(&wdt->wdt_device, wdt); |
594 | ||
1da177e4 LT |
595 | /* see if we can actually set the requested timer margin, and if |
596 | * not, try the default value */ | |
597 | ||
af4ea631 LKA |
598 | watchdog_init_timeout(&wdt->wdt_device, tmr_margin, &pdev->dev); |
599 | ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device, | |
600 | wdt->wdt_device.timeout); | |
601 | if (ret) { | |
602 | started = s3c2410wdt_set_heartbeat(&wdt->wdt_device, | |
41dc8b72 | 603 | CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME); |
1da177e4 | 604 | |
41dc8b72 AC |
605 | if (started == 0) |
606 | dev_info(dev, | |
607 | "tmr_margin value out of range, default %d used\n", | |
1da177e4 | 608 | CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME); |
41dc8b72 | 609 | else |
a77dba7e WVS |
610 | dev_info(dev, "default timer value is out of range, " |
611 | "cannot start\n"); | |
1da177e4 LT |
612 | } |
613 | ||
04ecc7dc JH |
614 | ret = devm_request_irq(dev, wdt_irq->start, s3c2410wdt_irq, 0, |
615 | pdev->name, pdev); | |
78d3e00b MH |
616 | if (ret != 0) { |
617 | dev_err(dev, "failed to install irq (%d)\n", ret); | |
618 | goto err_cpufreq; | |
619 | } | |
620 | ||
af4ea631 | 621 | watchdog_set_nowayout(&wdt->wdt_device, nowayout); |
c71f5cd2 | 622 | watchdog_set_restart_priority(&wdt->wdt_device, 128); |
ff0b3cd4 | 623 | |
cffc9a60 | 624 | wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt); |
6551881c | 625 | wdt->wdt_device.parent = &pdev->dev; |
cffc9a60 | 626 | |
af4ea631 | 627 | ret = watchdog_register_device(&wdt->wdt_device); |
1da177e4 | 628 | if (ret) { |
25dc46e3 | 629 | dev_err(dev, "cannot register watchdog (%d)\n", ret); |
04ecc7dc | 630 | goto err_cpufreq; |
1da177e4 LT |
631 | } |
632 | ||
4f1f653a LKA |
633 | ret = s3c2410wdt_mask_and_disable_reset(wdt, false); |
634 | if (ret < 0) | |
635 | goto err_unregister; | |
636 | ||
1da177e4 | 637 | if (tmr_atboot && started == 0) { |
e8ef92b8 | 638 | dev_info(dev, "starting watchdog timer\n"); |
af4ea631 | 639 | s3c2410wdt_start(&wdt->wdt_device); |
655516c8 BD |
640 | } else if (!tmr_atboot) { |
641 | /* if we're not enabling the watchdog, then ensure it is | |
642 | * disabled if it has been left running from the bootloader | |
643 | * or other source */ | |
644 | ||
af4ea631 | 645 | s3c2410wdt_stop(&wdt->wdt_device); |
1da177e4 LT |
646 | } |
647 | ||
af4ea631 LKA |
648 | platform_set_drvdata(pdev, wdt); |
649 | ||
46b814d6 BD |
650 | /* print out a statement of readiness */ |
651 | ||
af4ea631 | 652 | wtcon = readl(wdt->reg_base + S3C2410_WTCON); |
46b814d6 | 653 | |
e8ef92b8 | 654 | dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n", |
46b814d6 | 655 | (wtcon & S3C2410_WTCON_ENABLE) ? "" : "in", |
20403e84 DA |
656 | (wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis", |
657 | (wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis"); | |
41dc8b72 | 658 | |
1da177e4 | 659 | return 0; |
0b6dd8a6 | 660 | |
4f1f653a LKA |
661 | err_unregister: |
662 | watchdog_unregister_device(&wdt->wdt_device); | |
663 | ||
e02f838e | 664 | err_cpufreq: |
af4ea631 | 665 | s3c2410wdt_cpufreq_deregister(wdt); |
e02f838e | 666 | |
0b6dd8a6 | 667 | err_clk: |
af4ea631 | 668 | clk_disable_unprepare(wdt->clock); |
0b6dd8a6 | 669 | |
78d3e00b | 670 | err: |
0b6dd8a6 | 671 | return ret; |
1da177e4 LT |
672 | } |
673 | ||
4b12b896 | 674 | static int s3c2410wdt_remove(struct platform_device *dev) |
1da177e4 | 675 | { |
4f1f653a | 676 | int ret; |
af4ea631 LKA |
677 | struct s3c2410_wdt *wdt = platform_get_drvdata(dev); |
678 | ||
4f1f653a LKA |
679 | ret = s3c2410wdt_mask_and_disable_reset(wdt, true); |
680 | if (ret < 0) | |
681 | return ret; | |
682 | ||
af4ea631 | 683 | watchdog_unregister_device(&wdt->wdt_device); |
1da177e4 | 684 | |
af4ea631 | 685 | s3c2410wdt_cpufreq_deregister(wdt); |
1da177e4 | 686 | |
af4ea631 | 687 | clk_disable_unprepare(wdt->clock); |
1da177e4 | 688 | |
1da177e4 LT |
689 | return 0; |
690 | } | |
691 | ||
3ae5eaec | 692 | static void s3c2410wdt_shutdown(struct platform_device *dev) |
94f1e9f3 | 693 | { |
af4ea631 LKA |
694 | struct s3c2410_wdt *wdt = platform_get_drvdata(dev); |
695 | ||
4f1f653a LKA |
696 | s3c2410wdt_mask_and_disable_reset(wdt, true); |
697 | ||
af4ea631 | 698 | s3c2410wdt_stop(&wdt->wdt_device); |
94f1e9f3 BD |
699 | } |
700 | ||
0183984c | 701 | #ifdef CONFIG_PM_SLEEP |
af4bb822 | 702 | |
0183984c | 703 | static int s3c2410wdt_suspend(struct device *dev) |
af4bb822 | 704 | { |
4f1f653a | 705 | int ret; |
af4ea631 LKA |
706 | struct s3c2410_wdt *wdt = dev_get_drvdata(dev); |
707 | ||
9480e307 | 708 | /* Save watchdog state, and turn it off. */ |
af4ea631 LKA |
709 | wdt->wtcon_save = readl(wdt->reg_base + S3C2410_WTCON); |
710 | wdt->wtdat_save = readl(wdt->reg_base + S3C2410_WTDAT); | |
af4bb822 | 711 | |
4f1f653a LKA |
712 | ret = s3c2410wdt_mask_and_disable_reset(wdt, true); |
713 | if (ret < 0) | |
714 | return ret; | |
715 | ||
9480e307 | 716 | /* Note that WTCNT doesn't need to be saved. */ |
af4ea631 | 717 | s3c2410wdt_stop(&wdt->wdt_device); |
af4bb822 BD |
718 | |
719 | return 0; | |
720 | } | |
721 | ||
0183984c | 722 | static int s3c2410wdt_resume(struct device *dev) |
af4bb822 | 723 | { |
4f1f653a | 724 | int ret; |
af4ea631 | 725 | struct s3c2410_wdt *wdt = dev_get_drvdata(dev); |
af4bb822 | 726 | |
af4ea631 LKA |
727 | /* Restore watchdog state. */ |
728 | writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTDAT); | |
729 | writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTCNT);/* Reset count */ | |
730 | writel(wdt->wtcon_save, wdt->reg_base + S3C2410_WTCON); | |
af4bb822 | 731 | |
4f1f653a LKA |
732 | ret = s3c2410wdt_mask_and_disable_reset(wdt, false); |
733 | if (ret < 0) | |
734 | return ret; | |
735 | ||
0183984c | 736 | dev_info(dev, "watchdog %sabled\n", |
af4ea631 | 737 | (wdt->wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis"); |
af4bb822 BD |
738 | |
739 | return 0; | |
740 | } | |
0183984c | 741 | #endif |
af4bb822 | 742 | |
0183984c JH |
743 | static SIMPLE_DEV_PM_OPS(s3c2410wdt_pm_ops, s3c2410wdt_suspend, |
744 | s3c2410wdt_resume); | |
af4bb822 | 745 | |
3ae5eaec | 746 | static struct platform_driver s3c2410wdt_driver = { |
1da177e4 | 747 | .probe = s3c2410wdt_probe, |
82268714 | 748 | .remove = s3c2410wdt_remove, |
94f1e9f3 | 749 | .shutdown = s3c2410wdt_shutdown, |
4f1f653a | 750 | .id_table = s3c2410_wdt_ids, |
3ae5eaec | 751 | .driver = { |
3ae5eaec | 752 | .name = "s3c2410-wdt", |
0183984c | 753 | .pm = &s3c2410wdt_pm_ops, |
3016a552 | 754 | .of_match_table = of_match_ptr(s3c2410_wdt_match), |
3ae5eaec | 755 | }, |
1da177e4 LT |
756 | }; |
757 | ||
6b761b29 | 758 | module_platform_driver(s3c2410wdt_driver); |
1da177e4 | 759 | |
af4bb822 BD |
760 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, " |
761 | "Dimitry Andric <dimitry.andric@tomtom.com>"); | |
1da177e4 LT |
762 | MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver"); |
763 | MODULE_LICENSE("GPL"); |