ASoC: TWL4030: Add functionalty to reset the registers
[deliverable/linux.git] / drivers / watchdog / s3c2410_wdt.c
CommitLineData
1da177e4
LT
1/* linux/drivers/char/watchdog/s3c2410_wdt.c
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 Watchdog Timer Support
7 *
8 * Based on, softdog.c by Alan Cox,
29fa0586 9 * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>
1da177e4
LT
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1da177e4
LT
24*/
25
26#include <linux/module.h>
27#include <linux/moduleparam.h>
1da177e4
LT
28#include <linux/types.h>
29#include <linux/timer.h>
30#include <linux/miscdevice.h>
31#include <linux/watchdog.h>
32#include <linux/fs.h>
1da177e4 33#include <linux/init.h>
d052d1be 34#include <linux/platform_device.h>
1da177e4 35#include <linux/interrupt.h>
f8ce2547 36#include <linux/clk.h>
41dc8b72
AC
37#include <linux/uaccess.h>
38#include <linux/io.h>
e02f838e 39#include <linux/cpufreq.h>
1da177e4 40
a09e64fb 41#include <mach/map.h>
1da177e4 42
b430708a
BD
43#undef S3C_VA_WATCHDOG
44#define S3C_VA_WATCHDOG (0)
1da177e4 45
180ee700 46#include <plat/regs-watchdog.h>
1da177e4
LT
47
48#define PFX "s3c2410-wdt: "
49
50#define CONFIG_S3C2410_WATCHDOG_ATBOOT (0)
51#define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME (15)
52
25ff3780 53static int nowayout = WATCHDOG_NOWAYOUT;
1da177e4
LT
54static int tmr_margin = CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME;
55static int tmr_atboot = CONFIG_S3C2410_WATCHDOG_ATBOOT;
41dc8b72
AC
56static int soft_noboot;
57static int debug;
1da177e4
LT
58
59module_param(tmr_margin, int, 0);
60module_param(tmr_atboot, int, 0);
61module_param(nowayout, int, 0);
62module_param(soft_noboot, int, 0);
63module_param(debug, int, 0);
64
41dc8b72
AC
65MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. default="
66 __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME) ")");
67MODULE_PARM_DESC(tmr_atboot,
68 "Watchdog is started at boot time if set to 1, default="
69 __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_ATBOOT));
70MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
71 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
a77dba7e
WVS
72MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, "
73 "0 to reboot (default depends on ONLY_TESTING)");
1da177e4
LT
74MODULE_PARM_DESC(debug, "Watchdog debug, set to >1 for debug, (default 0)");
75
41dc8b72 76static unsigned long open_lock;
e8ef92b8 77static struct device *wdt_dev; /* platform device attached to */
1da177e4
LT
78static struct resource *wdt_mem;
79static struct resource *wdt_irq;
80static struct clk *wdt_clock;
81static void __iomem *wdt_base;
82static unsigned int wdt_count;
a77dba7e 83static char expect_close;
41dc8b72 84static DEFINE_SPINLOCK(wdt_lock);
1da177e4
LT
85
86/* watchdog control routines */
87
88#define DBG(msg...) do { \
89 if (debug) \
90 printk(KERN_INFO msg); \
41dc8b72 91 } while (0)
1da177e4
LT
92
93/* functions */
94
41dc8b72 95static void s3c2410wdt_keepalive(void)
1da177e4 96{
41dc8b72 97 spin_lock(&wdt_lock);
1da177e4 98 writel(wdt_count, wdt_base + S3C2410_WTCNT);
41dc8b72 99 spin_unlock(&wdt_lock);
1da177e4
LT
100}
101
41dc8b72
AC
102static void __s3c2410wdt_stop(void)
103{
104 unsigned long wtcon;
105
106 wtcon = readl(wdt_base + S3C2410_WTCON);
107 wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN);
108 writel(wtcon, wdt_base + S3C2410_WTCON);
109}
110
111static void s3c2410wdt_stop(void)
112{
113 spin_lock(&wdt_lock);
114 __s3c2410wdt_stop();
115 spin_unlock(&wdt_lock);
1da177e4
LT
116}
117
41dc8b72 118static void s3c2410wdt_start(void)
1da177e4
LT
119{
120 unsigned long wtcon;
121
41dc8b72
AC
122 spin_lock(&wdt_lock);
123
124 __s3c2410wdt_stop();
1da177e4
LT
125
126 wtcon = readl(wdt_base + S3C2410_WTCON);
127 wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128;
128
129 if (soft_noboot) {
130 wtcon |= S3C2410_WTCON_INTEN;
131 wtcon &= ~S3C2410_WTCON_RSTEN;
132 } else {
133 wtcon &= ~S3C2410_WTCON_INTEN;
134 wtcon |= S3C2410_WTCON_RSTEN;
135 }
136
137 DBG("%s: wdt_count=0x%08x, wtcon=%08lx\n",
fa9363c5 138 __func__, wdt_count, wtcon);
1da177e4
LT
139
140 writel(wdt_count, wdt_base + S3C2410_WTDAT);
141 writel(wdt_count, wdt_base + S3C2410_WTCNT);
142 writel(wtcon, wdt_base + S3C2410_WTCON);
41dc8b72 143 spin_unlock(&wdt_lock);
1da177e4
LT
144}
145
e02f838e
BD
146static inline int s3c2410wdt_is_running(void)
147{
148 return readl(wdt_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE;
149}
150
1da177e4
LT
151static int s3c2410wdt_set_heartbeat(int timeout)
152{
e02f838e 153 unsigned long freq = clk_get_rate(wdt_clock);
1da177e4
LT
154 unsigned int count;
155 unsigned int divisor = 1;
156 unsigned long wtcon;
157
158 if (timeout < 1)
159 return -EINVAL;
160
161 freq /= 128;
162 count = timeout * freq;
163
e02f838e 164 DBG("%s: count=%d, timeout=%d, freq=%lu\n",
fa9363c5 165 __func__, count, timeout, freq);
1da177e4
LT
166
167 /* if the count is bigger than the watchdog register,
168 then work out what we need to do (and if) we can
169 actually make this value
170 */
171
172 if (count >= 0x10000) {
173 for (divisor = 1; divisor <= 0x100; divisor++) {
174 if ((count / divisor) < 0x10000)
175 break;
176 }
177
178 if ((count / divisor) >= 0x10000) {
e8ef92b8 179 dev_err(wdt_dev, "timeout %d too big\n", timeout);
1da177e4
LT
180 return -EINVAL;
181 }
182 }
183
184 tmr_margin = timeout;
185
186 DBG("%s: timeout=%d, divisor=%d, count=%d (%08x)\n",
fa9363c5 187 __func__, timeout, divisor, count, count/divisor);
1da177e4
LT
188
189 count /= divisor;
190 wdt_count = count;
191
192 /* update the pre-scaler */
193 wtcon = readl(wdt_base + S3C2410_WTCON);
194 wtcon &= ~S3C2410_WTCON_PRESCALE_MASK;
195 wtcon |= S3C2410_WTCON_PRESCALE(divisor-1);
196
197 writel(count, wdt_base + S3C2410_WTDAT);
198 writel(wtcon, wdt_base + S3C2410_WTCON);
199
200 return 0;
201}
202
203/*
204 * /dev/watchdog handling
205 */
206
207static int s3c2410wdt_open(struct inode *inode, struct file *file)
208{
41dc8b72 209 if (test_and_set_bit(0, &open_lock))
1da177e4
LT
210 return -EBUSY;
211
25ff3780 212 if (nowayout)
1da177e4 213 __module_get(THIS_MODULE);
25ff3780 214
a77dba7e 215 expect_close = 0;
1da177e4
LT
216
217 /* start the timer */
218 s3c2410wdt_start();
219 return nonseekable_open(inode, file);
220}
221
222static int s3c2410wdt_release(struct inode *inode, struct file *file)
223{
224 /*
225 * Shut off the timer.
226 * Lock it in if it's a module and we set nowayout
227 */
25ff3780 228
a77dba7e 229 if (expect_close == 42)
1da177e4 230 s3c2410wdt_stop();
41dc8b72 231 else {
e8ef92b8 232 dev_err(wdt_dev, "Unexpected close, not stopping watchdog\n");
1da177e4
LT
233 s3c2410wdt_keepalive();
234 }
a77dba7e 235 expect_close = 0;
41dc8b72 236 clear_bit(0, &open_lock);
1da177e4
LT
237 return 0;
238}
239
240static ssize_t s3c2410wdt_write(struct file *file, const char __user *data,
241 size_t len, loff_t *ppos)
242{
243 /*
244 * Refresh the timer.
245 */
41dc8b72 246 if (len) {
1da177e4
LT
247 if (!nowayout) {
248 size_t i;
249
250 /* In case it was set long ago */
a77dba7e 251 expect_close = 0;
1da177e4
LT
252
253 for (i = 0; i != len; i++) {
254 char c;
255
256 if (get_user(c, data + i))
257 return -EFAULT;
258 if (c == 'V')
a77dba7e 259 expect_close = 42;
1da177e4
LT
260 }
261 }
1da177e4
LT
262 s3c2410wdt_keepalive();
263 }
264 return len;
265}
266
a77dba7e 267#define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)
1da177e4 268
41dc8b72 269static const struct watchdog_info s3c2410_wdt_ident = {
1da177e4
LT
270 .options = OPTIONS,
271 .firmware_version = 0,
272 .identity = "S3C2410 Watchdog",
273};
274
275
41dc8b72
AC
276static long s3c2410wdt_ioctl(struct file *file, unsigned int cmd,
277 unsigned long arg)
1da177e4
LT
278{
279 void __user *argp = (void __user *)arg;
280 int __user *p = argp;
281 int new_margin;
282
283 switch (cmd) {
41dc8b72
AC
284 case WDIOC_GETSUPPORT:
285 return copy_to_user(argp, &s3c2410_wdt_ident,
286 sizeof(s3c2410_wdt_ident)) ? -EFAULT : 0;
287 case WDIOC_GETSTATUS:
288 case WDIOC_GETBOOTSTATUS:
289 return put_user(0, p);
290 case WDIOC_KEEPALIVE:
291 s3c2410wdt_keepalive();
292 return 0;
293 case WDIOC_SETTIMEOUT:
294 if (get_user(new_margin, p))
295 return -EFAULT;
296 if (s3c2410wdt_set_heartbeat(new_margin))
297 return -EINVAL;
298 s3c2410wdt_keepalive();
299 return put_user(tmr_margin, p);
300 case WDIOC_GETTIMEOUT:
301 return put_user(tmr_margin, p);
0c06090c
WVS
302 default:
303 return -ENOTTY;
1da177e4
LT
304 }
305}
306
1da177e4
LT
307/* kernel interface */
308
62322d25 309static const struct file_operations s3c2410wdt_fops = {
1da177e4
LT
310 .owner = THIS_MODULE,
311 .llseek = no_llseek,
312 .write = s3c2410wdt_write,
41dc8b72 313 .unlocked_ioctl = s3c2410wdt_ioctl,
1da177e4
LT
314 .open = s3c2410wdt_open,
315 .release = s3c2410wdt_release,
316};
317
318static struct miscdevice s3c2410wdt_miscdev = {
319 .minor = WATCHDOG_MINOR,
320 .name = "watchdog",
321 .fops = &s3c2410wdt_fops,
322};
323
1da177e4
LT
324/* interrupt handler code */
325
7d12e780 326static irqreturn_t s3c2410wdt_irq(int irqno, void *param)
1da177e4 327{
e8ef92b8 328 dev_info(wdt_dev, "watchdog timer expired (irq)\n");
1da177e4
LT
329
330 s3c2410wdt_keepalive();
331 return IRQ_HANDLED;
332}
e02f838e
BD
333
334
335#ifdef CONFIG_CPU_FREQ
336
337static int s3c2410wdt_cpufreq_transition(struct notifier_block *nb,
338 unsigned long val, void *data)
339{
340 int ret;
341
342 if (!s3c2410wdt_is_running())
343 goto done;
344
345 if (val == CPUFREQ_PRECHANGE) {
346 /* To ensure that over the change we don't cause the
347 * watchdog to trigger, we perform an keep-alive if
348 * the watchdog is running.
349 */
350
351 s3c2410wdt_keepalive();
352 } else if (val == CPUFREQ_POSTCHANGE) {
353 s3c2410wdt_stop();
354
355 ret = s3c2410wdt_set_heartbeat(tmr_margin);
356
357 if (ret >= 0)
358 s3c2410wdt_start();
359 else
360 goto err;
361 }
362
363done:
364 return 0;
365
366 err:
367 dev_err(wdt_dev, "cannot set new value for timeout %d\n", tmr_margin);
368 return ret;
369}
370
371static struct notifier_block s3c2410wdt_cpufreq_transition_nb = {
372 .notifier_call = s3c2410wdt_cpufreq_transition,
373};
374
375static inline int s3c2410wdt_cpufreq_register(void)
376{
377 return cpufreq_register_notifier(&s3c2410wdt_cpufreq_transition_nb,
378 CPUFREQ_TRANSITION_NOTIFIER);
379}
380
381static inline void s3c2410wdt_cpufreq_deregister(void)
382{
383 cpufreq_unregister_notifier(&s3c2410wdt_cpufreq_transition_nb,
384 CPUFREQ_TRANSITION_NOTIFIER);
385}
386
387#else
388static inline int s3c2410wdt_cpufreq_register(void)
389{
390 return 0;
391}
392
393static inline void s3c2410wdt_cpufreq_deregister(void)
394{
395}
396#endif
397
398
399
1da177e4
LT
400/* device interface */
401
a77dba7e 402static int __devinit s3c2410wdt_probe(struct platform_device *pdev)
1da177e4 403{
1da177e4 404 struct resource *res;
e8ef92b8 405 struct device *dev;
46b814d6 406 unsigned int wtcon;
1da177e4
LT
407 int started = 0;
408 int ret;
409 int size;
410
fa9363c5 411 DBG("%s: probe=%p\n", __func__, pdev);
1da177e4 412
e8ef92b8
BD
413 dev = &pdev->dev;
414 wdt_dev = &pdev->dev;
415
1da177e4
LT
416 /* get the memory region for the watchdog timer */
417
418 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
419 if (res == NULL) {
e8ef92b8 420 dev_err(dev, "no memory resource specified\n");
1da177e4
LT
421 return -ENOENT;
422 }
423
b782a563 424 size = resource_size(res);
1da177e4
LT
425 wdt_mem = request_mem_region(res->start, size, pdev->name);
426 if (wdt_mem == NULL) {
e8ef92b8 427 dev_err(dev, "failed to get memory region\n");
0b6dd8a6
BD
428 ret = -ENOENT;
429 goto err_req;
1da177e4
LT
430 }
431
432 wdt_base = ioremap(res->start, size);
b4253f8f 433 if (wdt_base == NULL) {
e8ef92b8 434 dev_err(dev, "failed to ioremap() region\n");
0b6dd8a6
BD
435 ret = -EINVAL;
436 goto err_req;
1da177e4
LT
437 }
438
439 DBG("probe: mapped wdt_base=%p\n", wdt_base);
440
62be0741
AP
441 wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
442 if (wdt_irq == NULL) {
e8ef92b8 443 dev_err(dev, "no irq resource specified\n");
0b6dd8a6
BD
444 ret = -ENOENT;
445 goto err_map;
1da177e4
LT
446 }
447
62be0741 448 ret = request_irq(wdt_irq->start, s3c2410wdt_irq, 0, pdev->name, pdev);
1da177e4 449 if (ret != 0) {
e8ef92b8 450 dev_err(dev, "failed to install irq (%d)\n", ret);
0b6dd8a6 451 goto err_map;
1da177e4
LT
452 }
453
3ae5eaec 454 wdt_clock = clk_get(&pdev->dev, "watchdog");
9cd44619 455 if (IS_ERR(wdt_clock)) {
e8ef92b8 456 dev_err(dev, "failed to find watchdog clock source\n");
9cd44619 457 ret = PTR_ERR(wdt_clock);
0b6dd8a6 458 goto err_irq;
1da177e4
LT
459 }
460
1da177e4
LT
461 clk_enable(wdt_clock);
462
e02f838e
BD
463 if (s3c2410wdt_cpufreq_register() < 0) {
464 printk(KERN_ERR PFX "failed to register cpufreq\n");
465 goto err_clk;
466 }
467
1da177e4
LT
468 /* see if we can actually set the requested timer margin, and if
469 * not, try the default value */
470
471 if (s3c2410wdt_set_heartbeat(tmr_margin)) {
41dc8b72
AC
472 started = s3c2410wdt_set_heartbeat(
473 CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
1da177e4 474
41dc8b72
AC
475 if (started == 0)
476 dev_info(dev,
477 "tmr_margin value out of range, default %d used\n",
1da177e4 478 CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
41dc8b72 479 else
a77dba7e
WVS
480 dev_info(dev, "default timer value is out of range, "
481 "cannot start\n");
1da177e4
LT
482 }
483
1da177e4
LT
484 ret = misc_register(&s3c2410wdt_miscdev);
485 if (ret) {
e8ef92b8 486 dev_err(dev, "cannot register miscdev on minor=%d (%d)\n",
1da177e4 487 WATCHDOG_MINOR, ret);
e02f838e 488 goto err_cpufreq;
1da177e4
LT
489 }
490
491 if (tmr_atboot && started == 0) {
e8ef92b8 492 dev_info(dev, "starting watchdog timer\n");
1da177e4 493 s3c2410wdt_start();
655516c8
BD
494 } else if (!tmr_atboot) {
495 /* if we're not enabling the watchdog, then ensure it is
496 * disabled if it has been left running from the bootloader
497 * or other source */
498
499 s3c2410wdt_stop();
1da177e4
LT
500 }
501
46b814d6
BD
502 /* print out a statement of readiness */
503
504 wtcon = readl(wdt_base + S3C2410_WTCON);
505
e8ef92b8 506 dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n",
46b814d6
BD
507 (wtcon & S3C2410_WTCON_ENABLE) ? "" : "in",
508 (wtcon & S3C2410_WTCON_RSTEN) ? "" : "dis",
509 (wtcon & S3C2410_WTCON_INTEN) ? "" : "en");
41dc8b72 510
1da177e4 511 return 0;
0b6dd8a6 512
e02f838e
BD
513 err_cpufreq:
514 s3c2410wdt_cpufreq_deregister();
515
0b6dd8a6
BD
516 err_clk:
517 clk_disable(wdt_clock);
518 clk_put(wdt_clock);
519
520 err_irq:
521 free_irq(wdt_irq->start, pdev);
522
523 err_map:
524 iounmap(wdt_base);
525
526 err_req:
527 release_resource(wdt_mem);
528 kfree(wdt_mem);
529
530 return ret;
1da177e4
LT
531}
532
a77dba7e 533static int __devexit s3c2410wdt_remove(struct platform_device *dev)
1da177e4 534{
e02f838e
BD
535 s3c2410wdt_cpufreq_deregister();
536
0b6dd8a6
BD
537 release_resource(wdt_mem);
538 kfree(wdt_mem);
539 wdt_mem = NULL;
1da177e4 540
0b6dd8a6
BD
541 free_irq(wdt_irq->start, dev);
542 wdt_irq = NULL;
1da177e4 543
0b6dd8a6
BD
544 clk_disable(wdt_clock);
545 clk_put(wdt_clock);
546 wdt_clock = NULL;
1da177e4 547
e34477e9 548 iounmap(wdt_base);
1da177e4
LT
549 misc_deregister(&s3c2410wdt_miscdev);
550 return 0;
551}
552
3ae5eaec 553static void s3c2410wdt_shutdown(struct platform_device *dev)
94f1e9f3 554{
41dc8b72 555 s3c2410wdt_stop();
94f1e9f3
BD
556}
557
af4bb822
BD
558#ifdef CONFIG_PM
559
560static unsigned long wtcon_save;
561static unsigned long wtdat_save;
562
3ae5eaec 563static int s3c2410wdt_suspend(struct platform_device *dev, pm_message_t state)
af4bb822 564{
9480e307
RK
565 /* Save watchdog state, and turn it off. */
566 wtcon_save = readl(wdt_base + S3C2410_WTCON);
567 wtdat_save = readl(wdt_base + S3C2410_WTDAT);
af4bb822 568
9480e307
RK
569 /* Note that WTCNT doesn't need to be saved. */
570 s3c2410wdt_stop();
af4bb822
BD
571
572 return 0;
573}
574
3ae5eaec 575static int s3c2410wdt_resume(struct platform_device *dev)
af4bb822 576{
9480e307 577 /* Restore watchdog state. */
af4bb822 578
9480e307
RK
579 writel(wtdat_save, wdt_base + S3C2410_WTDAT);
580 writel(wtdat_save, wdt_base + S3C2410_WTCNT); /* Reset count */
581 writel(wtcon_save, wdt_base + S3C2410_WTCON);
af4bb822 582
9480e307
RK
583 printk(KERN_INFO PFX "watchdog %sabled\n",
584 (wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis");
af4bb822
BD
585
586 return 0;
587}
588
589#else
590#define s3c2410wdt_suspend NULL
591#define s3c2410wdt_resume NULL
592#endif /* CONFIG_PM */
593
594
3ae5eaec 595static struct platform_driver s3c2410wdt_driver = {
1da177e4 596 .probe = s3c2410wdt_probe,
a77dba7e 597 .remove = __devexit_p(s3c2410wdt_remove),
94f1e9f3 598 .shutdown = s3c2410wdt_shutdown,
af4bb822
BD
599 .suspend = s3c2410wdt_suspend,
600 .resume = s3c2410wdt_resume,
3ae5eaec
RK
601 .driver = {
602 .owner = THIS_MODULE,
603 .name = "s3c2410-wdt",
604 },
1da177e4
LT
605};
606
607
41dc8b72
AC
608static char banner[] __initdata =
609 KERN_INFO "S3C2410 Watchdog Timer, (c) 2004 Simtec Electronics\n";
1da177e4
LT
610
611static int __init watchdog_init(void)
612{
613 printk(banner);
3ae5eaec 614 return platform_driver_register(&s3c2410wdt_driver);
1da177e4
LT
615}
616
617static void __exit watchdog_exit(void)
618{
3ae5eaec 619 platform_driver_unregister(&s3c2410wdt_driver);
1da177e4
LT
620}
621
622module_init(watchdog_init);
623module_exit(watchdog_exit);
624
af4bb822
BD
625MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, "
626 "Dimitry Andric <dimitry.andric@tomtom.com>");
1da177e4
LT
627MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver");
628MODULE_LICENSE("GPL");
629MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
f37d193c 630MODULE_ALIAS("platform:s3c2410-wdt");
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