[deliverable/linux.git] / drivers / watchdog / shwdt.c

/*
 * drivers/watchdog/shwdt.c
 *
 * Watchdog driver for integrated watchdog in the SuperH processors.
 *
 * Copyright (C) 2001 - 2012  Paul Mundt <lethal@linux-sh.org>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * 14-Dec-2001 Matt Domsch <Matt_Domsch@dell.com>
 *     Added nowayout module option to override CONFIG_WATCHDOG_NOWAYOUT
 *
 * 19-Apr-2002 Rob Radez <rob@osinvestor.com>
 *     Added expect close support, made emulated timeout runtime changeable
 *     general cleanups, add some ioctls
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/spinlock.h>
#include <linux/miscdevice.h>
#include <linux/watchdog.h>
#include <linux/pm_runtime.h>
#include <linux/fs.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <asm/watchdog.h>

#define DRV_NAME "sh-wdt"

/*
 * Default clock division ratio is 5.25 msecs. For an additional table of
 * values, consult the asm-sh/watchdog.h. Overload this at module load
 * time.
 *
 * In order for this to work reliably we need to have HZ set to 1000 or
 * something quite higher than 100 (or we need a proper high-res timer
 * implementation that will deal with this properly), otherwise the 10ms
 * resolution of a jiffy is enough to trigger the overflow. For things like
 * the SH-4 and SH-5, this isn't necessarily that big of a problem, though
 * for the SH-2 and SH-3, this isn't recommended unless the WDT is absolutely
 * necssary.
 *
 * As a result of this timing problem, the only modes that are particularly
 * feasible are the 4096 and the 2048 divisors, which yield 5.25 and 2.62ms
 * overflow periods respectively.
 *
 * Also, since we can't really expect userspace to be responsive enough
 * before the overflow happens, we maintain two separate timers .. One in
 * the kernel for clearing out WOVF every 2ms or so (again, this depends on
 * HZ == 1000), and another for monitoring userspace writes to the WDT device.
 *
 * As such, we currently use a configurable heartbeat interval which defaults
 * to 30s. In this case, the userspace daemon is only responsible for periodic
 * writes to the device before the next heartbeat is scheduled. If the daemon
 * misses its deadline, the kernel timer will allow the WDT to overflow.
 */
static int clock_division_ratio = WTCSR_CKS_4096;
#define next_ping_period(cks)	(jiffies + msecs_to_jiffies(cks - 4))

#define WATCHDOG_HEARTBEAT 30			/* 30 sec default heartbeat */
static int heartbeat = WATCHDOG_HEARTBEAT;	/* in seconds */
static bool nowayout = WATCHDOG_NOWAYOUT;
static unsigned long next_heartbeat;

struct sh_wdt {
	void __iomem		*base;
	struct device		*dev;
	struct clk		*clk;
	spinlock_t		lock;

	struct timer_list	timer;
};

static int sh_wdt_start(struct watchdog_device *wdt_dev)
{
	struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
	unsigned long flags;
	u8 csr;

	pm_runtime_get_sync(wdt->dev);
	clk_enable(wdt->clk);

	spin_lock_irqsave(&wdt->lock, flags);

	next_heartbeat = jiffies + (heartbeat * HZ);
	mod_timer(&wdt->timer, next_ping_period(clock_division_ratio));

	csr = sh_wdt_read_csr();
	csr |= WTCSR_WT | clock_division_ratio;
	sh_wdt_write_csr(csr);

	sh_wdt_write_cnt(0);

	/*
	 * These processors have a bit of an inconsistent initialization
	 * process.. starting with SH-3, RSTS was moved to WTCSR, and the
	 * RSTCSR register was removed.
	 *
	 * On the SH-2 however, in addition with bits being in different
	 * locations, we must deal with RSTCSR outright..
	 */
	csr = sh_wdt_read_csr();
	csr |= WTCSR_TME;
	csr &= ~WTCSR_RSTS;
	sh_wdt_write_csr(csr);

#ifdef CONFIG_CPU_SH2
	csr = sh_wdt_read_rstcsr();
	csr &= ~RSTCSR_RSTS;
	sh_wdt_write_rstcsr(csr);
#endif
	spin_unlock_irqrestore(&wdt->lock, flags);

	return 0;
}

static int sh_wdt_stop(struct watchdog_device *wdt_dev)
{
	struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
	unsigned long flags;
	u8 csr;

	spin_lock_irqsave(&wdt->lock, flags);

	del_timer(&wdt->timer);

	csr = sh_wdt_read_csr();
	csr &= ~WTCSR_TME;
	sh_wdt_write_csr(csr);

	spin_unlock_irqrestore(&wdt->lock, flags);

	clk_disable(wdt->clk);
	pm_runtime_put_sync(wdt->dev);

	return 0;
}

static int sh_wdt_keepalive(struct watchdog_device *wdt_dev)
{
	struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
	unsigned long flags;

	spin_lock_irqsave(&wdt->lock, flags);
	next_heartbeat = jiffies + (heartbeat * HZ);
	spin_unlock_irqrestore(&wdt->lock, flags);

	return 0;
}

static int sh_wdt_set_heartbeat(struct watchdog_device *wdt_dev, unsigned t)
{
	struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
	unsigned long flags;

	if (unlikely(t < 1 || t > 3600)) /* arbitrary upper limit */
		return -EINVAL;

	spin_lock_irqsave(&wdt->lock, flags);
	heartbeat = t;
	wdt_dev->timeout = t;
	spin_unlock_irqrestore(&wdt->lock, flags);

	return 0;
}

static void sh_wdt_ping(unsigned long data)
{
	struct sh_wdt *wdt = (struct sh_wdt *)data;
	unsigned long flags;

	spin_lock_irqsave(&wdt->lock, flags);
	if (time_before(jiffies, next_heartbeat)) {
		u8 csr;

		csr = sh_wdt_read_csr();
		csr &= ~WTCSR_IOVF;
		sh_wdt_write_csr(csr);

		sh_wdt_write_cnt(0);

		mod_timer(&wdt->timer, next_ping_period(clock_division_ratio));
	} else
		dev_warn(wdt->dev, "Heartbeat lost! Will not ping "
		         "the watchdog\n");
	spin_unlock_irqrestore(&wdt->lock, flags);
}

static const struct watchdog_info sh_wdt_info = {
	.options		= WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
				  WDIOF_MAGICCLOSE,
	.firmware_version	= 1,
	.identity		= "SH WDT",
};

static const struct watchdog_ops sh_wdt_ops = {
	.owner		= THIS_MODULE,
	.start		= sh_wdt_start,
	.stop		= sh_wdt_stop,
	.ping		= sh_wdt_keepalive,
	.set_timeout	= sh_wdt_set_heartbeat,
};

static struct watchdog_device sh_wdt_dev = {
	.info	= &sh_wdt_info,
	.ops	= &sh_wdt_ops,
};

static int sh_wdt_probe(struct platform_device *pdev)
{
	struct sh_wdt *wdt;
	struct resource *res;
	int rc;

	/*
	 * As this driver only covers the global watchdog case, reject
	 * any attempts to register per-CPU watchdogs.
	 */
	if (pdev->id != -1)
		return -EINVAL;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (unlikely(!res))
		return -EINVAL;

	wdt = devm_kzalloc(&pdev->dev, sizeof(struct sh_wdt), GFP_KERNEL);
	if (unlikely(!wdt))
		return -ENOMEM;

	wdt->dev = &pdev->dev;

	wdt->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(wdt->clk)) {
		/*
		 * Clock framework support is optional, continue on
		 * anyways if we don't find a matching clock.
		 */
		wdt->clk = NULL;
	}

	wdt->base = devm_ioremap_resource(wdt->dev, res);
	if (IS_ERR(wdt->base))
		return PTR_ERR(wdt->base);

	watchdog_set_nowayout(&sh_wdt_dev, nowayout);
	watchdog_set_drvdata(&sh_wdt_dev, wdt);

	spin_lock_init(&wdt->lock);

	rc = sh_wdt_set_heartbeat(&sh_wdt_dev, heartbeat);
	if (unlikely(rc)) {
		/* Default timeout if invalid */
		sh_wdt_set_heartbeat(&sh_wdt_dev, WATCHDOG_HEARTBEAT);

		dev_warn(&pdev->dev,
			 "heartbeat value must be 1<=x<=3600, using %d\n",
			 sh_wdt_dev.timeout);
	}

	dev_info(&pdev->dev, "configured with heartbeat=%d sec (nowayout=%d)\n",
		 sh_wdt_dev.timeout, nowayout);

	rc = watchdog_register_device(&sh_wdt_dev);
	if (unlikely(rc)) {
		dev_err(&pdev->dev, "Can't register watchdog (err=%d)\n", rc);
		return rc;
	}

	init_timer(&wdt->timer);
	wdt->timer.function	= sh_wdt_ping;
	wdt->timer.data		= (unsigned long)wdt;
	wdt->timer.expires	= next_ping_period(clock_division_ratio);

	platform_set_drvdata(pdev, wdt);

	dev_info(&pdev->dev, "initialized.\n");

	pm_runtime_enable(&pdev->dev);

	return 0;
}

static int sh_wdt_remove(struct platform_device *pdev)
{
	struct sh_wdt *wdt = platform_get_drvdata(pdev);

	watchdog_unregister_device(&sh_wdt_dev);

	pm_runtime_disable(&pdev->dev);

	return 0;
}

static void sh_wdt_shutdown(struct platform_device *pdev)
{
	sh_wdt_stop(&sh_wdt_dev);
}

static struct platform_driver sh_wdt_driver = {
	.driver		= {
		.name	= DRV_NAME,
		.owner	= THIS_MODULE,
	},

	.probe		= sh_wdt_probe,
	.remove		= sh_wdt_remove,
	.shutdown	= sh_wdt_shutdown,
};

static int __init sh_wdt_init(void)
{
	if (unlikely(clock_division_ratio < 0x5 ||
		     clock_division_ratio > 0x7)) {
		clock_division_ratio = WTCSR_CKS_4096;

		pr_info("divisor must be 0x5<=x<=0x7, using %d\n",
			clock_division_ratio);
	}

	return platform_driver_register(&sh_wdt_driver);
}

static void __exit sh_wdt_exit(void)
{
	platform_driver_unregister(&sh_wdt_driver);
}
module_init(sh_wdt_init);
module_exit(sh_wdt_exit);

MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>");
MODULE_DESCRIPTION("SuperH watchdog driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRV_NAME);
MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);

module_param(clock_division_ratio, int, 0);
MODULE_PARM_DESC(clock_division_ratio,
	"Clock division ratio. Valid ranges are from 0x5 (1.31ms) "
	"to 0x7 (5.25ms). (default=" __MODULE_STRING(WTCSR_CKS_4096) ")");

module_param(heartbeat, int, 0);
MODULE_PARM_DESC(heartbeat,
	"Watchdog heartbeat in seconds. (1 <= heartbeat <= 3600, default="
				__MODULE_STRING(WATCHDOG_HEARTBEAT) ")");

module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
	"Watchdog cannot be stopped once started (default="
				__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
Commit	Line	Data
1da177e4	1	/*
b1fa888e	2	* drivers/watchdog/shwdt.c
1da177e4 LT	3	*
	4	* Watchdog driver for integrated watchdog in the SuperH processors.
	5	*
40968126	6	* Copyright (C) 2001 - 2012 Paul Mundt <lethal@linux-sh.org>
1da177e4 LT	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*
	13	* 14-Dec-2001 Matt Domsch <Matt_Domsch@dell.com>
	14	* Added nowayout module option to override CONFIG_WATCHDOG_NOWAYOUT
	15	*
	16	* 19-Apr-2002 Rob Radez <rob@osinvestor.com>
	17	* Added expect close support, made emulated timeout runtime changeable
	18	* general cleanups, add some ioctls
	19	*/
27c766aa JP	20
	21	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	22
1da177e4 LT	23	#include <linux/module.h>
1da177e4 LT	24	#include <linux/moduleparam.h>
8f5585ec	25	#include <linux/platform_device.h>
1da177e4 LT	26	#include <linux/init.h>
1da177e4 LT	27	#include <linux/types.h>
f9fb360c	28	#include <linux/spinlock.h>
1da177e4 LT	29	#include <linux/miscdevice.h>
1da177e4 LT	30	#include <linux/watchdog.h>
8c013d96	31	#include <linux/pm_runtime.h>
1da177e4	32	#include <linux/fs.h>
f118420b	33	#include <linux/mm.h>
8f5585ec	34	#include <linux/slab.h>
70b814ec	35	#include <linux/io.h>
9ea64046	36	#include <linux/clk.h>
6330c707	37	#include <linux/err.h>
58cf4198	38	#include <asm/watchdog.h>
1da177e4	39
8f5585ec	40	#define DRV_NAME "sh-wdt"
1da177e4 LT	41
	42	/*
	43	* Default clock division ratio is 5.25 msecs. For an additional table of
	44	* values, consult the asm-sh/watchdog.h. Overload this at module load
	45	* time.
	46	*
	47	* In order for this to work reliably we need to have HZ set to 1000 or
	48	* something quite higher than 100 (or we need a proper high-res timer
	49	* implementation that will deal with this properly), otherwise the 10ms
	50	* resolution of a jiffy is enough to trigger the overflow. For things like
	51	* the SH-4 and SH-5, this isn't necessarily that big of a problem, though
	52	* for the SH-2 and SH-3, this isn't recommended unless the WDT is absolutely
	53	* necssary.
	54	*
	55	* As a result of this timing problem, the only modes that are particularly
25985edc	56	* feasible are the 4096 and the 2048 divisors, which yield 5.25 and 2.62ms
1da177e4 LT	57	* overflow periods respectively.
	58	*
	59	* Also, since we can't really expect userspace to be responsive enough
ee0fc097	60	* before the overflow happens, we maintain two separate timers .. One in
1da177e4 LT	61	* the kernel for clearing out WOVF every 2ms or so (again, this depends on
	62	* HZ == 1000), and another for monitoring userspace writes to the WDT device.
	63	*
	64	* As such, we currently use a configurable heartbeat interval which defaults
	65	* to 30s. In this case, the userspace daemon is only responsible for periodic
	66	* writes to the device before the next heartbeat is scheduled. If the daemon
	67	* misses its deadline, the kernel timer will allow the WDT to overflow.
	68	*/
	69	static int clock_division_ratio = WTCSR_CKS_4096;
bea19066	70	#define next_ping_period(cks) (jiffies + msecs_to_jiffies(cks - 4))
1da177e4	71
1da177e4 LT	72	#define WATCHDOG_HEARTBEAT 30 /* 30 sec default heartbeat */
1da177e4 LT	73	static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
86a1e189	74	static bool nowayout = WATCHDOG_NOWAYOUT;
8f5585ec PM	75	static unsigned long next_heartbeat;
	76
	77	struct sh_wdt {
	78	void __iomem *base;
	79	struct device *dev;
9ea64046	80	struct clk *clk;
f9fb360c	81	spinlock_t lock;
1da177e4	82
8f5585ec	83	struct timer_list timer;
8f5585ec PM	84	};
8f5585ec PM	85
1950f499	86	static int sh_wdt_start(struct watchdog_device *wdt_dev)
1da177e4	87	{
1950f499	88	struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
70b814ec	89	unsigned long flags;
8f5585ec	90	u8 csr;
70b814ec	91
8c013d96	92	pm_runtime_get_sync(wdt->dev);
d42c9744	93	clk_enable(wdt->clk);
8c013d96	94
f9fb360c	95	spin_lock_irqsave(&wdt->lock, flags);
1da177e4 LT	96
1da177e4 LT	97	next_heartbeat = jiffies + (heartbeat * HZ);
8f5585ec	98	mod_timer(&wdt->timer, next_ping_period(clock_division_ratio));
1da177e4 LT	99
	100	csr = sh_wdt_read_csr();
	101	csr \|= WTCSR_WT \| clock_division_ratio;
	102	sh_wdt_write_csr(csr);
	103
	104	sh_wdt_write_cnt(0);
	105
	106	/*
	107	* These processors have a bit of an inconsistent initialization
	108	* process.. starting with SH-3, RSTS was moved to WTCSR, and the
	109	* RSTCSR register was removed.
	110	*
	111	* On the SH-2 however, in addition with bits being in different
	112	* locations, we must deal with RSTCSR outright..
	113	*/
	114	csr = sh_wdt_read_csr();
	115	csr \|= WTCSR_TME;
	116	csr &= ~WTCSR_RSTS;
	117	sh_wdt_write_csr(csr);
	118
	119	#ifdef CONFIG_CPU_SH2
1da177e4 LT	120	csr = sh_wdt_read_rstcsr();
	121	csr &= ~RSTCSR_RSTS;
	122	sh_wdt_write_rstcsr(csr);
	123	#endif
f9fb360c	124	spin_unlock_irqrestore(&wdt->lock, flags);
1950f499 PM	125
1950f499 PM	126	return 0;
1da177e4 LT	127	}
1da177e4 LT	128
1950f499	129	static int sh_wdt_stop(struct watchdog_device *wdt_dev)
1da177e4	130	{
1950f499	131	struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
70b814ec	132	unsigned long flags;
8f5585ec	133	u8 csr;
70b814ec	134
f9fb360c	135	spin_lock_irqsave(&wdt->lock, flags);
1da177e4	136
8f5585ec	137	del_timer(&wdt->timer);
1da177e4 LT	138
	139	csr = sh_wdt_read_csr();
	140	csr &= ~WTCSR_TME;
	141	sh_wdt_write_csr(csr);
8f5585ec	142
f9fb360c	143	spin_unlock_irqrestore(&wdt->lock, flags);
1950f499	144
d42c9744	145	clk_disable(wdt->clk);
8c013d96 PM	146	pm_runtime_put_sync(wdt->dev);
8c013d96 PM	147
1950f499	148	return 0;
1da177e4 LT	149	}
1da177e4 LT	150
1950f499	151	static int sh_wdt_keepalive(struct watchdog_device *wdt_dev)
1da177e4	152	{
f9fb360c	153	struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
70b814ec AC	154	unsigned long flags;
70b814ec AC	155
f9fb360c	156	spin_lock_irqsave(&wdt->lock, flags);
1da177e4	157	next_heartbeat = jiffies + (heartbeat * HZ);
f9fb360c	158	spin_unlock_irqrestore(&wdt->lock, flags);
1950f499 PM	159
1950f499 PM	160	return 0;
1da177e4 LT	161	}
1da177e4 LT	162
1950f499	163	static int sh_wdt_set_heartbeat(struct watchdog_device *wdt_dev, unsigned t)
1da177e4	164	{
f9fb360c	165	struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
70b814ec AC	166	unsigned long flags;
	167
	168	if (unlikely(t < 1 \|\| t > 3600)) /* arbitrary upper limit */
1da177e4 LT	169	return -EINVAL;
1da177e4 LT	170
f9fb360c	171	spin_lock_irqsave(&wdt->lock, flags);
1da177e4	172	heartbeat = t;
1950f499	173	wdt_dev->timeout = t;
f9fb360c	174	spin_unlock_irqrestore(&wdt->lock, flags);
1950f499	175
1da177e4 LT	176	return 0;
	177	}
	178
1da177e4 LT	179	static void sh_wdt_ping(unsigned long data)
1da177e4 LT	180	{
8f5585ec	181	struct sh_wdt wdt = (struct sh_wdt )data;
70b814ec AC	182	unsigned long flags;
70b814ec AC	183
f9fb360c	184	spin_lock_irqsave(&wdt->lock, flags);
1da177e4	185	if (time_before(jiffies, next_heartbeat)) {
8f5585ec	186	u8 csr;
1da177e4 LT	187
	188	csr = sh_wdt_read_csr();
	189	csr &= ~WTCSR_IOVF;
	190	sh_wdt_write_csr(csr);
	191
	192	sh_wdt_write_cnt(0);
	193
8f5585ec	194	mod_timer(&wdt->timer, next_ping_period(clock_division_ratio));
e4c2cfee	195	} else
8f5585ec PM	196	dev_warn(wdt->dev, "Heartbeat lost! Will not ping "
8f5585ec PM	197	"the watchdog\n");
f9fb360c	198	spin_unlock_irqrestore(&wdt->lock, flags);
1da177e4 LT	199	}
1da177e4 LT	200
70b814ec	201	static const struct watchdog_info sh_wdt_info = {
e4c2cfee PM	202	.options = WDIOF_KEEPALIVEPING \| WDIOF_SETTIMEOUT \|
e4c2cfee PM	203	WDIOF_MAGICCLOSE,
1da177e4 LT	204	.firmware_version = 1,
	205	.identity = "SH WDT",
	206	};
	207
1950f499 PM	208	static const struct watchdog_ops sh_wdt_ops = {
	209	.owner = THIS_MODULE,
	210	.start = sh_wdt_start,
	211	.stop = sh_wdt_stop,
	212	.ping = sh_wdt_keepalive,
	213	.set_timeout = sh_wdt_set_heartbeat,
	214	};
	215
	216	static struct watchdog_device sh_wdt_dev = {
	217	.info = &sh_wdt_info,
	218	.ops = &sh_wdt_ops,
1da177e4 LT	219	};
1da177e4 LT	220
2d991a16	221	static int sh_wdt_probe(struct platform_device *pdev)
1da177e4	222	{
8f5585ec PM	223	struct sh_wdt *wdt;
8f5585ec PM	224	struct resource *res;
1da177e4 LT	225	int rc;
1da177e4 LT	226
8f5585ec PM	227	/*
	228	* As this driver only covers the global watchdog case, reject
	229	* any attempts to register per-CPU watchdogs.
	230	*/
	231	if (pdev->id != -1)
	232	return -EINVAL;
	233
	234	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	235	if (unlikely(!res))
	236	return -EINVAL;
	237
8f5585ec	238	wdt = devm_kzalloc(&pdev->dev, sizeof(struct sh_wdt), GFP_KERNEL);
9ea64046 PM	239	if (unlikely(!wdt))
9ea64046 PM	240	return -ENOMEM;
1da177e4	241
8f5585ec PM	242	wdt->dev = &pdev->dev;
8f5585ec PM	243
2f7b9b48	244	wdt->clk = devm_clk_get(&pdev->dev, NULL);
9ea64046 PM	245	if (IS_ERR(wdt->clk)) {
	246	/*
	247	* Clock framework support is optional, continue on
	248	* anyways if we don't find a matching clock.
	249	*/
	250	wdt->clk = NULL;
	251	}
f9fb360c	252
6330c707	253	wdt->base = devm_ioremap_resource(wdt->dev, res);
2f7b9b48 JH	254	if (IS_ERR(wdt->base))
2f7b9b48 JH	255	return PTR_ERR(wdt->base);
1da177e4	256
9ea64046 PM	257	watchdog_set_nowayout(&sh_wdt_dev, nowayout);
	258	watchdog_set_drvdata(&sh_wdt_dev, wdt);
	259
f9fb360c PM	260	spin_lock_init(&wdt->lock);
f9fb360c PM	261
1950f499 PM	262	rc = sh_wdt_set_heartbeat(&sh_wdt_dev, heartbeat);
	263	if (unlikely(rc)) {
	264	/* Default timeout if invalid */
	265	sh_wdt_set_heartbeat(&sh_wdt_dev, WATCHDOG_HEARTBEAT);
	266
	267	dev_warn(&pdev->dev,
	268	"heartbeat value must be 1<=x<=3600, using %d\n",
	269	sh_wdt_dev.timeout);
	270	}
	271
	272	dev_info(&pdev->dev, "configured with heartbeat=%d sec (nowayout=%d)\n",
	273	sh_wdt_dev.timeout, nowayout);
8f5585ec	274
1950f499	275	rc = watchdog_register_device(&sh_wdt_dev);
e4c2cfee	276	if (unlikely(rc)) {
1950f499	277	dev_err(&pdev->dev, "Can't register watchdog (err=%d)\n", rc);
2f7b9b48	278	return rc;
1da177e4 LT	279	}
1da177e4 LT	280
8f5585ec PM	281	init_timer(&wdt->timer);
	282	wdt->timer.function = sh_wdt_ping;
	283	wdt->timer.data = (unsigned long)wdt;
	284	wdt->timer.expires = next_ping_period(clock_division_ratio);
	285
	286	platform_set_drvdata(pdev, wdt);
8f5585ec PM	287
8f5585ec PM	288	dev_info(&pdev->dev, "initialized.\n");
1da177e4	289
8c013d96 PM	290	pm_runtime_enable(&pdev->dev);
8c013d96 PM	291
1da177e4 LT	292	return 0;
	293	}
	294
4b12b896	295	static int sh_wdt_remove(struct platform_device *pdev)
1da177e4	296	{
8f5585ec	297	struct sh_wdt *wdt = platform_get_drvdata(pdev);
8f5585ec	298
1950f499	299	watchdog_unregister_device(&sh_wdt_dev);
8f5585ec	300
8c013d96	301	pm_runtime_disable(&pdev->dev);
8f5585ec PM	302
	303	return 0;
	304	}
	305
40968126 PM	306	static void sh_wdt_shutdown(struct platform_device *pdev)
40968126 PM	307	{
1950f499	308	sh_wdt_stop(&sh_wdt_dev);
40968126 PM	309	}
40968126 PM	310
8f5585ec PM	311	static struct platform_driver sh_wdt_driver = {
	312	.driver = {
	313	.name = DRV_NAME,
	314	.owner = THIS_MODULE,
	315	},
	316
40968126	317	.probe = sh_wdt_probe,
82268714	318	.remove = sh_wdt_remove,
40968126	319	.shutdown = sh_wdt_shutdown,
8f5585ec PM	320	};
	321
	322	static int __init sh_wdt_init(void)
	323	{
8f5585ec PM	324	if (unlikely(clock_division_ratio < 0x5 \|\|
	325	clock_division_ratio > 0x7)) {
	326	clock_division_ratio = WTCSR_CKS_4096;
	327
27c766aa JP	328	pr_info("divisor must be 0x5<=x<=0x7, using %d\n",
27c766aa JP	329	clock_division_ratio);
8f5585ec PM	330	}
8f5585ec PM	331
8f5585ec	332	return platform_driver_register(&sh_wdt_driver);
1da177e4 LT	333	}
1da177e4 LT	334
8f5585ec PM	335	static void __exit sh_wdt_exit(void)
	336	{
	337	platform_driver_unregister(&sh_wdt_driver);
	338	}
	339	module_init(sh_wdt_init);
	340	module_exit(sh_wdt_exit);
	341
1da177e4 LT	342	MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>");
	343	MODULE_DESCRIPTION("SuperH watchdog driver");
	344	MODULE_LICENSE("GPL");
8f5585ec	345	MODULE_ALIAS("platform:" DRV_NAME);
1da177e4 LT	346	MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
	347
	348	module_param(clock_division_ratio, int, 0);
a77dba7e WVS	349	MODULE_PARM_DESC(clock_division_ratio,
a77dba7e WVS	350	"Clock division ratio. Valid ranges are from 0x5 (1.31ms) "
76550d32	351	"to 0x7 (5.25ms). (default=" __MODULE_STRING(WTCSR_CKS_4096) ")");
1da177e4 LT	352
1da177e4 LT	353	module_param(heartbeat, int, 0);
70b814ec AC	354	MODULE_PARM_DESC(heartbeat,
	355	"Watchdog heartbeat in seconds. (1 <= heartbeat <= 3600, default="
	356	__MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
1da177e4	357
86a1e189	358	module_param(nowayout, bool, 0);
70b814ec AC	359	MODULE_PARM_DESC(nowayout,
	360	"Watchdog cannot be stopped once started (default="
	361	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");