Commit | Line | Data |
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15e28bf1 PG |
1 | /* |
2 | * sp5100_tco : TCO timer driver for sp5100 chipsets | |
3 | * | |
4 | * (c) Copyright 2009 Google Inc., All Rights Reserved. | |
5 | * | |
6 | * Based on i8xx_tco.c: | |
7 | * (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights | |
8 | * Reserved. | |
9 | * http://www.kernelconcepts.de | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License | |
13 | * as published by the Free Software Foundation; either version | |
14 | * 2 of the License, or (at your option) any later version. | |
15 | * | |
740fbddf TT |
16 | * See AMD Publication 43009 "AMD SB700/710/750 Register Reference Guide", |
17 | * AMD Publication 45482 "AMD SB800-Series Southbridges Register | |
18 | * Reference Guide" | |
15e28bf1 PG |
19 | */ |
20 | ||
21 | /* | |
22 | * Includes, defines, variables, module parameters, ... | |
23 | */ | |
24 | ||
27c766aa JP |
25 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
26 | ||
15e28bf1 PG |
27 | #include <linux/module.h> |
28 | #include <linux/moduleparam.h> | |
29 | #include <linux/types.h> | |
30 | #include <linux/miscdevice.h> | |
31 | #include <linux/watchdog.h> | |
32 | #include <linux/init.h> | |
33 | #include <linux/fs.h> | |
34 | #include <linux/pci.h> | |
35 | #include <linux/ioport.h> | |
36 | #include <linux/platform_device.h> | |
37 | #include <linux/uaccess.h> | |
38 | #include <linux/io.h> | |
39 | ||
40 | #include "sp5100_tco.h" | |
41 | ||
42 | /* Module and version information */ | |
18e43212 | 43 | #define TCO_VERSION "0.05" |
15e28bf1 PG |
44 | #define TCO_MODULE_NAME "SP5100 TCO timer" |
45 | #define TCO_DRIVER_NAME TCO_MODULE_NAME ", v" TCO_VERSION | |
15e28bf1 PG |
46 | |
47 | /* internal variables */ | |
90d241ed | 48 | static u32 tcobase_phys; |
740fbddf | 49 | static u32 tco_wdt_fired; |
15e28bf1 PG |
50 | static void __iomem *tcobase; |
51 | static unsigned int pm_iobase; | |
52 | static DEFINE_SPINLOCK(tco_lock); /* Guards the hardware */ | |
53 | static unsigned long timer_alive; | |
54 | static char tco_expect_close; | |
55 | static struct pci_dev *sp5100_tco_pci; | |
56 | ||
57 | /* the watchdog platform device */ | |
58 | static struct platform_device *sp5100_tco_platform_device; | |
59 | ||
60 | /* module parameters */ | |
61 | ||
62 | #define WATCHDOG_HEARTBEAT 60 /* 60 sec default heartbeat. */ | |
63 | static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */ | |
64 | module_param(heartbeat, int, 0); | |
65 | MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (default=" | |
66 | __MODULE_STRING(WATCHDOG_HEARTBEAT) ")"); | |
67 | ||
86a1e189 WVS |
68 | static bool nowayout = WATCHDOG_NOWAYOUT; |
69 | module_param(nowayout, bool, 0); | |
740fbddf | 70 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started." |
15e28bf1 PG |
71 | " (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); |
72 | ||
73 | /* | |
74 | * Some TCO specific functions | |
75 | */ | |
76 | static void tco_timer_start(void) | |
77 | { | |
78 | u32 val; | |
79 | unsigned long flags; | |
80 | ||
81 | spin_lock_irqsave(&tco_lock, flags); | |
82 | val = readl(SP5100_WDT_CONTROL(tcobase)); | |
83 | val |= SP5100_WDT_START_STOP_BIT; | |
84 | writel(val, SP5100_WDT_CONTROL(tcobase)); | |
85 | spin_unlock_irqrestore(&tco_lock, flags); | |
86 | } | |
87 | ||
88 | static void tco_timer_stop(void) | |
89 | { | |
90 | u32 val; | |
91 | unsigned long flags; | |
92 | ||
93 | spin_lock_irqsave(&tco_lock, flags); | |
94 | val = readl(SP5100_WDT_CONTROL(tcobase)); | |
95 | val &= ~SP5100_WDT_START_STOP_BIT; | |
96 | writel(val, SP5100_WDT_CONTROL(tcobase)); | |
97 | spin_unlock_irqrestore(&tco_lock, flags); | |
98 | } | |
99 | ||
100 | static void tco_timer_keepalive(void) | |
101 | { | |
102 | u32 val; | |
103 | unsigned long flags; | |
104 | ||
105 | spin_lock_irqsave(&tco_lock, flags); | |
106 | val = readl(SP5100_WDT_CONTROL(tcobase)); | |
107 | val |= SP5100_WDT_TRIGGER_BIT; | |
108 | writel(val, SP5100_WDT_CONTROL(tcobase)); | |
109 | spin_unlock_irqrestore(&tco_lock, flags); | |
110 | } | |
111 | ||
112 | static int tco_timer_set_heartbeat(int t) | |
113 | { | |
114 | unsigned long flags; | |
115 | ||
116 | if (t < 0 || t > 0xffff) | |
117 | return -EINVAL; | |
118 | ||
119 | /* Write new heartbeat to watchdog */ | |
120 | spin_lock_irqsave(&tco_lock, flags); | |
121 | writel(t, SP5100_WDT_COUNT(tcobase)); | |
122 | spin_unlock_irqrestore(&tco_lock, flags); | |
123 | ||
124 | heartbeat = t; | |
125 | return 0; | |
126 | } | |
127 | ||
740fbddf TT |
128 | static void tco_timer_enable(void) |
129 | { | |
130 | int val; | |
131 | ||
132 | if (sp5100_tco_pci->revision >= 0x40) { | |
133 | /* For SB800 or later */ | |
134 | /* Set the Watchdog timer resolution to 1 sec */ | |
135 | outb(SB800_PM_WATCHDOG_CONFIG, SB800_IO_PM_INDEX_REG); | |
136 | val = inb(SB800_IO_PM_DATA_REG); | |
137 | val |= SB800_PM_WATCHDOG_SECOND_RES; | |
138 | outb(val, SB800_IO_PM_DATA_REG); | |
139 | ||
140 | /* Enable watchdog decode bit and watchdog timer */ | |
141 | outb(SB800_PM_WATCHDOG_CONTROL, SB800_IO_PM_INDEX_REG); | |
142 | val = inb(SB800_IO_PM_DATA_REG); | |
143 | val |= SB800_PCI_WATCHDOG_DECODE_EN; | |
144 | val &= ~SB800_PM_WATCHDOG_DISABLE; | |
145 | outb(val, SB800_IO_PM_DATA_REG); | |
146 | } else { | |
147 | /* For SP5100 or SB7x0 */ | |
148 | /* Enable watchdog decode bit */ | |
149 | pci_read_config_dword(sp5100_tco_pci, | |
150 | SP5100_PCI_WATCHDOG_MISC_REG, | |
151 | &val); | |
152 | ||
153 | val |= SP5100_PCI_WATCHDOG_DECODE_EN; | |
154 | ||
155 | pci_write_config_dword(sp5100_tco_pci, | |
156 | SP5100_PCI_WATCHDOG_MISC_REG, | |
157 | val); | |
158 | ||
159 | /* Enable Watchdog timer and set the resolution to 1 sec */ | |
160 | outb(SP5100_PM_WATCHDOG_CONTROL, SP5100_IO_PM_INDEX_REG); | |
161 | val = inb(SP5100_IO_PM_DATA_REG); | |
162 | val |= SP5100_PM_WATCHDOG_SECOND_RES; | |
163 | val &= ~SP5100_PM_WATCHDOG_DISABLE; | |
164 | outb(val, SP5100_IO_PM_DATA_REG); | |
165 | } | |
166 | } | |
167 | ||
15e28bf1 PG |
168 | /* |
169 | * /dev/watchdog handling | |
170 | */ | |
171 | ||
172 | static int sp5100_tco_open(struct inode *inode, struct file *file) | |
173 | { | |
174 | /* /dev/watchdog can only be opened once */ | |
175 | if (test_and_set_bit(0, &timer_alive)) | |
176 | return -EBUSY; | |
177 | ||
178 | /* Reload and activate timer */ | |
179 | tco_timer_start(); | |
180 | tco_timer_keepalive(); | |
181 | return nonseekable_open(inode, file); | |
182 | } | |
183 | ||
184 | static int sp5100_tco_release(struct inode *inode, struct file *file) | |
185 | { | |
186 | /* Shut off the timer. */ | |
187 | if (tco_expect_close == 42) { | |
188 | tco_timer_stop(); | |
189 | } else { | |
27c766aa | 190 | pr_crit("Unexpected close, not stopping watchdog!\n"); |
15e28bf1 PG |
191 | tco_timer_keepalive(); |
192 | } | |
193 | clear_bit(0, &timer_alive); | |
194 | tco_expect_close = 0; | |
195 | return 0; | |
196 | } | |
197 | ||
198 | static ssize_t sp5100_tco_write(struct file *file, const char __user *data, | |
199 | size_t len, loff_t *ppos) | |
200 | { | |
201 | /* See if we got the magic character 'V' and reload the timer */ | |
202 | if (len) { | |
203 | if (!nowayout) { | |
204 | size_t i; | |
205 | ||
206 | /* note: just in case someone wrote the magic character | |
207 | * five months ago... */ | |
208 | tco_expect_close = 0; | |
209 | ||
210 | /* scan to see whether or not we got the magic character | |
211 | */ | |
212 | for (i = 0; i != len; i++) { | |
213 | char c; | |
214 | if (get_user(c, data + i)) | |
215 | return -EFAULT; | |
216 | if (c == 'V') | |
217 | tco_expect_close = 42; | |
218 | } | |
219 | } | |
220 | ||
221 | /* someone wrote to us, we should reload the timer */ | |
222 | tco_timer_keepalive(); | |
223 | } | |
224 | return len; | |
225 | } | |
226 | ||
227 | static long sp5100_tco_ioctl(struct file *file, unsigned int cmd, | |
228 | unsigned long arg) | |
229 | { | |
230 | int new_options, retval = -EINVAL; | |
231 | int new_heartbeat; | |
232 | void __user *argp = (void __user *)arg; | |
233 | int __user *p = argp; | |
234 | static const struct watchdog_info ident = { | |
235 | .options = WDIOF_SETTIMEOUT | | |
236 | WDIOF_KEEPALIVEPING | | |
237 | WDIOF_MAGICCLOSE, | |
238 | .firmware_version = 0, | |
239 | .identity = TCO_MODULE_NAME, | |
240 | }; | |
241 | ||
242 | switch (cmd) { | |
243 | case WDIOC_GETSUPPORT: | |
244 | return copy_to_user(argp, &ident, | |
245 | sizeof(ident)) ? -EFAULT : 0; | |
246 | case WDIOC_GETSTATUS: | |
247 | case WDIOC_GETBOOTSTATUS: | |
248 | return put_user(0, p); | |
249 | case WDIOC_SETOPTIONS: | |
250 | if (get_user(new_options, p)) | |
251 | return -EFAULT; | |
252 | if (new_options & WDIOS_DISABLECARD) { | |
253 | tco_timer_stop(); | |
254 | retval = 0; | |
255 | } | |
256 | if (new_options & WDIOS_ENABLECARD) { | |
257 | tco_timer_start(); | |
258 | tco_timer_keepalive(); | |
259 | retval = 0; | |
260 | } | |
261 | return retval; | |
262 | case WDIOC_KEEPALIVE: | |
263 | tco_timer_keepalive(); | |
264 | return 0; | |
265 | case WDIOC_SETTIMEOUT: | |
266 | if (get_user(new_heartbeat, p)) | |
267 | return -EFAULT; | |
268 | if (tco_timer_set_heartbeat(new_heartbeat)) | |
269 | return -EINVAL; | |
270 | tco_timer_keepalive(); | |
271 | /* Fall through */ | |
272 | case WDIOC_GETTIMEOUT: | |
273 | return put_user(heartbeat, p); | |
274 | default: | |
275 | return -ENOTTY; | |
276 | } | |
277 | } | |
278 | ||
279 | /* | |
280 | * Kernel Interfaces | |
281 | */ | |
282 | ||
283 | static const struct file_operations sp5100_tco_fops = { | |
284 | .owner = THIS_MODULE, | |
285 | .llseek = no_llseek, | |
286 | .write = sp5100_tco_write, | |
287 | .unlocked_ioctl = sp5100_tco_ioctl, | |
288 | .open = sp5100_tco_open, | |
289 | .release = sp5100_tco_release, | |
290 | }; | |
291 | ||
292 | static struct miscdevice sp5100_tco_miscdev = { | |
293 | .minor = WATCHDOG_MINOR, | |
294 | .name = "watchdog", | |
295 | .fops = &sp5100_tco_fops, | |
296 | }; | |
297 | ||
298 | /* | |
299 | * Data for PCI driver interface | |
300 | * | |
301 | * This data only exists for exporting the supported | |
302 | * PCI ids via MODULE_DEVICE_TABLE. We do not actually | |
303 | * register a pci_driver, because someone else might | |
304 | * want to register another driver on the same PCI id. | |
305 | */ | |
4562f539 | 306 | static DEFINE_PCI_DEVICE_TABLE(sp5100_tco_pci_tbl) = { |
15e28bf1 PG |
307 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, PCI_ANY_ID, |
308 | PCI_ANY_ID, }, | |
309 | { 0, }, /* End of list */ | |
310 | }; | |
311 | MODULE_DEVICE_TABLE(pci, sp5100_tco_pci_tbl); | |
312 | ||
313 | /* | |
314 | * Init & exit routines | |
315 | */ | |
2d991a16 | 316 | static unsigned char sp5100_tco_setupdevice(void) |
15e28bf1 PG |
317 | { |
318 | struct pci_dev *dev = NULL; | |
740fbddf | 319 | const char *dev_name = NULL; |
18e43212 | 320 | u32 val; |
740fbddf | 321 | u32 index_reg, data_reg, base_addr; |
15e28bf1 PG |
322 | |
323 | /* Match the PCI device */ | |
324 | for_each_pci_dev(dev) { | |
325 | if (pci_match_id(sp5100_tco_pci_tbl, dev) != NULL) { | |
326 | sp5100_tco_pci = dev; | |
327 | break; | |
328 | } | |
329 | } | |
330 | ||
331 | if (!sp5100_tco_pci) | |
332 | return 0; | |
333 | ||
740fbddf TT |
334 | pr_info("PCI Revision ID: 0x%x\n", sp5100_tco_pci->revision); |
335 | ||
336 | /* | |
337 | * Determine type of southbridge chipset. | |
338 | */ | |
339 | if (sp5100_tco_pci->revision >= 0x40) { | |
340 | dev_name = SB800_DEVNAME; | |
341 | index_reg = SB800_IO_PM_INDEX_REG; | |
342 | data_reg = SB800_IO_PM_DATA_REG; | |
343 | base_addr = SB800_PM_WATCHDOG_BASE; | |
344 | } else { | |
345 | dev_name = SP5100_DEVNAME; | |
346 | index_reg = SP5100_IO_PM_INDEX_REG; | |
347 | data_reg = SP5100_IO_PM_DATA_REG; | |
348 | base_addr = SP5100_PM_WATCHDOG_BASE; | |
349 | } | |
350 | ||
15e28bf1 PG |
351 | /* Request the IO ports used by this driver */ |
352 | pm_iobase = SP5100_IO_PM_INDEX_REG; | |
740fbddf | 353 | if (!request_region(pm_iobase, SP5100_PM_IOPORTS_SIZE, dev_name)) { |
27c766aa | 354 | pr_err("I/O address 0x%04x already in use\n", pm_iobase); |
15e28bf1 PG |
355 | goto exit; |
356 | } | |
357 | ||
740fbddf TT |
358 | /* |
359 | * First, Find the watchdog timer MMIO address from indirect I/O. | |
360 | */ | |
361 | outb(base_addr+3, index_reg); | |
362 | val = inb(data_reg); | |
363 | outb(base_addr+2, index_reg); | |
364 | val = val << 8 | inb(data_reg); | |
365 | outb(base_addr+1, index_reg); | |
366 | val = val << 8 | inb(data_reg); | |
367 | outb(base_addr+0, index_reg); | |
368 | /* Low three bits of BASE are reserved */ | |
369 | val = val << 8 | (inb(data_reg) & 0xf8); | |
370 | ||
371 | pr_debug("Got 0x%04x from indirect I/O\n", val); | |
372 | ||
373 | /* Check MMIO address conflict */ | |
374 | if (request_mem_region_exclusive(val, SP5100_WDT_MEM_MAP_SIZE, | |
375 | dev_name)) | |
376 | goto setup_wdt; | |
377 | else | |
378 | pr_debug("MMIO address 0x%04x already in use\n", val); | |
379 | ||
380 | /* | |
381 | * Secondly, Find the watchdog timer MMIO address | |
382 | * from SBResource_MMIO register. | |
383 | */ | |
384 | if (sp5100_tco_pci->revision >= 0x40) { | |
385 | /* Read SBResource_MMIO from AcpiMmioEn(PM_Reg: 24h) */ | |
386 | outb(SB800_PM_ACPI_MMIO_EN+3, SB800_IO_PM_INDEX_REG); | |
387 | val = inb(SB800_IO_PM_DATA_REG); | |
388 | outb(SB800_PM_ACPI_MMIO_EN+2, SB800_IO_PM_INDEX_REG); | |
389 | val = val << 8 | inb(SB800_IO_PM_DATA_REG); | |
390 | outb(SB800_PM_ACPI_MMIO_EN+1, SB800_IO_PM_INDEX_REG); | |
391 | val = val << 8 | inb(SB800_IO_PM_DATA_REG); | |
392 | outb(SB800_PM_ACPI_MMIO_EN+0, SB800_IO_PM_INDEX_REG); | |
393 | val = val << 8 | inb(SB800_IO_PM_DATA_REG); | |
394 | } else { | |
395 | /* Read SBResource_MMIO from PCI config(PCI_Reg: 9Ch) */ | |
396 | pci_read_config_dword(sp5100_tco_pci, | |
397 | SP5100_SB_RESOURCE_MMIO_BASE, &val); | |
398 | } | |
399 | ||
400 | /* The SBResource_MMIO is enabled and mapped memory space? */ | |
401 | if ((val & (SB800_ACPI_MMIO_DECODE_EN | SB800_ACPI_MMIO_SEL)) == | |
402 | SB800_ACPI_MMIO_DECODE_EN) { | |
403 | /* Clear unnecessary the low twelve bits */ | |
404 | val &= ~0xFFF; | |
405 | /* Add the Watchdog Timer offset to base address. */ | |
406 | val += SB800_PM_WDT_MMIO_OFFSET; | |
407 | /* Check MMIO address conflict */ | |
408 | if (request_mem_region_exclusive(val, SP5100_WDT_MEM_MAP_SIZE, | |
409 | dev_name)) { | |
410 | pr_debug("Got 0x%04x from SBResource_MMIO register\n", | |
411 | val); | |
412 | goto setup_wdt; | |
413 | } else | |
414 | pr_debug("MMIO address 0x%04x already in use\n", val); | |
415 | } else | |
416 | pr_debug("SBResource_MMIO is disabled(0x%04x)\n", val); | |
417 | ||
18e43212 TT |
418 | pr_notice("failed to find MMIO address, giving up.\n"); |
419 | goto unreg_region; | |
740fbddf TT |
420 | |
421 | setup_wdt: | |
90d241ed YL |
422 | tcobase_phys = val; |
423 | ||
15e28bf1 | 424 | tcobase = ioremap(val, SP5100_WDT_MEM_MAP_SIZE); |
62a9aebc | 425 | if (!tcobase) { |
27c766aa | 426 | pr_err("failed to get tcobase address\n"); |
90d241ed | 427 | goto unreg_mem_region; |
15e28bf1 PG |
428 | } |
429 | ||
740fbddf | 430 | pr_info("Using 0x%04x for watchdog MMIO address\n", val); |
15e28bf1 | 431 | |
740fbddf TT |
432 | /* Setup the watchdog timer */ |
433 | tco_timer_enable(); | |
15e28bf1 | 434 | |
740fbddf | 435 | /* Check that the watchdog action is set to reset the system */ |
15e28bf1 | 436 | val = readl(SP5100_WDT_CONTROL(tcobase)); |
740fbddf TT |
437 | /* |
438 | * Save WatchDogFired status, because WatchDogFired flag is | |
439 | * cleared here. | |
440 | */ | |
441 | tco_wdt_fired = val & SP5100_PM_WATCHDOG_FIRED; | |
15e28bf1 PG |
442 | val &= ~SP5100_PM_WATCHDOG_ACTION_RESET; |
443 | writel(val, SP5100_WDT_CONTROL(tcobase)); | |
444 | ||
445 | /* Set a reasonable heartbeat before we stop the timer */ | |
446 | tco_timer_set_heartbeat(heartbeat); | |
447 | ||
448 | /* | |
449 | * Stop the TCO before we change anything so we don't race with | |
450 | * a zeroed timer. | |
451 | */ | |
452 | tco_timer_stop(); | |
453 | ||
454 | /* Done */ | |
455 | return 1; | |
456 | ||
90d241ed YL |
457 | unreg_mem_region: |
458 | release_mem_region(tcobase_phys, SP5100_WDT_MEM_MAP_SIZE); | |
15e28bf1 PG |
459 | unreg_region: |
460 | release_region(pm_iobase, SP5100_PM_IOPORTS_SIZE); | |
461 | exit: | |
462 | return 0; | |
463 | } | |
464 | ||
2d991a16 | 465 | static int sp5100_tco_init(struct platform_device *dev) |
15e28bf1 PG |
466 | { |
467 | int ret; | |
15e28bf1 | 468 | |
740fbddf TT |
469 | /* |
470 | * Check whether or not the hardware watchdog is there. If found, then | |
15e28bf1 PG |
471 | * set it up. |
472 | */ | |
473 | if (!sp5100_tco_setupdevice()) | |
474 | return -ENODEV; | |
475 | ||
476 | /* Check to see if last reboot was due to watchdog timeout */ | |
740fbddf TT |
477 | pr_info("Last reboot was %striggered by watchdog.\n", |
478 | tco_wdt_fired ? "" : "not "); | |
15e28bf1 PG |
479 | |
480 | /* | |
481 | * Check that the heartbeat value is within it's range. | |
482 | * If not, reset to the default. | |
483 | */ | |
484 | if (tco_timer_set_heartbeat(heartbeat)) { | |
485 | heartbeat = WATCHDOG_HEARTBEAT; | |
486 | tco_timer_set_heartbeat(heartbeat); | |
487 | } | |
488 | ||
489 | ret = misc_register(&sp5100_tco_miscdev); | |
490 | if (ret != 0) { | |
27c766aa | 491 | pr_err("cannot register miscdev on minor=%d (err=%d)\n", |
15e28bf1 PG |
492 | WATCHDOG_MINOR, ret); |
493 | goto exit; | |
494 | } | |
495 | ||
496 | clear_bit(0, &timer_alive); | |
497 | ||
740fbddf | 498 | /* Show module parameters */ |
18e43212 TT |
499 | pr_info("initialized (0x%p). heartbeat=%d sec (nowayout=%d)\n", |
500 | tcobase, heartbeat, nowayout); | |
15e28bf1 PG |
501 | |
502 | return 0; | |
503 | ||
504 | exit: | |
505 | iounmap(tcobase); | |
90d241ed | 506 | release_mem_region(tcobase_phys, SP5100_WDT_MEM_MAP_SIZE); |
15e28bf1 PG |
507 | release_region(pm_iobase, SP5100_PM_IOPORTS_SIZE); |
508 | return ret; | |
509 | } | |
510 | ||
4b12b896 | 511 | static void sp5100_tco_cleanup(void) |
15e28bf1 PG |
512 | { |
513 | /* Stop the timer before we leave */ | |
514 | if (!nowayout) | |
515 | tco_timer_stop(); | |
516 | ||
517 | /* Deregister */ | |
518 | misc_deregister(&sp5100_tco_miscdev); | |
519 | iounmap(tcobase); | |
90d241ed | 520 | release_mem_region(tcobase_phys, SP5100_WDT_MEM_MAP_SIZE); |
15e28bf1 PG |
521 | release_region(pm_iobase, SP5100_PM_IOPORTS_SIZE); |
522 | } | |
523 | ||
4b12b896 | 524 | static int sp5100_tco_remove(struct platform_device *dev) |
15e28bf1 PG |
525 | { |
526 | if (tcobase) | |
527 | sp5100_tco_cleanup(); | |
528 | return 0; | |
529 | } | |
530 | ||
531 | static void sp5100_tco_shutdown(struct platform_device *dev) | |
532 | { | |
533 | tco_timer_stop(); | |
534 | } | |
535 | ||
536 | static struct platform_driver sp5100_tco_driver = { | |
537 | .probe = sp5100_tco_init, | |
82268714 | 538 | .remove = sp5100_tco_remove, |
15e28bf1 PG |
539 | .shutdown = sp5100_tco_shutdown, |
540 | .driver = { | |
541 | .owner = THIS_MODULE, | |
542 | .name = TCO_MODULE_NAME, | |
543 | }, | |
544 | }; | |
545 | ||
546 | static int __init sp5100_tco_init_module(void) | |
547 | { | |
548 | int err; | |
549 | ||
740fbddf | 550 | pr_info("SP5100/SB800 TCO WatchDog Timer Driver v%s\n", TCO_VERSION); |
15e28bf1 PG |
551 | |
552 | err = platform_driver_register(&sp5100_tco_driver); | |
553 | if (err) | |
554 | return err; | |
555 | ||
556 | sp5100_tco_platform_device = platform_device_register_simple( | |
557 | TCO_MODULE_NAME, -1, NULL, 0); | |
558 | if (IS_ERR(sp5100_tco_platform_device)) { | |
559 | err = PTR_ERR(sp5100_tco_platform_device); | |
560 | goto unreg_platform_driver; | |
561 | } | |
562 | ||
563 | return 0; | |
564 | ||
565 | unreg_platform_driver: | |
566 | platform_driver_unregister(&sp5100_tco_driver); | |
567 | return err; | |
568 | } | |
569 | ||
570 | static void __exit sp5100_tco_cleanup_module(void) | |
571 | { | |
572 | platform_device_unregister(sp5100_tco_platform_device); | |
573 | platform_driver_unregister(&sp5100_tco_driver); | |
740fbddf | 574 | pr_info("SP5100/SB800 TCO Watchdog Module Unloaded\n"); |
15e28bf1 PG |
575 | } |
576 | ||
577 | module_init(sp5100_tco_init_module); | |
578 | module_exit(sp5100_tco_cleanup_module); | |
579 | ||
580 | MODULE_AUTHOR("Priyanka Gupta"); | |
740fbddf | 581 | MODULE_DESCRIPTION("TCO timer driver for SP5100/SB800 chipset"); |
15e28bf1 PG |
582 | MODULE_LICENSE("GPL"); |
583 | MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); |