Commit | Line | Data |
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15e28bf1 PG |
1 | /* |
2 | * sp5100_tco : TCO timer driver for sp5100 chipsets | |
3 | * | |
4 | * (c) Copyright 2009 Google Inc., All Rights Reserved. | |
5 | * | |
6 | * Based on i8xx_tco.c: | |
7 | * (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights | |
8 | * Reserved. | |
9 | * http://www.kernelconcepts.de | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License | |
13 | * as published by the Free Software Foundation; either version | |
14 | * 2 of the License, or (at your option) any later version. | |
15 | * | |
16 | * See AMD Publication 43009 "AMD SB700/710/750 Register Reference Guide" | |
17 | */ | |
18 | ||
19 | /* | |
20 | * Includes, defines, variables, module parameters, ... | |
21 | */ | |
22 | ||
27c766aa JP |
23 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
24 | ||
15e28bf1 PG |
25 | #include <linux/module.h> |
26 | #include <linux/moduleparam.h> | |
27 | #include <linux/types.h> | |
28 | #include <linux/miscdevice.h> | |
29 | #include <linux/watchdog.h> | |
30 | #include <linux/init.h> | |
31 | #include <linux/fs.h> | |
32 | #include <linux/pci.h> | |
33 | #include <linux/ioport.h> | |
34 | #include <linux/platform_device.h> | |
35 | #include <linux/uaccess.h> | |
36 | #include <linux/io.h> | |
37 | ||
38 | #include "sp5100_tco.h" | |
39 | ||
40 | /* Module and version information */ | |
41 | #define TCO_VERSION "0.01" | |
42 | #define TCO_MODULE_NAME "SP5100 TCO timer" | |
43 | #define TCO_DRIVER_NAME TCO_MODULE_NAME ", v" TCO_VERSION | |
15e28bf1 PG |
44 | |
45 | /* internal variables */ | |
90d241ed | 46 | static u32 tcobase_phys; |
15e28bf1 PG |
47 | static void __iomem *tcobase; |
48 | static unsigned int pm_iobase; | |
49 | static DEFINE_SPINLOCK(tco_lock); /* Guards the hardware */ | |
50 | static unsigned long timer_alive; | |
51 | static char tco_expect_close; | |
52 | static struct pci_dev *sp5100_tco_pci; | |
53 | ||
54 | /* the watchdog platform device */ | |
55 | static struct platform_device *sp5100_tco_platform_device; | |
56 | ||
57 | /* module parameters */ | |
58 | ||
59 | #define WATCHDOG_HEARTBEAT 60 /* 60 sec default heartbeat. */ | |
60 | static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */ | |
61 | module_param(heartbeat, int, 0); | |
62 | MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (default=" | |
63 | __MODULE_STRING(WATCHDOG_HEARTBEAT) ")"); | |
64 | ||
86a1e189 WVS |
65 | static bool nowayout = WATCHDOG_NOWAYOUT; |
66 | module_param(nowayout, bool, 0); | |
15e28bf1 PG |
67 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started" |
68 | " (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
69 | ||
70 | /* | |
71 | * Some TCO specific functions | |
72 | */ | |
73 | static void tco_timer_start(void) | |
74 | { | |
75 | u32 val; | |
76 | unsigned long flags; | |
77 | ||
78 | spin_lock_irqsave(&tco_lock, flags); | |
79 | val = readl(SP5100_WDT_CONTROL(tcobase)); | |
80 | val |= SP5100_WDT_START_STOP_BIT; | |
81 | writel(val, SP5100_WDT_CONTROL(tcobase)); | |
82 | spin_unlock_irqrestore(&tco_lock, flags); | |
83 | } | |
84 | ||
85 | static void tco_timer_stop(void) | |
86 | { | |
87 | u32 val; | |
88 | unsigned long flags; | |
89 | ||
90 | spin_lock_irqsave(&tco_lock, flags); | |
91 | val = readl(SP5100_WDT_CONTROL(tcobase)); | |
92 | val &= ~SP5100_WDT_START_STOP_BIT; | |
93 | writel(val, SP5100_WDT_CONTROL(tcobase)); | |
94 | spin_unlock_irqrestore(&tco_lock, flags); | |
95 | } | |
96 | ||
97 | static void tco_timer_keepalive(void) | |
98 | { | |
99 | u32 val; | |
100 | unsigned long flags; | |
101 | ||
102 | spin_lock_irqsave(&tco_lock, flags); | |
103 | val = readl(SP5100_WDT_CONTROL(tcobase)); | |
104 | val |= SP5100_WDT_TRIGGER_BIT; | |
105 | writel(val, SP5100_WDT_CONTROL(tcobase)); | |
106 | spin_unlock_irqrestore(&tco_lock, flags); | |
107 | } | |
108 | ||
109 | static int tco_timer_set_heartbeat(int t) | |
110 | { | |
111 | unsigned long flags; | |
112 | ||
113 | if (t < 0 || t > 0xffff) | |
114 | return -EINVAL; | |
115 | ||
116 | /* Write new heartbeat to watchdog */ | |
117 | spin_lock_irqsave(&tco_lock, flags); | |
118 | writel(t, SP5100_WDT_COUNT(tcobase)); | |
119 | spin_unlock_irqrestore(&tco_lock, flags); | |
120 | ||
121 | heartbeat = t; | |
122 | return 0; | |
123 | } | |
124 | ||
125 | /* | |
126 | * /dev/watchdog handling | |
127 | */ | |
128 | ||
129 | static int sp5100_tco_open(struct inode *inode, struct file *file) | |
130 | { | |
131 | /* /dev/watchdog can only be opened once */ | |
132 | if (test_and_set_bit(0, &timer_alive)) | |
133 | return -EBUSY; | |
134 | ||
135 | /* Reload and activate timer */ | |
136 | tco_timer_start(); | |
137 | tco_timer_keepalive(); | |
138 | return nonseekable_open(inode, file); | |
139 | } | |
140 | ||
141 | static int sp5100_tco_release(struct inode *inode, struct file *file) | |
142 | { | |
143 | /* Shut off the timer. */ | |
144 | if (tco_expect_close == 42) { | |
145 | tco_timer_stop(); | |
146 | } else { | |
27c766aa | 147 | pr_crit("Unexpected close, not stopping watchdog!\n"); |
15e28bf1 PG |
148 | tco_timer_keepalive(); |
149 | } | |
150 | clear_bit(0, &timer_alive); | |
151 | tco_expect_close = 0; | |
152 | return 0; | |
153 | } | |
154 | ||
155 | static ssize_t sp5100_tco_write(struct file *file, const char __user *data, | |
156 | size_t len, loff_t *ppos) | |
157 | { | |
158 | /* See if we got the magic character 'V' and reload the timer */ | |
159 | if (len) { | |
160 | if (!nowayout) { | |
161 | size_t i; | |
162 | ||
163 | /* note: just in case someone wrote the magic character | |
164 | * five months ago... */ | |
165 | tco_expect_close = 0; | |
166 | ||
167 | /* scan to see whether or not we got the magic character | |
168 | */ | |
169 | for (i = 0; i != len; i++) { | |
170 | char c; | |
171 | if (get_user(c, data + i)) | |
172 | return -EFAULT; | |
173 | if (c == 'V') | |
174 | tco_expect_close = 42; | |
175 | } | |
176 | } | |
177 | ||
178 | /* someone wrote to us, we should reload the timer */ | |
179 | tco_timer_keepalive(); | |
180 | } | |
181 | return len; | |
182 | } | |
183 | ||
184 | static long sp5100_tco_ioctl(struct file *file, unsigned int cmd, | |
185 | unsigned long arg) | |
186 | { | |
187 | int new_options, retval = -EINVAL; | |
188 | int new_heartbeat; | |
189 | void __user *argp = (void __user *)arg; | |
190 | int __user *p = argp; | |
191 | static const struct watchdog_info ident = { | |
192 | .options = WDIOF_SETTIMEOUT | | |
193 | WDIOF_KEEPALIVEPING | | |
194 | WDIOF_MAGICCLOSE, | |
195 | .firmware_version = 0, | |
196 | .identity = TCO_MODULE_NAME, | |
197 | }; | |
198 | ||
199 | switch (cmd) { | |
200 | case WDIOC_GETSUPPORT: | |
201 | return copy_to_user(argp, &ident, | |
202 | sizeof(ident)) ? -EFAULT : 0; | |
203 | case WDIOC_GETSTATUS: | |
204 | case WDIOC_GETBOOTSTATUS: | |
205 | return put_user(0, p); | |
206 | case WDIOC_SETOPTIONS: | |
207 | if (get_user(new_options, p)) | |
208 | return -EFAULT; | |
209 | if (new_options & WDIOS_DISABLECARD) { | |
210 | tco_timer_stop(); | |
211 | retval = 0; | |
212 | } | |
213 | if (new_options & WDIOS_ENABLECARD) { | |
214 | tco_timer_start(); | |
215 | tco_timer_keepalive(); | |
216 | retval = 0; | |
217 | } | |
218 | return retval; | |
219 | case WDIOC_KEEPALIVE: | |
220 | tco_timer_keepalive(); | |
221 | return 0; | |
222 | case WDIOC_SETTIMEOUT: | |
223 | if (get_user(new_heartbeat, p)) | |
224 | return -EFAULT; | |
225 | if (tco_timer_set_heartbeat(new_heartbeat)) | |
226 | return -EINVAL; | |
227 | tco_timer_keepalive(); | |
228 | /* Fall through */ | |
229 | case WDIOC_GETTIMEOUT: | |
230 | return put_user(heartbeat, p); | |
231 | default: | |
232 | return -ENOTTY; | |
233 | } | |
234 | } | |
235 | ||
236 | /* | |
237 | * Kernel Interfaces | |
238 | */ | |
239 | ||
240 | static const struct file_operations sp5100_tco_fops = { | |
241 | .owner = THIS_MODULE, | |
242 | .llseek = no_llseek, | |
243 | .write = sp5100_tco_write, | |
244 | .unlocked_ioctl = sp5100_tco_ioctl, | |
245 | .open = sp5100_tco_open, | |
246 | .release = sp5100_tco_release, | |
247 | }; | |
248 | ||
249 | static struct miscdevice sp5100_tco_miscdev = { | |
250 | .minor = WATCHDOG_MINOR, | |
251 | .name = "watchdog", | |
252 | .fops = &sp5100_tco_fops, | |
253 | }; | |
254 | ||
255 | /* | |
256 | * Data for PCI driver interface | |
257 | * | |
258 | * This data only exists for exporting the supported | |
259 | * PCI ids via MODULE_DEVICE_TABLE. We do not actually | |
260 | * register a pci_driver, because someone else might | |
261 | * want to register another driver on the same PCI id. | |
262 | */ | |
4562f539 | 263 | static DEFINE_PCI_DEVICE_TABLE(sp5100_tco_pci_tbl) = { |
15e28bf1 PG |
264 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, PCI_ANY_ID, |
265 | PCI_ANY_ID, }, | |
266 | { 0, }, /* End of list */ | |
267 | }; | |
268 | MODULE_DEVICE_TABLE(pci, sp5100_tco_pci_tbl); | |
269 | ||
270 | /* | |
271 | * Init & exit routines | |
272 | */ | |
273 | ||
2d991a16 | 274 | static unsigned char sp5100_tco_setupdevice(void) |
15e28bf1 PG |
275 | { |
276 | struct pci_dev *dev = NULL; | |
277 | u32 val; | |
278 | ||
279 | /* Match the PCI device */ | |
280 | for_each_pci_dev(dev) { | |
281 | if (pci_match_id(sp5100_tco_pci_tbl, dev) != NULL) { | |
282 | sp5100_tco_pci = dev; | |
283 | break; | |
284 | } | |
285 | } | |
286 | ||
287 | if (!sp5100_tco_pci) | |
288 | return 0; | |
289 | ||
290 | /* Request the IO ports used by this driver */ | |
291 | pm_iobase = SP5100_IO_PM_INDEX_REG; | |
292 | if (!request_region(pm_iobase, SP5100_PM_IOPORTS_SIZE, "SP5100 TCO")) { | |
27c766aa | 293 | pr_err("I/O address 0x%04x already in use\n", pm_iobase); |
15e28bf1 PG |
294 | goto exit; |
295 | } | |
296 | ||
297 | /* Find the watchdog base address. */ | |
298 | outb(SP5100_PM_WATCHDOG_BASE3, SP5100_IO_PM_INDEX_REG); | |
299 | val = inb(SP5100_IO_PM_DATA_REG); | |
300 | outb(SP5100_PM_WATCHDOG_BASE2, SP5100_IO_PM_INDEX_REG); | |
301 | val = val << 8 | inb(SP5100_IO_PM_DATA_REG); | |
302 | outb(SP5100_PM_WATCHDOG_BASE1, SP5100_IO_PM_INDEX_REG); | |
303 | val = val << 8 | inb(SP5100_IO_PM_DATA_REG); | |
304 | outb(SP5100_PM_WATCHDOG_BASE0, SP5100_IO_PM_INDEX_REG); | |
305 | /* Low three bits of BASE0 are reserved. */ | |
306 | val = val << 8 | (inb(SP5100_IO_PM_DATA_REG) & 0xf8); | |
307 | ||
90d241ed YL |
308 | if (!request_mem_region_exclusive(val, SP5100_WDT_MEM_MAP_SIZE, |
309 | "SP5100 TCO")) { | |
27c766aa | 310 | pr_err("mmio address 0x%04x already in use\n", val); |
90d241ed YL |
311 | goto unreg_region; |
312 | } | |
313 | tcobase_phys = val; | |
314 | ||
15e28bf1 | 315 | tcobase = ioremap(val, SP5100_WDT_MEM_MAP_SIZE); |
62a9aebc | 316 | if (!tcobase) { |
27c766aa | 317 | pr_err("failed to get tcobase address\n"); |
90d241ed | 318 | goto unreg_mem_region; |
15e28bf1 PG |
319 | } |
320 | ||
321 | /* Enable watchdog decode bit */ | |
322 | pci_read_config_dword(sp5100_tco_pci, | |
323 | SP5100_PCI_WATCHDOG_MISC_REG, | |
324 | &val); | |
325 | ||
326 | val |= SP5100_PCI_WATCHDOG_DECODE_EN; | |
327 | ||
328 | pci_write_config_dword(sp5100_tco_pci, | |
329 | SP5100_PCI_WATCHDOG_MISC_REG, | |
330 | val); | |
331 | ||
332 | /* Enable Watchdog timer and set the resolution to 1 sec. */ | |
333 | outb(SP5100_PM_WATCHDOG_CONTROL, SP5100_IO_PM_INDEX_REG); | |
334 | val = inb(SP5100_IO_PM_DATA_REG); | |
335 | val |= SP5100_PM_WATCHDOG_SECOND_RES; | |
336 | val &= ~SP5100_PM_WATCHDOG_DISABLE; | |
337 | outb(val, SP5100_IO_PM_DATA_REG); | |
338 | ||
339 | /* Check that the watchdog action is set to reset the system. */ | |
340 | val = readl(SP5100_WDT_CONTROL(tcobase)); | |
341 | val &= ~SP5100_PM_WATCHDOG_ACTION_RESET; | |
342 | writel(val, SP5100_WDT_CONTROL(tcobase)); | |
343 | ||
344 | /* Set a reasonable heartbeat before we stop the timer */ | |
345 | tco_timer_set_heartbeat(heartbeat); | |
346 | ||
347 | /* | |
348 | * Stop the TCO before we change anything so we don't race with | |
349 | * a zeroed timer. | |
350 | */ | |
351 | tco_timer_stop(); | |
352 | ||
353 | /* Done */ | |
354 | return 1; | |
355 | ||
90d241ed YL |
356 | unreg_mem_region: |
357 | release_mem_region(tcobase_phys, SP5100_WDT_MEM_MAP_SIZE); | |
15e28bf1 PG |
358 | unreg_region: |
359 | release_region(pm_iobase, SP5100_PM_IOPORTS_SIZE); | |
360 | exit: | |
361 | return 0; | |
362 | } | |
363 | ||
2d991a16 | 364 | static int sp5100_tco_init(struct platform_device *dev) |
15e28bf1 PG |
365 | { |
366 | int ret; | |
367 | u32 val; | |
368 | ||
369 | /* Check whether or not the hardware watchdog is there. If found, then | |
370 | * set it up. | |
371 | */ | |
372 | if (!sp5100_tco_setupdevice()) | |
373 | return -ENODEV; | |
374 | ||
375 | /* Check to see if last reboot was due to watchdog timeout */ | |
27c766aa JP |
376 | pr_info("Watchdog reboot %sdetected\n", |
377 | readl(SP5100_WDT_CONTROL(tcobase)) & SP5100_PM_WATCHDOG_FIRED ? | |
378 | "" : "not "); | |
15e28bf1 PG |
379 | |
380 | /* Clear out the old status */ | |
381 | val = readl(SP5100_WDT_CONTROL(tcobase)); | |
382 | val &= ~SP5100_PM_WATCHDOG_FIRED; | |
383 | writel(val, SP5100_WDT_CONTROL(tcobase)); | |
384 | ||
385 | /* | |
386 | * Check that the heartbeat value is within it's range. | |
387 | * If not, reset to the default. | |
388 | */ | |
389 | if (tco_timer_set_heartbeat(heartbeat)) { | |
390 | heartbeat = WATCHDOG_HEARTBEAT; | |
391 | tco_timer_set_heartbeat(heartbeat); | |
392 | } | |
393 | ||
394 | ret = misc_register(&sp5100_tco_miscdev); | |
395 | if (ret != 0) { | |
27c766aa | 396 | pr_err("cannot register miscdev on minor=%d (err=%d)\n", |
15e28bf1 PG |
397 | WATCHDOG_MINOR, ret); |
398 | goto exit; | |
399 | } | |
400 | ||
401 | clear_bit(0, &timer_alive); | |
402 | ||
27c766aa | 403 | pr_info("initialized (0x%p). heartbeat=%d sec (nowayout=%d)\n", |
15e28bf1 PG |
404 | tcobase, heartbeat, nowayout); |
405 | ||
406 | return 0; | |
407 | ||
408 | exit: | |
409 | iounmap(tcobase); | |
90d241ed | 410 | release_mem_region(tcobase_phys, SP5100_WDT_MEM_MAP_SIZE); |
15e28bf1 PG |
411 | release_region(pm_iobase, SP5100_PM_IOPORTS_SIZE); |
412 | return ret; | |
413 | } | |
414 | ||
4b12b896 | 415 | static void sp5100_tco_cleanup(void) |
15e28bf1 PG |
416 | { |
417 | /* Stop the timer before we leave */ | |
418 | if (!nowayout) | |
419 | tco_timer_stop(); | |
420 | ||
421 | /* Deregister */ | |
422 | misc_deregister(&sp5100_tco_miscdev); | |
423 | iounmap(tcobase); | |
90d241ed | 424 | release_mem_region(tcobase_phys, SP5100_WDT_MEM_MAP_SIZE); |
15e28bf1 PG |
425 | release_region(pm_iobase, SP5100_PM_IOPORTS_SIZE); |
426 | } | |
427 | ||
4b12b896 | 428 | static int sp5100_tco_remove(struct platform_device *dev) |
15e28bf1 PG |
429 | { |
430 | if (tcobase) | |
431 | sp5100_tco_cleanup(); | |
432 | return 0; | |
433 | } | |
434 | ||
435 | static void sp5100_tco_shutdown(struct platform_device *dev) | |
436 | { | |
437 | tco_timer_stop(); | |
438 | } | |
439 | ||
440 | static struct platform_driver sp5100_tco_driver = { | |
441 | .probe = sp5100_tco_init, | |
82268714 | 442 | .remove = sp5100_tco_remove, |
15e28bf1 PG |
443 | .shutdown = sp5100_tco_shutdown, |
444 | .driver = { | |
445 | .owner = THIS_MODULE, | |
446 | .name = TCO_MODULE_NAME, | |
447 | }, | |
448 | }; | |
449 | ||
450 | static int __init sp5100_tco_init_module(void) | |
451 | { | |
452 | int err; | |
453 | ||
27c766aa | 454 | pr_info("SP5100 TCO WatchDog Timer Driver v%s\n", TCO_VERSION); |
15e28bf1 PG |
455 | |
456 | err = platform_driver_register(&sp5100_tco_driver); | |
457 | if (err) | |
458 | return err; | |
459 | ||
460 | sp5100_tco_platform_device = platform_device_register_simple( | |
461 | TCO_MODULE_NAME, -1, NULL, 0); | |
462 | if (IS_ERR(sp5100_tco_platform_device)) { | |
463 | err = PTR_ERR(sp5100_tco_platform_device); | |
464 | goto unreg_platform_driver; | |
465 | } | |
466 | ||
467 | return 0; | |
468 | ||
469 | unreg_platform_driver: | |
470 | platform_driver_unregister(&sp5100_tco_driver); | |
471 | return err; | |
472 | } | |
473 | ||
474 | static void __exit sp5100_tco_cleanup_module(void) | |
475 | { | |
476 | platform_device_unregister(sp5100_tco_platform_device); | |
477 | platform_driver_unregister(&sp5100_tco_driver); | |
27c766aa | 478 | pr_info("SP5100 TCO Watchdog Module Unloaded\n"); |
15e28bf1 PG |
479 | } |
480 | ||
481 | module_init(sp5100_tco_init_module); | |
482 | module_exit(sp5100_tco_cleanup_module); | |
483 | ||
484 | MODULE_AUTHOR("Priyanka Gupta"); | |
485 | MODULE_DESCRIPTION("TCO timer driver for SP5100 chipset"); | |
486 | MODULE_LICENSE("GPL"); | |
487 | MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); |