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c33a1597 AC |
1 | /* |
2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/of.h> | |
19 | #include <linux/platform_device.h> | |
20 | #include <linux/watchdog.h> | |
21 | ||
22 | /* minimum and maximum watchdog trigger timeout, in seconds */ | |
23 | #define MIN_WDT_TIMEOUT 1 | |
24 | #define MAX_WDT_TIMEOUT 255 | |
25 | ||
26 | /* | |
27 | * Base of the WDT registers, from the timer base address. There are | |
28 | * actually 5 watchdogs that can be configured (by pairing with an available | |
29 | * timer), at bases 0x100 + (WDT ID) * 0x20, where WDT ID is 0 through 4. | |
30 | * This driver only configures the first watchdog (WDT ID 0). | |
31 | */ | |
32 | #define WDT_BASE 0x100 | |
33 | #define WDT_ID 0 | |
34 | ||
35 | /* | |
36 | * Register base of the timer that's selected for pairing with the watchdog. | |
37 | * This driver arbitrarily uses timer 5, which is currently unused by | |
38 | * other drivers (in particular, the Tegra clocksource driver). If this | |
39 | * needs to change, take care that the new timer is not used by the | |
40 | * clocksource driver. | |
41 | */ | |
42 | #define WDT_TIMER_BASE 0x60 | |
43 | #define WDT_TIMER_ID 5 | |
44 | ||
45 | /* WDT registers */ | |
46 | #define WDT_CFG 0x0 | |
47 | #define WDT_CFG_PERIOD_SHIFT 4 | |
48 | #define WDT_CFG_PERIOD_MASK 0xff | |
49 | #define WDT_CFG_INT_EN (1 << 12) | |
50 | #define WDT_CFG_PMC2CAR_RST_EN (1 << 15) | |
51 | #define WDT_STS 0x4 | |
52 | #define WDT_STS_COUNT_SHIFT 4 | |
53 | #define WDT_STS_COUNT_MASK 0xff | |
54 | #define WDT_STS_EXP_SHIFT 12 | |
55 | #define WDT_STS_EXP_MASK 0x3 | |
56 | #define WDT_CMD 0x8 | |
57 | #define WDT_CMD_START_COUNTER (1 << 0) | |
58 | #define WDT_CMD_DISABLE_COUNTER (1 << 1) | |
59 | #define WDT_UNLOCK (0xc) | |
60 | #define WDT_UNLOCK_PATTERN (0xc45a << 0) | |
61 | ||
62 | /* Timer registers */ | |
63 | #define TIMER_PTV 0x0 | |
64 | #define TIMER_EN (1 << 31) | |
65 | #define TIMER_PERIODIC (1 << 30) | |
66 | ||
67 | struct tegra_wdt { | |
68 | struct watchdog_device wdd; | |
69 | void __iomem *wdt_regs; | |
70 | void __iomem *tmr_regs; | |
71 | }; | |
72 | ||
73 | #define WDT_HEARTBEAT 120 | |
74 | static int heartbeat = WDT_HEARTBEAT; | |
75 | module_param(heartbeat, int, 0); | |
76 | MODULE_PARM_DESC(heartbeat, | |
77 | "Watchdog heartbeats in seconds. (default = " | |
78 | __MODULE_STRING(WDT_HEARTBEAT) ")"); | |
79 | ||
80 | static bool nowayout = WATCHDOG_NOWAYOUT; | |
81 | module_param(nowayout, bool, 0); | |
82 | MODULE_PARM_DESC(nowayout, | |
83 | "Watchdog cannot be stopped once started (default=" | |
84 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
85 | ||
86 | static int tegra_wdt_start(struct watchdog_device *wdd) | |
87 | { | |
88 | struct tegra_wdt *wdt = watchdog_get_drvdata(wdd); | |
89 | u32 val; | |
90 | ||
91 | /* | |
92 | * This thing has a fixed 1MHz clock. Normally, we would set the | |
93 | * period to 1 second by writing 1000000ul, but the watchdog system | |
94 | * reset actually occurs on the 4th expiration of this counter, | |
95 | * so we set the period to 1/4 of this amount. | |
96 | */ | |
97 | val = 1000000ul / 4; | |
98 | val |= (TIMER_EN | TIMER_PERIODIC); | |
99 | writel(val, wdt->tmr_regs + TIMER_PTV); | |
100 | ||
101 | /* | |
102 | * Set number of periods and start counter. | |
103 | * | |
104 | * Interrupt handler is not required for user space | |
105 | * WDT accesses, since the caller is responsible to ping the | |
106 | * WDT to reset the counter before expiration, through ioctls. | |
107 | */ | |
108 | val = WDT_TIMER_ID | | |
109 | (wdd->timeout << WDT_CFG_PERIOD_SHIFT) | | |
110 | WDT_CFG_PMC2CAR_RST_EN; | |
111 | writel(val, wdt->wdt_regs + WDT_CFG); | |
112 | ||
113 | writel(WDT_CMD_START_COUNTER, wdt->wdt_regs + WDT_CMD); | |
114 | ||
115 | return 0; | |
116 | } | |
117 | ||
118 | static int tegra_wdt_stop(struct watchdog_device *wdd) | |
119 | { | |
120 | struct tegra_wdt *wdt = watchdog_get_drvdata(wdd); | |
121 | ||
122 | writel(WDT_UNLOCK_PATTERN, wdt->wdt_regs + WDT_UNLOCK); | |
123 | writel(WDT_CMD_DISABLE_COUNTER, wdt->wdt_regs + WDT_CMD); | |
124 | writel(0, wdt->tmr_regs + TIMER_PTV); | |
125 | ||
126 | return 0; | |
127 | } | |
128 | ||
129 | static int tegra_wdt_ping(struct watchdog_device *wdd) | |
130 | { | |
131 | struct tegra_wdt *wdt = watchdog_get_drvdata(wdd); | |
132 | ||
133 | writel(WDT_CMD_START_COUNTER, wdt->wdt_regs + WDT_CMD); | |
134 | ||
135 | return 0; | |
136 | } | |
137 | ||
138 | static int tegra_wdt_set_timeout(struct watchdog_device *wdd, | |
139 | unsigned int timeout) | |
140 | { | |
141 | wdd->timeout = timeout; | |
142 | ||
0879eee1 AC |
143 | if (watchdog_active(wdd)) { |
144 | tegra_wdt_stop(wdd); | |
c33a1597 | 145 | return tegra_wdt_start(wdd); |
0879eee1 | 146 | } |
c33a1597 AC |
147 | |
148 | return 0; | |
149 | } | |
150 | ||
151 | static unsigned int tegra_wdt_get_timeleft(struct watchdog_device *wdd) | |
152 | { | |
153 | struct tegra_wdt *wdt = watchdog_get_drvdata(wdd); | |
154 | u32 val; | |
155 | int count; | |
156 | int exp; | |
157 | ||
158 | val = readl(wdt->wdt_regs + WDT_STS); | |
159 | ||
160 | /* Current countdown (from timeout) */ | |
161 | count = (val >> WDT_STS_COUNT_SHIFT) & WDT_STS_COUNT_MASK; | |
162 | ||
163 | /* Number of expirations (we are waiting for the 4th expiration) */ | |
164 | exp = (val >> WDT_STS_EXP_SHIFT) & WDT_STS_EXP_MASK; | |
165 | ||
166 | /* | |
167 | * The entire thing is divided by 4 because we are ticking down 4 times | |
168 | * faster due to needing to wait for the 4th expiration. | |
169 | */ | |
170 | return (((3 - exp) * wdd->timeout) + count) / 4; | |
171 | } | |
172 | ||
173 | static const struct watchdog_info tegra_wdt_info = { | |
174 | .options = WDIOF_SETTIMEOUT | | |
175 | WDIOF_MAGICCLOSE | | |
176 | WDIOF_KEEPALIVEPING, | |
177 | .firmware_version = 0, | |
178 | .identity = "Tegra Watchdog", | |
179 | }; | |
180 | ||
181 | static struct watchdog_ops tegra_wdt_ops = { | |
182 | .owner = THIS_MODULE, | |
183 | .start = tegra_wdt_start, | |
184 | .stop = tegra_wdt_stop, | |
185 | .ping = tegra_wdt_ping, | |
186 | .set_timeout = tegra_wdt_set_timeout, | |
187 | .get_timeleft = tegra_wdt_get_timeleft, | |
188 | }; | |
189 | ||
190 | static int tegra_wdt_probe(struct platform_device *pdev) | |
191 | { | |
192 | struct watchdog_device *wdd; | |
193 | struct tegra_wdt *wdt; | |
194 | struct resource *res; | |
195 | void __iomem *regs; | |
196 | int ret; | |
197 | ||
198 | /* This is the timer base. */ | |
199 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
200 | regs = devm_ioremap_resource(&pdev->dev, res); | |
201 | if (IS_ERR(regs)) | |
202 | return PTR_ERR(regs); | |
203 | ||
204 | /* | |
205 | * Allocate our watchdog driver data, which has the | |
206 | * struct watchdog_device nested within it. | |
207 | */ | |
208 | wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL); | |
209 | if (!wdt) | |
210 | return -ENOMEM; | |
211 | ||
212 | /* Initialize struct tegra_wdt. */ | |
213 | wdt->wdt_regs = regs + WDT_BASE; | |
214 | wdt->tmr_regs = regs + WDT_TIMER_BASE; | |
215 | ||
216 | /* Initialize struct watchdog_device. */ | |
217 | wdd = &wdt->wdd; | |
218 | wdd->timeout = heartbeat; | |
219 | wdd->info = &tegra_wdt_info; | |
220 | wdd->ops = &tegra_wdt_ops; | |
221 | wdd->min_timeout = MIN_WDT_TIMEOUT; | |
222 | wdd->max_timeout = MAX_WDT_TIMEOUT; | |
6551881c | 223 | wdd->parent = &pdev->dev; |
c33a1597 AC |
224 | |
225 | watchdog_set_drvdata(wdd, wdt); | |
226 | ||
227 | watchdog_set_nowayout(wdd, nowayout); | |
228 | ||
229 | ret = watchdog_register_device(wdd); | |
230 | if (ret) { | |
231 | dev_err(&pdev->dev, | |
232 | "failed to register watchdog device\n"); | |
233 | return ret; | |
234 | } | |
235 | ||
236 | platform_set_drvdata(pdev, wdt); | |
237 | ||
238 | dev_info(&pdev->dev, | |
239 | "initialized (heartbeat = %d sec, nowayout = %d)\n", | |
240 | heartbeat, nowayout); | |
241 | ||
242 | return 0; | |
243 | } | |
244 | ||
245 | static int tegra_wdt_remove(struct platform_device *pdev) | |
246 | { | |
247 | struct tegra_wdt *wdt = platform_get_drvdata(pdev); | |
248 | ||
249 | tegra_wdt_stop(&wdt->wdd); | |
250 | ||
251 | watchdog_unregister_device(&wdt->wdd); | |
252 | ||
253 | dev_info(&pdev->dev, "removed wdt\n"); | |
254 | ||
255 | return 0; | |
256 | } | |
257 | ||
258 | #ifdef CONFIG_PM_SLEEP | |
259 | static int tegra_wdt_runtime_suspend(struct device *dev) | |
260 | { | |
261 | struct tegra_wdt *wdt = dev_get_drvdata(dev); | |
262 | ||
263 | if (watchdog_active(&wdt->wdd)) | |
264 | tegra_wdt_stop(&wdt->wdd); | |
265 | ||
266 | return 0; | |
267 | } | |
268 | ||
269 | static int tegra_wdt_runtime_resume(struct device *dev) | |
270 | { | |
271 | struct tegra_wdt *wdt = dev_get_drvdata(dev); | |
272 | ||
273 | if (watchdog_active(&wdt->wdd)) | |
274 | tegra_wdt_start(&wdt->wdd); | |
275 | ||
276 | return 0; | |
277 | } | |
278 | #endif | |
279 | ||
280 | static const struct of_device_id tegra_wdt_of_match[] = { | |
281 | { .compatible = "nvidia,tegra30-timer", }, | |
282 | { }, | |
283 | }; | |
284 | MODULE_DEVICE_TABLE(of, tegra_wdt_of_match); | |
285 | ||
286 | static const struct dev_pm_ops tegra_wdt_pm_ops = { | |
287 | SET_SYSTEM_SLEEP_PM_OPS(tegra_wdt_runtime_suspend, | |
288 | tegra_wdt_runtime_resume) | |
289 | }; | |
290 | ||
291 | static struct platform_driver tegra_wdt_driver = { | |
292 | .probe = tegra_wdt_probe, | |
293 | .remove = tegra_wdt_remove, | |
294 | .driver = { | |
c33a1597 AC |
295 | .name = "tegra-wdt", |
296 | .pm = &tegra_wdt_pm_ops, | |
297 | .of_match_table = tegra_wdt_of_match, | |
298 | }, | |
299 | }; | |
300 | module_platform_driver(tegra_wdt_driver); | |
301 | ||
302 | MODULE_AUTHOR("NVIDIA Corporation"); | |
303 | MODULE_DESCRIPTION("Tegra Watchdog Driver"); | |
304 | MODULE_LICENSE("GPL v2"); |