Commit | Line | Data |
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1da177e4 | 1 | /* |
0e94f2ee VD |
2 | * w83627hf/thf WDT driver |
3 | * | |
30a83695 GR |
4 | * (c) Copyright 2013 Guenter Roeck |
5 | * converted to watchdog infrastructure | |
6 | * | |
0e94f2ee VD |
7 | * (c) Copyright 2007 Vlad Drukker <vlad@storewiz.com> |
8 | * added support for W83627THF. | |
1da177e4 | 9 | * |
d36b6910 | 10 | * (c) Copyright 2003,2007 Pádraig Brady <P@draigBrady.com> |
1da177e4 LT |
11 | * |
12 | * Based on advantechwdt.c which is based on wdt.c. | |
13 | * Original copyright messages: | |
14 | * | |
15 | * (c) Copyright 2000-2001 Marek Michalkiewicz <marekm@linux.org.pl> | |
16 | * | |
29fa0586 AC |
17 | * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>, |
18 | * All Rights Reserved. | |
1da177e4 LT |
19 | * |
20 | * This program is free software; you can redistribute it and/or | |
21 | * modify it under the terms of the GNU General Public License | |
22 | * as published by the Free Software Foundation; either version | |
23 | * 2 of the License, or (at your option) any later version. | |
24 | * | |
25 | * Neither Alan Cox nor CymruNet Ltd. admit liability nor provide | |
26 | * warranty for any of this software. This material is provided | |
27 | * "AS-IS" and at no charge. | |
28 | * | |
29fa0586 | 29 | * (c) Copyright 1995 Alan Cox <alan@lxorguk.ukuu.org.uk> |
1da177e4 LT |
30 | */ |
31 | ||
27c766aa JP |
32 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
33 | ||
1da177e4 LT |
34 | #include <linux/module.h> |
35 | #include <linux/moduleparam.h> | |
36 | #include <linux/types.h> | |
1da177e4 | 37 | #include <linux/watchdog.h> |
1da177e4 | 38 | #include <linux/ioport.h> |
1da177e4 | 39 | #include <linux/init.h> |
46a3949d | 40 | #include <linux/io.h> |
1da177e4 | 41 | |
9c67bea4 | 42 | #define WATCHDOG_NAME "w83627hf/thf/hg/dhg WDT" |
1da177e4 LT |
43 | #define WATCHDOG_TIMEOUT 60 /* 60 sec default timeout */ |
44 | ||
962c04f5 | 45 | static int wdt_io; |
7b6d0b6a GR |
46 | static int cr_wdt_timeout; /* WDT timeout register */ |
47 | static int cr_wdt_control; /* WDT control register */ | |
33f74b89 | 48 | static int cr_wdt_csr; /* WDT control & status register */ |
962c04f5 | 49 | |
7b6d0b6a GR |
50 | enum chips { w83627hf, w83627s, w83697hf, w83697ug, w83637hf, w83627thf, |
51 | w83687thf, w83627ehf, w83627dhg, w83627uhg, w83667hg, w83627dhg_p, | |
33f74b89 | 52 | w83667hg_b, nct6775, nct6776, nct6779, nct6791, nct6792, nct6102 }; |
1da177e4 | 53 | |
30a83695 | 54 | static int timeout; /* in seconds */ |
1da177e4 | 55 | module_param(timeout, int, 0); |
46a3949d AC |
56 | MODULE_PARM_DESC(timeout, |
57 | "Watchdog timeout in seconds. 1 <= timeout <= 255, default=" | |
58 | __MODULE_STRING(WATCHDOG_TIMEOUT) "."); | |
1da177e4 | 59 | |
86a1e189 WVS |
60 | static bool nowayout = WATCHDOG_NOWAYOUT; |
61 | module_param(nowayout, bool, 0); | |
46a3949d AC |
62 | MODULE_PARM_DESC(nowayout, |
63 | "Watchdog cannot be stopped once started (default=" | |
64 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
1da177e4 | 65 | |
be281588 GR |
66 | static int early_disable; |
67 | module_param(early_disable, int, 0); | |
68 | MODULE_PARM_DESC(early_disable, "Disable watchdog at boot time (default=0)"); | |
69 | ||
1da177e4 LT |
70 | /* |
71 | * Kernel methods. | |
72 | */ | |
73 | ||
74 | #define WDT_EFER (wdt_io+0) /* Extended Function Enable Registers */ | |
46a3949d AC |
75 | #define WDT_EFIR (wdt_io+0) /* Extended Function Index Register |
76 | (same as EFER) */ | |
1da177e4 LT |
77 | #define WDT_EFDR (WDT_EFIR+1) /* Extended Function Data Register */ |
78 | ||
ef0c1a6b GR |
79 | #define W83627HF_LD_WDT 0x08 |
80 | ||
962c04f5 GR |
81 | #define W83627HF_ID 0x52 |
82 | #define W83627S_ID 0x59 | |
7b6d0b6a GR |
83 | #define W83697HF_ID 0x60 |
84 | #define W83697UG_ID 0x68 | |
962c04f5 GR |
85 | #define W83637HF_ID 0x70 |
86 | #define W83627THF_ID 0x82 | |
87 | #define W83687THF_ID 0x85 | |
88 | #define W83627EHF_ID 0x88 | |
89 | #define W83627DHG_ID 0xa0 | |
90 | #define W83627UHG_ID 0xa2 | |
91 | #define W83667HG_ID 0xa5 | |
92 | #define W83627DHG_P_ID 0xb0 | |
93 | #define W83667HG_B_ID 0xb3 | |
94 | #define NCT6775_ID 0xb4 | |
95 | #define NCT6776_ID 0xc3 | |
33f74b89 | 96 | #define NCT6102_ID 0xc4 |
962c04f5 | 97 | #define NCT6779_ID 0xc5 |
a77841d5 GR |
98 | #define NCT6791_ID 0xc8 |
99 | #define NCT6792_ID 0xc9 | |
962c04f5 | 100 | |
7b6d0b6a GR |
101 | #define W83627HF_WDT_TIMEOUT 0xf6 |
102 | #define W83697HF_WDT_TIMEOUT 0xf4 | |
33f74b89 | 103 | #define NCT6102D_WDT_TIMEOUT 0xf1 |
7b6d0b6a GR |
104 | |
105 | #define W83627HF_WDT_CONTROL 0xf5 | |
106 | #define W83697HF_WDT_CONTROL 0xf3 | |
33f74b89 RK |
107 | #define NCT6102D_WDT_CONTROL 0xf0 |
108 | ||
109 | #define W836X7HF_WDT_CSR 0xf7 | |
110 | #define NCT6102D_WDT_CSR 0xf2 | |
7b6d0b6a | 111 | |
ef0c1a6b GR |
112 | static void superio_outb(int reg, int val) |
113 | { | |
114 | outb(reg, WDT_EFER); | |
115 | outb(val, WDT_EFDR); | |
116 | } | |
117 | ||
118 | static inline int superio_inb(int reg) | |
119 | { | |
120 | outb(reg, WDT_EFER); | |
121 | return inb(WDT_EFDR); | |
122 | } | |
123 | ||
124 | static int superio_enter(void) | |
1da177e4 | 125 | { |
ef0c1a6b GR |
126 | if (!request_muxed_region(wdt_io, 2, WATCHDOG_NAME)) |
127 | return -EBUSY; | |
128 | ||
1da177e4 LT |
129 | outb_p(0x87, WDT_EFER); /* Enter extended function mode */ |
130 | outb_p(0x87, WDT_EFER); /* Again according to manual */ | |
ef0c1a6b GR |
131 | |
132 | return 0; | |
1da177e4 LT |
133 | } |
134 | ||
ef0c1a6b GR |
135 | static void superio_select(int ld) |
136 | { | |
137 | superio_outb(0x07, ld); | |
138 | } | |
139 | ||
140 | static void superio_exit(void) | |
1da177e4 LT |
141 | { |
142 | outb_p(0xAA, WDT_EFER); /* Leave extended function mode */ | |
ef0c1a6b | 143 | release_region(wdt_io, 2); |
1da177e4 LT |
144 | } |
145 | ||
962c04f5 | 146 | static int w83627hf_init(struct watchdog_device *wdog, enum chips chip) |
1da177e4 | 147 | { |
ef0c1a6b | 148 | int ret; |
1da177e4 LT |
149 | unsigned char t; |
150 | ||
ef0c1a6b GR |
151 | ret = superio_enter(); |
152 | if (ret) | |
153 | return ret; | |
1da177e4 | 154 | |
ef0c1a6b | 155 | superio_select(W83627HF_LD_WDT); |
8f526389 | 156 | |
ef0c1a6b GR |
157 | /* set CR30 bit 0 to activate GPIO2 */ |
158 | t = superio_inb(0x30); | |
ac461103 | 159 | if (!(t & 0x01)) |
ef0c1a6b | 160 | superio_outb(0x30, t | 0x01); |
8f526389 | 161 | |
962c04f5 GR |
162 | switch (chip) { |
163 | case w83627hf: | |
164 | case w83627s: | |
165 | t = superio_inb(0x2B) & ~0x10; | |
166 | superio_outb(0x2B, t); /* set GPIO24 to WDT0 */ | |
167 | break; | |
7b6d0b6a GR |
168 | case w83697hf: |
169 | /* Set pin 119 to WDTO# mode (= CR29, WDT0) */ | |
170 | t = superio_inb(0x29) & ~0x60; | |
171 | t |= 0x20; | |
172 | superio_outb(0x29, t); | |
173 | break; | |
174 | case w83697ug: | |
175 | /* Set pin 118 to WDTO# mode */ | |
176 | t = superio_inb(0x2b) & ~0x04; | |
177 | superio_outb(0x2b, t); | |
178 | break; | |
962c04f5 GR |
179 | case w83627thf: |
180 | t = (superio_inb(0x2B) & ~0x08) | 0x04; | |
181 | superio_outb(0x2B, t); /* set GPIO3 to WDT0 */ | |
182 | break; | |
183 | case w83627dhg: | |
184 | case w83627dhg_p: | |
185 | t = superio_inb(0x2D) & ~0x01; /* PIN77 -> WDT0# */ | |
186 | superio_outb(0x2D, t); /* set GPIO5 to WDT0 */ | |
7b6d0b6a | 187 | t = superio_inb(cr_wdt_control); |
962c04f5 GR |
188 | t |= 0x02; /* enable the WDTO# output low pulse |
189 | * to the KBRST# pin */ | |
7b6d0b6a | 190 | superio_outb(cr_wdt_control, t); |
962c04f5 GR |
191 | break; |
192 | case w83637hf: | |
193 | break; | |
194 | case w83687thf: | |
195 | t = superio_inb(0x2C) & ~0x80; /* PIN47 -> WDT0# */ | |
196 | superio_outb(0x2C, t); | |
197 | break; | |
198 | case w83627ehf: | |
199 | case w83627uhg: | |
200 | case w83667hg: | |
201 | case w83667hg_b: | |
202 | case nct6775: | |
203 | case nct6776: | |
204 | case nct6779: | |
a77841d5 GR |
205 | case nct6791: |
206 | case nct6792: | |
33f74b89 | 207 | case nct6102: |
962c04f5 GR |
208 | /* |
209 | * These chips have a fixed WDTO# output pin (W83627UHG), | |
210 | * or support more than one WDTO# output pin. | |
211 | * Don't touch its configuration, and hope the BIOS | |
212 | * does the right thing. | |
213 | */ | |
7b6d0b6a | 214 | t = superio_inb(cr_wdt_control); |
962c04f5 GR |
215 | t |= 0x02; /* enable the WDTO# output low pulse |
216 | * to the KBRST# pin */ | |
7b6d0b6a | 217 | superio_outb(cr_wdt_control, t); |
962c04f5 GR |
218 | break; |
219 | default: | |
220 | break; | |
221 | } | |
222 | ||
7b6d0b6a | 223 | t = superio_inb(cr_wdt_timeout); |
93642ecd | 224 | if (t != 0) { |
be281588 GR |
225 | if (early_disable) { |
226 | pr_warn("Stopping previously enabled watchdog until userland kicks in\n"); | |
227 | superio_outb(cr_wdt_timeout, 0); | |
228 | } else { | |
229 | pr_info("Watchdog already running. Resetting timeout to %d sec\n", | |
230 | wdog->timeout); | |
231 | superio_outb(cr_wdt_timeout, wdog->timeout); | |
232 | } | |
93642ecd | 233 | } |