xen: Use the proper irq functions
[deliverable/linux.git] / drivers / xen / events / events_base.c
CommitLineData
e46cdb66
JF
1/*
2 * Xen event channels
3 *
4 * Xen models interrupts with abstract event channels. Because each
5 * domain gets 1024 event channels, but NR_IRQ is not that large, we
6 * must dynamically map irqs<->event channels. The event channels
7 * interface with the rest of the kernel by defining a xen interrupt
25985edc 8 * chip. When an event is received, it is mapped to an irq and sent
e46cdb66
JF
9 * through the normal interrupt processing path.
10 *
11 * There are four kinds of events which can be mapped to an event
12 * channel:
13 *
14 * 1. Inter-domain notifications. This includes all the virtual
15 * device events, since they're driven by front-ends in another domain
16 * (typically dom0).
17 * 2. VIRQs, typically used for timers. These are per-cpu events.
18 * 3. IPIs.
d46a78b0 19 * 4. PIRQs - Hardware interrupts.
e46cdb66
JF
20 *
21 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
22 */
23
283c0972
JP
24#define pr_fmt(fmt) "xen:" KBUILD_MODNAME ": " fmt
25
e46cdb66
JF
26#include <linux/linkage.h>
27#include <linux/interrupt.h>
28#include <linux/irq.h>
29#include <linux/module.h>
30#include <linux/string.h>
28e08861 31#include <linux/bootmem.h>
5a0e3ad6 32#include <linux/slab.h>
b21ddbf5 33#include <linux/irqnr.h>
f731e3ef 34#include <linux/pci.h>
e46cdb66 35
0ec53ecf 36#ifdef CONFIG_X86
38e20b07 37#include <asm/desc.h>
e46cdb66
JF
38#include <asm/ptrace.h>
39#include <asm/irq.h>
792dc4f6 40#include <asm/idle.h>
0794bfc7 41#include <asm/io_apic.h>
9846ff10 42#include <asm/xen/page.h>
42a1de56 43#include <asm/xen/pci.h>
0ec53ecf
SS
44#endif
45#include <asm/sync_bitops.h>
e46cdb66 46#include <asm/xen/hypercall.h>
8d1b8753 47#include <asm/xen/hypervisor.h>
e46cdb66 48
38e20b07
SY
49#include <xen/xen.h>
50#include <xen/hvm.h>
e04d0d07 51#include <xen/xen-ops.h>
e46cdb66
JF
52#include <xen/events.h>
53#include <xen/interface/xen.h>
54#include <xen/interface/event_channel.h>
38e20b07
SY
55#include <xen/interface/hvm/hvm_op.h>
56#include <xen/interface/hvm/params.h>
0ec53ecf
SS
57#include <xen/interface/physdev.h>
58#include <xen/interface/sched.h>
6efa20e4 59#include <xen/interface/vcpu.h>
0ec53ecf 60#include <asm/hw_irq.h>
e46cdb66 61
9a489f45
DV
62#include "events_internal.h"
63
ab9a1cca
DV
64const struct evtchn_ops *evtchn_ops;
65
e46cdb66
JF
66/*
67 * This lock protects updates to the following mapping and reference-count
68 * arrays. The lock does not need to be acquired to read the mapping tables.
69 */
77365948 70static DEFINE_MUTEX(irq_mapping_update_lock);
e46cdb66 71
6cb6537d
IC
72static LIST_HEAD(xen_irq_list_head);
73
e46cdb66 74/* IRQ <-> VIRQ mapping. */
204fba4a 75static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
e46cdb66 76
f87e4cac 77/* IRQ <-> IPI mapping */
204fba4a 78static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
f87e4cac 79
d0b075ff 80int **evtchn_to_irq;
bf86ad80 81#ifdef CONFIG_X86
9846ff10 82static unsigned long *pirq_eoi_map;
bf86ad80 83#endif
9846ff10 84static bool (*pirq_needs_eoi)(unsigned irq);
3b32f574 85
d0b075ff
DV
86#define EVTCHN_ROW(e) (e / (PAGE_SIZE/sizeof(**evtchn_to_irq)))
87#define EVTCHN_COL(e) (e % (PAGE_SIZE/sizeof(**evtchn_to_irq)))
88#define EVTCHN_PER_ROW (PAGE_SIZE / sizeof(**evtchn_to_irq))
89
e46cdb66
JF
90/* Xen will never allocate port zero for any purpose. */
91#define VALID_EVTCHN(chn) ((chn) != 0)
92
e46cdb66 93static struct irq_chip xen_dynamic_chip;
aaca4964 94static struct irq_chip xen_percpu_chip;
d46a78b0 95static struct irq_chip xen_pirq_chip;
7e186bdd
SS
96static void enable_dynirq(struct irq_data *data);
97static void disable_dynirq(struct irq_data *data);
e46cdb66 98
d0b075ff
DV
99static void clear_evtchn_to_irq_row(unsigned row)
100{
101 unsigned col;
102
103 for (col = 0; col < EVTCHN_PER_ROW; col++)
104 evtchn_to_irq[row][col] = -1;
105}
106
107static void clear_evtchn_to_irq_all(void)
108{
109 unsigned row;
110
111 for (row = 0; row < EVTCHN_ROW(xen_evtchn_max_channels()); row++) {
112 if (evtchn_to_irq[row] == NULL)
113 continue;
114 clear_evtchn_to_irq_row(row);
115 }
116}
117
118static int set_evtchn_to_irq(unsigned evtchn, unsigned irq)
119{
120 unsigned row;
121 unsigned col;
122
123 if (evtchn >= xen_evtchn_max_channels())
124 return -EINVAL;
125
126 row = EVTCHN_ROW(evtchn);
127 col = EVTCHN_COL(evtchn);
128
129 if (evtchn_to_irq[row] == NULL) {
130 /* Unallocated irq entries return -1 anyway */
131 if (irq == -1)
132 return 0;
133
134 evtchn_to_irq[row] = (int *)get_zeroed_page(GFP_KERNEL);
135 if (evtchn_to_irq[row] == NULL)
136 return -ENOMEM;
137
138 clear_evtchn_to_irq_row(row);
139 }
140
141 evtchn_to_irq[EVTCHN_ROW(evtchn)][EVTCHN_COL(evtchn)] = irq;
142 return 0;
143}
144
145int get_evtchn_to_irq(unsigned evtchn)
146{
147 if (evtchn >= xen_evtchn_max_channels())
148 return -1;
149 if (evtchn_to_irq[EVTCHN_ROW(evtchn)] == NULL)
150 return -1;
151 return evtchn_to_irq[EVTCHN_ROW(evtchn)][EVTCHN_COL(evtchn)];
152}
153
9158c358 154/* Get info for IRQ */
9a489f45 155struct irq_info *info_for_irq(unsigned irq)
ced40d0f 156{
c442b806 157 return irq_get_handler_data(irq);
ced40d0f
JF
158}
159
9158c358 160/* Constructors for packed IRQ information. */
96d4c588 161static int xen_irq_info_common_setup(struct irq_info *info,
3d4cfa37 162 unsigned irq,
9158c358 163 enum xen_irq_type type,
d0b075ff 164 unsigned evtchn,
9158c358 165 unsigned short cpu)
ced40d0f 166{
d0b075ff 167 int ret;
9158c358
IC
168
169 BUG_ON(info->type != IRQT_UNBOUND && info->type != type);
170
171 info->type = type;
6cb6537d 172 info->irq = irq;
9158c358
IC
173 info->evtchn = evtchn;
174 info->cpu = cpu;
3d4cfa37 175
d0b075ff
DV
176 ret = set_evtchn_to_irq(evtchn, irq);
177 if (ret < 0)
178 return ret;
934f585e
JG
179
180 irq_clear_status_flags(irq, IRQ_NOREQUEST|IRQ_NOAUTOEN);
96d4c588 181
08385875 182 return xen_evtchn_port_setup(info);
ced40d0f
JF
183}
184
96d4c588 185static int xen_irq_info_evtchn_setup(unsigned irq,
d0b075ff 186 unsigned evtchn)
ced40d0f 187{
9158c358
IC
188 struct irq_info *info = info_for_irq(irq);
189
96d4c588 190 return xen_irq_info_common_setup(info, irq, IRQT_EVTCHN, evtchn, 0);
ced40d0f
JF
191}
192
96d4c588 193static int xen_irq_info_ipi_setup(unsigned cpu,
3d4cfa37 194 unsigned irq,
d0b075ff 195 unsigned evtchn,
9158c358 196 enum ipi_vector ipi)
e46cdb66 197{
9158c358
IC
198 struct irq_info *info = info_for_irq(irq);
199
9158c358 200 info->u.ipi = ipi;
3d4cfa37
IC
201
202 per_cpu(ipi_to_irq, cpu)[ipi] = irq;
96d4c588
DV
203
204 return xen_irq_info_common_setup(info, irq, IRQT_IPI, evtchn, 0);
ced40d0f
JF
205}
206
96d4c588 207static int xen_irq_info_virq_setup(unsigned cpu,
3d4cfa37 208 unsigned irq,
d0b075ff
DV
209 unsigned evtchn,
210 unsigned virq)
ced40d0f 211{
9158c358
IC
212 struct irq_info *info = info_for_irq(irq);
213
9158c358 214 info->u.virq = virq;
3d4cfa37
IC
215
216 per_cpu(virq_to_irq, cpu)[virq] = irq;
96d4c588
DV
217
218 return xen_irq_info_common_setup(info, irq, IRQT_VIRQ, evtchn, 0);
ced40d0f
JF
219}
220
96d4c588 221static int xen_irq_info_pirq_setup(unsigned irq,
d0b075ff
DV
222 unsigned evtchn,
223 unsigned pirq,
224 unsigned gsi,
beafbdc1 225 uint16_t domid,
9158c358 226 unsigned char flags)
ced40d0f 227{
9158c358
IC
228 struct irq_info *info = info_for_irq(irq);
229
9158c358
IC
230 info->u.pirq.pirq = pirq;
231 info->u.pirq.gsi = gsi;
beafbdc1 232 info->u.pirq.domid = domid;
9158c358 233 info->u.pirq.flags = flags;
96d4c588
DV
234
235 return xen_irq_info_common_setup(info, irq, IRQT_PIRQ, evtchn, 0);
e46cdb66
JF
236}
237
d0b075ff
DV
238static void xen_irq_info_cleanup(struct irq_info *info)
239{
240 set_evtchn_to_irq(info->evtchn, -1);
241 info->evtchn = 0;
242}
243
e46cdb66
JF
244/*
245 * Accessors for packed IRQ information.
246 */
9a489f45 247unsigned int evtchn_from_irq(unsigned irq)
e46cdb66 248{
110e7c7e
JJ
249 if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
250 return 0;
251
ced40d0f 252 return info_for_irq(irq)->evtchn;
e46cdb66
JF
253}
254
d4c04536
IC
255unsigned irq_from_evtchn(unsigned int evtchn)
256{
d0b075ff 257 return get_evtchn_to_irq(evtchn);
d4c04536
IC
258}
259EXPORT_SYMBOL_GPL(irq_from_evtchn);
260
9a489f45
DV
261int irq_from_virq(unsigned int cpu, unsigned int virq)
262{
263 return per_cpu(virq_to_irq, cpu)[virq];
264}
265
ced40d0f 266static enum ipi_vector ipi_from_irq(unsigned irq)
e46cdb66 267{
ced40d0f
JF
268 struct irq_info *info = info_for_irq(irq);
269
270 BUG_ON(info == NULL);
271 BUG_ON(info->type != IRQT_IPI);
272
273 return info->u.ipi;
274}
275
276static unsigned virq_from_irq(unsigned irq)
277{
278 struct irq_info *info = info_for_irq(irq);
279
280 BUG_ON(info == NULL);
281 BUG_ON(info->type != IRQT_VIRQ);
282
283 return info->u.virq;
284}
285
7a043f11
SS
286static unsigned pirq_from_irq(unsigned irq)
287{
288 struct irq_info *info = info_for_irq(irq);
289
290 BUG_ON(info == NULL);
291 BUG_ON(info->type != IRQT_PIRQ);
292
293 return info->u.pirq.pirq;
294}
295
ced40d0f
JF
296static enum xen_irq_type type_from_irq(unsigned irq)
297{
298 return info_for_irq(irq)->type;
299}
300
9a489f45 301unsigned cpu_from_irq(unsigned irq)
ced40d0f
JF
302{
303 return info_for_irq(irq)->cpu;
304}
305
9a489f45 306unsigned int cpu_from_evtchn(unsigned int evtchn)
ced40d0f 307{
d0b075ff 308 int irq = get_evtchn_to_irq(evtchn);
ced40d0f
JF
309 unsigned ret = 0;
310
311 if (irq != -1)
312 ret = cpu_from_irq(irq);
313
314 return ret;
e46cdb66
JF
315}
316
bf86ad80 317#ifdef CONFIG_X86
9846ff10 318static bool pirq_check_eoi_map(unsigned irq)
d46a78b0 319{
521394e4 320 return test_bit(pirq_from_irq(irq), pirq_eoi_map);
9846ff10 321}
bf86ad80 322#endif
d46a78b0 323
9846ff10
SS
324static bool pirq_needs_eoi_flag(unsigned irq)
325{
326 struct irq_info *info = info_for_irq(irq);
d46a78b0
JF
327 BUG_ON(info->type != IRQT_PIRQ);
328
329 return info->u.pirq.flags & PIRQ_NEEDS_EOI;
330}
331
e46cdb66
JF
332static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
333{
d0b075ff 334 int irq = get_evtchn_to_irq(chn);
9a489f45 335 struct irq_info *info = info_for_irq(irq);
e46cdb66
JF
336
337 BUG_ON(irq == -1);
338#ifdef CONFIG_SMP
589d03e9 339 cpumask_copy(irq_get_irq_data(irq)->affinity, cpumask_of(cpu));
e46cdb66 340#endif
9a489f45 341 xen_evtchn_port_bind_to_cpu(info, cpu);
168d2f46 342
9a489f45 343 info->cpu = cpu;
3f70fa82
WL
344}
345
fd21069d
DV
346static void xen_evtchn_mask_all(void)
347{
348 unsigned int evtchn;
349
350 for (evtchn = 0; evtchn < xen_evtchn_nr_channels(); evtchn++)
351 mask_evtchn(evtchn);
352}
353
e46cdb66
JF
354/**
355 * notify_remote_via_irq - send event to remote end of event channel via irq
356 * @irq: irq of event channel to send event to
357 *
358 * Unlike notify_remote_via_evtchn(), this is safe to use across
359 * save/restore. Notifications on a broken connection are silently
360 * dropped.
361 */
362void notify_remote_via_irq(int irq)
363{
364 int evtchn = evtchn_from_irq(irq);
365
366 if (VALID_EVTCHN(evtchn))
367 notify_remote_via_evtchn(evtchn);
368}
369EXPORT_SYMBOL_GPL(notify_remote_via_irq);
370
6cb6537d
IC
371static void xen_irq_init(unsigned irq)
372{
373 struct irq_info *info;
b5328cd1 374#ifdef CONFIG_SMP
6cb6537d 375 /* By default all event channels notify CPU#0. */
589d03e9 376 cpumask_copy(irq_get_irq_data(irq)->affinity, cpumask_of(0));
44626e4a 377#endif
6cb6537d 378
ca62ce8c
IC
379 info = kzalloc(sizeof(*info), GFP_KERNEL);
380 if (info == NULL)
381 panic("Unable to allocate metadata for IRQ%d\n", irq);
6cb6537d
IC
382
383 info->type = IRQT_UNBOUND;
420eb554 384 info->refcnt = -1;
6cb6537d 385
c442b806 386 irq_set_handler_data(irq, info);
ca62ce8c 387
6cb6537d
IC
388 list_add_tail(&info->list, &xen_irq_list_head);
389}
390
7bee9768 391static int __must_check xen_allocate_irq_dynamic(void)
0794bfc7 392{
89911501
IC
393 int first = 0;
394 int irq;
0794bfc7
KRW
395
396#ifdef CONFIG_X86_IO_APIC
89911501
IC
397 /*
398 * For an HVM guest or domain 0 which see "real" (emulated or
25985edc 399 * actual respectively) GSIs we allocate dynamic IRQs
89911501
IC
400 * e.g. those corresponding to event channels or MSIs
401 * etc. from the range above those "real" GSIs to avoid
402 * collisions.
403 */
404 if (xen_initial_domain() || xen_hvm_domain())
405 first = get_nr_irqs_gsi();
0794bfc7
KRW
406#endif
407
89911501 408 irq = irq_alloc_desc_from(first, -1);
3a69e916 409
e6599225
KRW
410 if (irq >= 0)
411 xen_irq_init(irq);
ced40d0f 412
e46cdb66 413 return irq;
d46a78b0
JF
414}
415
7bee9768 416static int __must_check xen_allocate_irq_gsi(unsigned gsi)
c9df1ce5
IC
417{
418 int irq;
419
89911501
IC
420 /*
421 * A PV guest has no concept of a GSI (since it has no ACPI
422 * nor access to/knowledge of the physical APICs). Therefore
423 * all IRQs are dynamically allocated from the entire IRQ
424 * space.
425 */
426 if (xen_pv_domain() && !xen_initial_domain())
c9df1ce5
IC
427 return xen_allocate_irq_dynamic();
428
429 /* Legacy IRQ descriptors are already allocated by the arch. */
430 if (gsi < NR_IRQS_LEGACY)
6cb6537d
IC
431 irq = gsi;
432 else
433 irq = irq_alloc_desc_at(gsi, -1);
c9df1ce5 434
6cb6537d 435 xen_irq_init(irq);
c9df1ce5
IC
436
437 return irq;
438}
439
440static void xen_free_irq(unsigned irq)
441{
c442b806 442 struct irq_info *info = irq_get_handler_data(irq);
6cb6537d 443
94032c50
KRW
444 if (WARN_ON(!info))
445 return;
446
6cb6537d 447 list_del(&info->list);
9158c358 448
c442b806 449 irq_set_handler_data(irq, NULL);
ca62ce8c 450
420eb554
DDG
451 WARN_ON(info->refcnt > 0);
452
ca62ce8c
IC
453 kfree(info);
454
72146104
IC
455 /* Legacy IRQ descriptors are managed by the arch. */
456 if (irq < NR_IRQS_LEGACY)
457 return;
458
c9df1ce5
IC
459 irq_free_desc(irq);
460}
461
d0b075ff
DV
462static void xen_evtchn_close(unsigned int port)
463{
464 struct evtchn_close close;
465
466 close.port = port;
467 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
468 BUG();
469
470 /* Closed ports are implicitly re-bound to VCPU0. */
471 bind_evtchn_to_cpu(port, 0);
472}
473
d46a78b0
JF
474static void pirq_query_unmask(int irq)
475{
476 struct physdev_irq_status_query irq_status;
477 struct irq_info *info = info_for_irq(irq);
478
479 BUG_ON(info->type != IRQT_PIRQ);
480
7a043f11 481 irq_status.irq = pirq_from_irq(irq);
d46a78b0
JF
482 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
483 irq_status.flags = 0;
484
485 info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
486 if (irq_status.flags & XENIRQSTAT_needs_eoi)
487 info->u.pirq.flags |= PIRQ_NEEDS_EOI;
488}
489
490static bool probing_irq(int irq)
491{
492 struct irq_desc *desc = irq_to_desc(irq);
493
494 return desc && desc->action == NULL;
495}
496
7e186bdd
SS
497static void eoi_pirq(struct irq_data *data)
498{
499 int evtchn = evtchn_from_irq(data->irq);
500 struct physdev_eoi eoi = { .irq = pirq_from_irq(data->irq) };
501 int rc = 0;
502
503 irq_move_irq(data);
504
505 if (VALID_EVTCHN(evtchn))
506 clear_evtchn(evtchn);
507
508 if (pirq_needs_eoi(data->irq)) {
509 rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
510 WARN_ON(rc);
511 }
512}
513
514static void mask_ack_pirq(struct irq_data *data)
515{
516 disable_dynirq(data);
517 eoi_pirq(data);
518}
519
c9e265e0 520static unsigned int __startup_pirq(unsigned int irq)
d46a78b0
JF
521{
522 struct evtchn_bind_pirq bind_pirq;
523 struct irq_info *info = info_for_irq(irq);
524 int evtchn = evtchn_from_irq(irq);
15ebbb82 525 int rc;
d46a78b0
JF
526
527 BUG_ON(info->type != IRQT_PIRQ);
528
529 if (VALID_EVTCHN(evtchn))
530 goto out;
531
7a043f11 532 bind_pirq.pirq = pirq_from_irq(irq);
d46a78b0 533 /* NB. We are happy to share unless we are probing. */
15ebbb82
KRW
534 bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
535 BIND_PIRQ__WILL_SHARE : 0;
536 rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
537 if (rc != 0) {
d46a78b0 538 if (!probing_irq(irq))
283c0972 539 pr_info("Failed to obtain physical IRQ %d\n", irq);
d46a78b0
JF
540 return 0;
541 }
542 evtchn = bind_pirq.port;
543
544 pirq_query_unmask(irq);
545
d0b075ff
DV
546 rc = set_evtchn_to_irq(evtchn, irq);
547 if (rc != 0) {
548 pr_err("irq%d: Failed to set port to irq mapping (%d)\n",
549 irq, rc);
550 xen_evtchn_close(evtchn);
551 return 0;
552 }
d46a78b0
JF
553 bind_evtchn_to_cpu(evtchn, 0);
554 info->evtchn = evtchn;
555
556out:
557 unmask_evtchn(evtchn);
7e186bdd 558 eoi_pirq(irq_get_irq_data(irq));
d46a78b0
JF
559
560 return 0;
561}
562
c9e265e0
TG
563static unsigned int startup_pirq(struct irq_data *data)
564{
565 return __startup_pirq(data->irq);
566}
567
568static void shutdown_pirq(struct irq_data *data)
d46a78b0 569{
c9e265e0 570 unsigned int irq = data->irq;
d46a78b0 571 struct irq_info *info = info_for_irq(irq);
d0b075ff 572 unsigned evtchn = evtchn_from_irq(irq);
d46a78b0
JF
573
574 BUG_ON(info->type != IRQT_PIRQ);
575
576 if (!VALID_EVTCHN(evtchn))
577 return;
578
579 mask_evtchn(evtchn);
d0b075ff
DV
580 xen_evtchn_close(evtchn);
581 xen_irq_info_cleanup(info);
d46a78b0
JF
582}
583
c9e265e0 584static void enable_pirq(struct irq_data *data)
d46a78b0 585{
c9e265e0 586 startup_pirq(data);
d46a78b0
JF
587}
588
c9e265e0 589static void disable_pirq(struct irq_data *data)
d46a78b0 590{
7e186bdd 591 disable_dynirq(data);
d46a78b0
JF
592}
593
68c2c39a 594int xen_irq_from_gsi(unsigned gsi)
d46a78b0 595{
6cb6537d 596 struct irq_info *info;
d46a78b0 597
6cb6537d
IC
598 list_for_each_entry(info, &xen_irq_list_head, list) {
599 if (info->type != IRQT_PIRQ)
d46a78b0
JF
600 continue;
601
6cb6537d
IC
602 if (info->u.pirq.gsi == gsi)
603 return info->irq;
d46a78b0
JF
604 }
605
606 return -1;
607}
68c2c39a 608EXPORT_SYMBOL_GPL(xen_irq_from_gsi);
d46a78b0 609
96d4c588
DV
610static void __unbind_from_irq(unsigned int irq)
611{
96d4c588
DV
612 int evtchn = evtchn_from_irq(irq);
613 struct irq_info *info = irq_get_handler_data(irq);
614
615 if (info->refcnt > 0) {
616 info->refcnt--;
617 if (info->refcnt != 0)
618 return;
619 }
620
621 if (VALID_EVTCHN(evtchn)) {
d0b075ff
DV
622 unsigned int cpu = cpu_from_irq(irq);
623
624 xen_evtchn_close(evtchn);
96d4c588
DV
625
626 switch (type_from_irq(irq)) {
627 case IRQT_VIRQ:
d0b075ff 628 per_cpu(virq_to_irq, cpu)[virq_from_irq(irq)] = -1;
96d4c588
DV
629 break;
630 case IRQT_IPI:
d0b075ff 631 per_cpu(ipi_to_irq, cpu)[ipi_from_irq(irq)] = -1;
96d4c588
DV
632 break;
633 default:
634 break;
635 }
636
d0b075ff 637 xen_irq_info_cleanup(info);
96d4c588
DV
638 }
639
640 BUG_ON(info_for_irq(irq)->type == IRQT_UNBOUND);
641
642 xen_free_irq(irq);
643}
644
653378ac
IC
645/*
646 * Do not make any assumptions regarding the relationship between the
647 * IRQ number returned here and the Xen pirq argument.
7a043f11
SS
648 *
649 * Note: We don't assign an event channel until the irq actually started
650 * up. Return an existing irq if we've already got one for the gsi.
e5ac0bda
SS
651 *
652 * Shareable implies level triggered, not shareable implies edge
653 * triggered here.
d46a78b0 654 */
f4d0635b
IC
655int xen_bind_pirq_gsi_to_irq(unsigned gsi,
656 unsigned pirq, int shareable, char *name)
d46a78b0 657{
a0e18116 658 int irq = -1;
d46a78b0 659 struct physdev_irq irq_op;
96d4c588 660 int ret;
d46a78b0 661
77365948 662 mutex_lock(&irq_mapping_update_lock);
d46a78b0 663
68c2c39a 664 irq = xen_irq_from_gsi(gsi);
d46a78b0 665 if (irq != -1) {
283c0972
JP
666 pr_info("%s: returning irq %d for gsi %u\n",
667 __func__, irq, gsi);
420eb554 668 goto out;
d46a78b0
JF
669 }
670
c9df1ce5 671 irq = xen_allocate_irq_gsi(gsi);
7bee9768
IC
672 if (irq < 0)
673 goto out;
d46a78b0 674
d46a78b0 675 irq_op.irq = irq;
b5401a96
AN
676 irq_op.vector = 0;
677
678 /* Only the privileged domain can do this. For non-priv, the pcifront
679 * driver provides a PCI bus that does the call to do exactly
680 * this in the priv domain. */
681 if (xen_initial_domain() &&
682 HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
c9df1ce5 683 xen_free_irq(irq);
d46a78b0
JF
684 irq = -ENOSPC;
685 goto out;
686 }
687
96d4c588 688 ret = xen_irq_info_pirq_setup(irq, 0, pirq, gsi, DOMID_SELF,
9158c358 689 shareable ? PIRQ_SHAREABLE : 0);
96d4c588
DV
690 if (ret < 0) {
691 __unbind_from_irq(irq);
692 irq = ret;
693 goto out;
694 }
d46a78b0 695
7e186bdd
SS
696 pirq_query_unmask(irq);
697 /* We try to use the handler with the appropriate semantic for the
e5ac0bda
SS
698 * type of interrupt: if the interrupt is an edge triggered
699 * interrupt we use handle_edge_irq.
7e186bdd 700 *
e5ac0bda
SS
701 * On the other hand if the interrupt is level triggered we use
702 * handle_fasteoi_irq like the native code does for this kind of
7e186bdd 703 * interrupts.
e5ac0bda 704 *
7e186bdd
SS
705 * Depending on the Xen version, pirq_needs_eoi might return true
706 * not only for level triggered interrupts but for edge triggered
707 * interrupts too. In any case Xen always honors the eoi mechanism,
708 * not injecting any more pirqs of the same kind if the first one
709 * hasn't received an eoi yet. Therefore using the fasteoi handler
710 * is the right choice either way.
711 */
e5ac0bda 712 if (shareable)
7e186bdd
SS
713 irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
714 handle_fasteoi_irq, name);
715 else
716 irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
717 handle_edge_irq, name);
718
d46a78b0 719out:
77365948 720 mutex_unlock(&irq_mapping_update_lock);
d46a78b0
JF
721
722 return irq;
723}
724
f731e3ef 725#ifdef CONFIG_PCI_MSI
bf480d95 726int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc)
cbf6aa89 727{
5cad61a6 728 int rc;
cbf6aa89 729 struct physdev_get_free_pirq op_get_free_pirq;
cbf6aa89 730
bf480d95 731 op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI;
cbf6aa89 732 rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
cbf6aa89 733
5cad61a6
IC
734 WARN_ONCE(rc == -ENOSYS,
735 "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n");
736
737 return rc ? -1 : op_get_free_pirq.pirq;
cbf6aa89
IC
738}
739
bf480d95 740int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc,
dec02dea 741 int pirq, const char *name, domid_t domid)
809f9267 742{
bf480d95 743 int irq, ret;
4b41df7f 744
77365948 745 mutex_lock(&irq_mapping_update_lock);
809f9267 746
4b41df7f 747 irq = xen_allocate_irq_dynamic();
e6599225 748 if (irq < 0)
bb5d079a 749 goto out;
809f9267 750
7e186bdd
SS
751 irq_set_chip_and_handler_name(irq, &xen_pirq_chip, handle_edge_irq,
752 name);
809f9267 753
96d4c588
DV
754 ret = xen_irq_info_pirq_setup(irq, 0, pirq, 0, domid, 0);
755 if (ret < 0)
756 goto error_irq;
5f6fb454 757 ret = irq_set_msi_desc(irq, msidesc);
bf480d95
IC
758 if (ret < 0)
759 goto error_irq;
809f9267 760out:
77365948 761 mutex_unlock(&irq_mapping_update_lock);
4b41df7f 762 return irq;
bf480d95 763error_irq:
96d4c588 764 __unbind_from_irq(irq);
77365948 765 mutex_unlock(&irq_mapping_update_lock);
e6599225 766 return ret;
809f9267 767}
f731e3ef
QH
768#endif
769
b5401a96
AN
770int xen_destroy_irq(int irq)
771{
772 struct irq_desc *desc;
38aa66fc
JF
773 struct physdev_unmap_pirq unmap_irq;
774 struct irq_info *info = info_for_irq(irq);
b5401a96
AN
775 int rc = -ENOENT;
776
77365948 777 mutex_lock(&irq_mapping_update_lock);
b5401a96
AN
778
779 desc = irq_to_desc(irq);
780 if (!desc)
781 goto out;
782
38aa66fc 783 if (xen_initial_domain()) {
12334715 784 unmap_irq.pirq = info->u.pirq.pirq;
beafbdc1 785 unmap_irq.domid = info->u.pirq.domid;
38aa66fc 786 rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
1eff1ad0
KRW
787 /* If another domain quits without making the pci_disable_msix
788 * call, the Xen hypervisor takes care of freeing the PIRQs
789 * (free_domain_pirqs).
790 */
791 if ((rc == -ESRCH && info->u.pirq.domid != DOMID_SELF))
283c0972 792 pr_info("domain %d does not have %d anymore\n",
1eff1ad0
KRW
793 info->u.pirq.domid, info->u.pirq.pirq);
794 else if (rc) {
283c0972 795 pr_warn("unmap irq failed %d\n", rc);
38aa66fc
JF
796 goto out;
797 }
798 }
b5401a96 799
c9df1ce5 800 xen_free_irq(irq);
b5401a96
AN
801
802out:
77365948 803 mutex_unlock(&irq_mapping_update_lock);
b5401a96
AN
804 return rc;
805}
806
af42b8d1 807int xen_irq_from_pirq(unsigned pirq)
d46a78b0 808{
69c358ce 809 int irq;
d46a78b0 810
69c358ce 811 struct irq_info *info;
e46cdb66 812
77365948 813 mutex_lock(&irq_mapping_update_lock);
69c358ce
IC
814
815 list_for_each_entry(info, &xen_irq_list_head, list) {
9bb9efe4 816 if (info->type != IRQT_PIRQ)
69c358ce
IC
817 continue;
818 irq = info->irq;
819 if (info->u.pirq.pirq == pirq)
820 goto out;
821 }
822 irq = -1;
823out:
77365948 824 mutex_unlock(&irq_mapping_update_lock);
69c358ce
IC
825
826 return irq;
af42b8d1
SS
827}
828
e6197acc
KRW
829
830int xen_pirq_from_irq(unsigned irq)
831{
832 return pirq_from_irq(irq);
833}
834EXPORT_SYMBOL_GPL(xen_pirq_from_irq);
96d4c588 835
b536b4b9 836int bind_evtchn_to_irq(unsigned int evtchn)
e46cdb66
JF
837{
838 int irq;
96d4c588 839 int ret;
e46cdb66 840
d0b075ff
DV
841 if (evtchn >= xen_evtchn_max_channels())
842 return -ENOMEM;
843
77365948 844 mutex_lock(&irq_mapping_update_lock);
e46cdb66 845
d0b075ff 846 irq = get_evtchn_to_irq(evtchn);
e46cdb66
JF
847
848 if (irq == -1) {
c9df1ce5 849 irq = xen_allocate_irq_dynamic();
68ba45ff 850 if (irq < 0)
7bee9768 851 goto out;
e46cdb66 852
c442b806 853 irq_set_chip_and_handler_name(irq, &xen_dynamic_chip,
7e186bdd 854 handle_edge_irq, "event");
e46cdb66 855
96d4c588
DV
856 ret = xen_irq_info_evtchn_setup(irq, evtchn);
857 if (ret < 0) {
858 __unbind_from_irq(irq);
859 irq = ret;
860 goto out;
861 }
97253eee
DV
862 /* New interdomain events are bound to VCPU 0. */
863 bind_evtchn_to_cpu(evtchn, 0);
5e152e6c
KRW
864 } else {
865 struct irq_info *info = info_for_irq(irq);
866 WARN_ON(info == NULL || info->type != IRQT_EVTCHN);
e46cdb66
JF
867 }
868
7bee9768 869out:
77365948 870 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
871
872 return irq;
873}
b536b4b9 874EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
e46cdb66 875
f87e4cac
JF
876static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
877{
878 struct evtchn_bind_ipi bind_ipi;
879 int evtchn, irq;
96d4c588 880 int ret;
f87e4cac 881
77365948 882 mutex_lock(&irq_mapping_update_lock);
f87e4cac
JF
883
884 irq = per_cpu(ipi_to_irq, cpu)[ipi];
90af9514 885
f87e4cac 886 if (irq == -1) {
c9df1ce5 887 irq = xen_allocate_irq_dynamic();
f87e4cac
JF
888 if (irq < 0)
889 goto out;
890
c442b806 891 irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
aaca4964 892 handle_percpu_irq, "ipi");
f87e4cac
JF
893
894 bind_ipi.vcpu = cpu;
895 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
896 &bind_ipi) != 0)
897 BUG();
898 evtchn = bind_ipi.port;
899
96d4c588
DV
900 ret = xen_irq_info_ipi_setup(cpu, irq, evtchn, ipi);
901 if (ret < 0) {
902 __unbind_from_irq(irq);
903 irq = ret;
904 goto out;
905 }
f87e4cac 906 bind_evtchn_to_cpu(evtchn, cpu);
5e152e6c
KRW
907 } else {
908 struct irq_info *info = info_for_irq(irq);
909 WARN_ON(info == NULL || info->type != IRQT_IPI);
f87e4cac
JF
910 }
911
f87e4cac 912 out:
77365948 913 mutex_unlock(&irq_mapping_update_lock);
f87e4cac
JF
914 return irq;
915}
916
2e820f58
IC
917static int bind_interdomain_evtchn_to_irq(unsigned int remote_domain,
918 unsigned int remote_port)
919{
920 struct evtchn_bind_interdomain bind_interdomain;
921 int err;
922
923 bind_interdomain.remote_dom = remote_domain;
924 bind_interdomain.remote_port = remote_port;
925
926 err = HYPERVISOR_event_channel_op(EVTCHNOP_bind_interdomain,
927 &bind_interdomain);
928
929 return err ? : bind_evtchn_to_irq(bind_interdomain.local_port);
930}
931
62cc5fc7
OH
932static int find_virq(unsigned int virq, unsigned int cpu)
933{
934 struct evtchn_status status;
935 int port, rc = -ENOENT;
936
937 memset(&status, 0, sizeof(status));
d0b075ff 938 for (port = 0; port < xen_evtchn_max_channels(); port++) {
62cc5fc7
OH
939 status.dom = DOMID_SELF;
940 status.port = port;
941 rc = HYPERVISOR_event_channel_op(EVTCHNOP_status, &status);
942 if (rc < 0)
943 continue;
944 if (status.status != EVTCHNSTAT_virq)
945 continue;
946 if (status.u.virq == virq && status.vcpu == cpu) {
947 rc = port;
948 break;
949 }
950 }
951 return rc;
952}
f87e4cac 953
0dc0064a
DV
954/**
955 * xen_evtchn_nr_channels - number of usable event channel ports
956 *
957 * This may be less than the maximum supported by the current
958 * hypervisor ABI. Use xen_evtchn_max_channels() for the maximum
959 * supported.
960 */
961unsigned xen_evtchn_nr_channels(void)
962{
963 return evtchn_ops->nr_channels();
964}
965EXPORT_SYMBOL_GPL(xen_evtchn_nr_channels);
966
4fe7d5a7 967int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
e46cdb66
JF
968{
969 struct evtchn_bind_virq bind_virq;
62cc5fc7 970 int evtchn, irq, ret;
e46cdb66 971
77365948 972 mutex_lock(&irq_mapping_update_lock);
e46cdb66
JF
973
974 irq = per_cpu(virq_to_irq, cpu)[virq];
975
976 if (irq == -1) {
c9df1ce5 977 irq = xen_allocate_irq_dynamic();
68ba45ff 978 if (irq < 0)
7bee9768 979 goto out;
a52521f1 980
c442b806 981 irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
a52521f1
JF
982 handle_percpu_irq, "virq");
983
e46cdb66
JF
984 bind_virq.virq = virq;
985 bind_virq.vcpu = cpu;
62cc5fc7
OH
986 ret = HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
987 &bind_virq);
988 if (ret == 0)
989 evtchn = bind_virq.port;
990 else {
991 if (ret == -EEXIST)
992 ret = find_virq(virq, cpu);
993 BUG_ON(ret < 0);
994 evtchn = ret;
995 }
e46cdb66 996
96d4c588
DV
997 ret = xen_irq_info_virq_setup(cpu, irq, evtchn, virq);
998 if (ret < 0) {
999 __unbind_from_irq(irq);
1000 irq = ret;
1001 goto out;
1002 }
e46cdb66
JF
1003
1004 bind_evtchn_to_cpu(evtchn, cpu);
5e152e6c
KRW
1005 } else {
1006 struct irq_info *info = info_for_irq(irq);
1007 WARN_ON(info == NULL || info->type != IRQT_VIRQ);
e46cdb66
JF
1008 }
1009
7bee9768 1010out:
77365948 1011 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
1012
1013 return irq;
1014}
1015
1016static void unbind_from_irq(unsigned int irq)
1017{
77365948 1018 mutex_lock(&irq_mapping_update_lock);
96d4c588 1019 __unbind_from_irq(irq);
77365948 1020 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
1021}
1022
1023int bind_evtchn_to_irqhandler(unsigned int evtchn,
7c239975 1024 irq_handler_t handler,
e46cdb66
JF
1025 unsigned long irqflags,
1026 const char *devname, void *dev_id)
1027{
361ae8cb 1028 int irq, retval;
e46cdb66
JF
1029
1030 irq = bind_evtchn_to_irq(evtchn);
7bee9768
IC
1031 if (irq < 0)
1032 return irq;
e46cdb66
JF
1033 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1034 if (retval != 0) {
1035 unbind_from_irq(irq);
1036 return retval;
1037 }
1038
1039 return irq;
1040}
1041EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
1042
2e820f58
IC
1043int bind_interdomain_evtchn_to_irqhandler(unsigned int remote_domain,
1044 unsigned int remote_port,
1045 irq_handler_t handler,
1046 unsigned long irqflags,
1047 const char *devname,
1048 void *dev_id)
1049{
1050 int irq, retval;
1051
1052 irq = bind_interdomain_evtchn_to_irq(remote_domain, remote_port);
1053 if (irq < 0)
1054 return irq;
1055
1056 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1057 if (retval != 0) {
1058 unbind_from_irq(irq);
1059 return retval;
1060 }
1061
1062 return irq;
1063}
1064EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irqhandler);
1065
e46cdb66 1066int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
7c239975 1067 irq_handler_t handler,
e46cdb66
JF
1068 unsigned long irqflags, const char *devname, void *dev_id)
1069{
361ae8cb 1070 int irq, retval;
e46cdb66
JF
1071
1072 irq = bind_virq_to_irq(virq, cpu);
7bee9768
IC
1073 if (irq < 0)
1074 return irq;
e46cdb66
JF
1075 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1076 if (retval != 0) {
1077 unbind_from_irq(irq);
1078 return retval;
1079 }
1080
1081 return irq;
1082}
1083EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
1084
f87e4cac
JF
1085int bind_ipi_to_irqhandler(enum ipi_vector ipi,
1086 unsigned int cpu,
1087 irq_handler_t handler,
1088 unsigned long irqflags,
1089 const char *devname,
1090 void *dev_id)
1091{
1092 int irq, retval;
1093
1094 irq = bind_ipi_to_irq(ipi, cpu);
1095 if (irq < 0)
1096 return irq;
1097
9bab0b7f 1098 irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME | IRQF_EARLY_RESUME;
f87e4cac
JF
1099 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1100 if (retval != 0) {
1101 unbind_from_irq(irq);
1102 return retval;
1103 }
1104
1105 return irq;
1106}
1107
e46cdb66
JF
1108void unbind_from_irqhandler(unsigned int irq, void *dev_id)
1109{
94032c50
KRW
1110 struct irq_info *info = irq_get_handler_data(irq);
1111
1112 if (WARN_ON(!info))
1113 return;
e46cdb66
JF
1114 free_irq(irq, dev_id);
1115 unbind_from_irq(irq);
1116}
1117EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
1118
6ccecb0f
DV
1119/**
1120 * xen_set_irq_priority() - set an event channel priority.
1121 * @irq:irq bound to an event channel.
1122 * @priority: priority between XEN_IRQ_PRIORITY_MAX and XEN_IRQ_PRIORITY_MIN.
1123 */
1124int xen_set_irq_priority(unsigned irq, unsigned priority)
1125{
1126 struct evtchn_set_priority set_priority;
1127
1128 set_priority.port = evtchn_from_irq(irq);
1129 set_priority.priority = priority;
1130
1131 return HYPERVISOR_event_channel_op(EVTCHNOP_set_priority,
1132 &set_priority);
1133}
1134EXPORT_SYMBOL_GPL(xen_set_irq_priority);
1135
420eb554
DDG
1136int evtchn_make_refcounted(unsigned int evtchn)
1137{
d0b075ff 1138 int irq = get_evtchn_to_irq(evtchn);
420eb554
DDG
1139 struct irq_info *info;
1140
1141 if (irq == -1)
1142 return -ENOENT;
1143
1144 info = irq_get_handler_data(irq);
1145
1146 if (!info)
1147 return -ENOENT;
1148
1149 WARN_ON(info->refcnt != -1);
1150
1151 info->refcnt = 1;
1152
1153 return 0;
1154}
1155EXPORT_SYMBOL_GPL(evtchn_make_refcounted);
1156
1157int evtchn_get(unsigned int evtchn)
1158{
1159 int irq;
1160 struct irq_info *info;
1161 int err = -ENOENT;
1162
d0b075ff 1163 if (evtchn >= xen_evtchn_max_channels())
c3b3f16d
DDG
1164 return -EINVAL;
1165
420eb554
DDG
1166 mutex_lock(&irq_mapping_update_lock);
1167
d0b075ff 1168 irq = get_evtchn_to_irq(evtchn);
420eb554
DDG
1169 if (irq == -1)
1170 goto done;
1171
1172 info = irq_get_handler_data(irq);
1173
1174 if (!info)
1175 goto done;
1176
1177 err = -EINVAL;
1178 if (info->refcnt <= 0)
1179 goto done;
1180
1181 info->refcnt++;
1182 err = 0;
1183 done:
1184 mutex_unlock(&irq_mapping_update_lock);
1185
1186 return err;
1187}
1188EXPORT_SYMBOL_GPL(evtchn_get);
1189
1190void evtchn_put(unsigned int evtchn)
1191{
d0b075ff 1192 int irq = get_evtchn_to_irq(evtchn);
420eb554
DDG
1193 if (WARN_ON(irq == -1))
1194 return;
1195 unbind_from_irq(irq);
1196}
1197EXPORT_SYMBOL_GPL(evtchn_put);
1198
f87e4cac
JF
1199void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
1200{
6efa20e4
KRW
1201 int irq;
1202
072b2064 1203#ifdef CONFIG_X86
6efa20e4
KRW
1204 if (unlikely(vector == XEN_NMI_VECTOR)) {
1205 int rc = HYPERVISOR_vcpu_op(VCPUOP_send_nmi, cpu, NULL);
1206 if (rc < 0)
1207 printk(KERN_WARNING "Sending nmi to CPU%d failed (rc:%d)\n", cpu, rc);
1208 return;
1209 }
072b2064 1210#endif
6efa20e4 1211 irq = per_cpu(ipi_to_irq, cpu)[vector];
f87e4cac
JF
1212 BUG_ON(irq < 0);
1213 notify_remote_via_irq(irq);
1214}
1215
245b2e70
TH
1216static DEFINE_PER_CPU(unsigned, xed_nesting_count);
1217
38e20b07 1218static void __xen_evtchn_do_upcall(void)
e46cdb66 1219{
780f36d8 1220 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
9a489f45 1221 int cpu = get_cpu();
088c05a8 1222 unsigned count;
e46cdb66 1223
229664be 1224 do {
229664be 1225 vcpu_info->evtchn_upcall_pending = 0;
e46cdb66 1226
b2e4ae69 1227 if (__this_cpu_inc_return(xed_nesting_count) - 1)
229664be 1228 goto out;
e46cdb66 1229
9a489f45 1230 xen_evtchn_handle_events(cpu);
e46cdb66 1231
229664be
JF
1232 BUG_ON(!irqs_disabled());
1233
780f36d8
CL
1234 count = __this_cpu_read(xed_nesting_count);
1235 __this_cpu_write(xed_nesting_count, 0);
183d03cc 1236 } while (count != 1 || vcpu_info->evtchn_upcall_pending);
229664be
JF
1237
1238out:
38e20b07
SY
1239
1240 put_cpu();
1241}
1242
1243void xen_evtchn_do_upcall(struct pt_regs *regs)
1244{
1245 struct pt_regs *old_regs = set_irq_regs(regs);
1246
772aebce 1247 irq_enter();
0ec53ecf 1248#ifdef CONFIG_X86
38e20b07 1249 exit_idle();
0ec53ecf 1250#endif
38e20b07
SY
1251
1252 __xen_evtchn_do_upcall();
1253
3445a8fd
JF
1254 irq_exit();
1255 set_irq_regs(old_regs);
38e20b07 1256}
3445a8fd 1257
38e20b07
SY
1258void xen_hvm_evtchn_do_upcall(void)
1259{
1260 __xen_evtchn_do_upcall();
e46cdb66 1261}
183d03cc 1262EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
e46cdb66 1263
eb1e305f
JF
1264/* Rebind a new event channel to an existing irq. */
1265void rebind_evtchn_irq(int evtchn, int irq)
1266{
d77bbd4d
JF
1267 struct irq_info *info = info_for_irq(irq);
1268
94032c50
KRW
1269 if (WARN_ON(!info))
1270 return;
1271
eb1e305f
JF
1272 /* Make sure the irq is masked, since the new event channel
1273 will also be masked. */
1274 disable_irq(irq);
1275
77365948 1276 mutex_lock(&irq_mapping_update_lock);
eb1e305f
JF
1277
1278 /* After resume the irq<->evtchn mappings are all cleared out */
d0b075ff 1279 BUG_ON(get_evtchn_to_irq(evtchn) != -1);
eb1e305f 1280 /* Expect irq to have been bound before,
d77bbd4d
JF
1281 so there should be a proper type */
1282 BUG_ON(info->type == IRQT_UNBOUND);
eb1e305f 1283
96d4c588 1284 (void)xen_irq_info_evtchn_setup(irq, evtchn);
eb1e305f 1285
77365948 1286 mutex_unlock(&irq_mapping_update_lock);
eb1e305f
JF
1287
1288 /* new event channels are always bound to cpu 0 */
0de26520 1289 irq_set_affinity(irq, cpumask_of(0));
eb1e305f
JF
1290
1291 /* Unmask the event channel. */
1292 enable_irq(irq);
1293}
1294
e46cdb66 1295/* Rebind an evtchn so that it gets delivered to a specific cpu */
d5dedd45 1296static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
e46cdb66
JF
1297{
1298 struct evtchn_bind_vcpu bind_vcpu;
1299 int evtchn = evtchn_from_irq(irq);
4704fe4f 1300 int masked;
e46cdb66 1301
be49472f
IC
1302 if (!VALID_EVTCHN(evtchn))
1303 return -1;
1304
1305 /*
1306 * Events delivered via platform PCI interrupts are always
1307 * routed to vcpu 0 and hence cannot be rebound.
1308 */
1309 if (xen_hvm_domain() && !xen_have_vector_callback)
d5dedd45 1310 return -1;
e46cdb66
JF
1311
1312 /* Send future instances of this interrupt to other vcpu. */
1313 bind_vcpu.port = evtchn;
1314 bind_vcpu.vcpu = tcpu;
1315
4704fe4f
DV
1316 /*
1317 * Mask the event while changing the VCPU binding to prevent
1318 * it being delivered on an unexpected VCPU.
1319 */
3f70fa82 1320 masked = test_and_set_mask(evtchn);
4704fe4f 1321
e46cdb66
JF
1322 /*
1323 * If this fails, it usually just indicates that we're dealing with a
1324 * virq or IPI channel, which don't actually need to be rebound. Ignore
1325 * it, but don't do the xenlinux-level rebind in that case.
1326 */
1327 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
1328 bind_evtchn_to_cpu(evtchn, tcpu);
e46cdb66 1329
4704fe4f
DV
1330 if (!masked)
1331 unmask_evtchn(evtchn);
1332
d5dedd45
YL
1333 return 0;
1334}
e46cdb66 1335
c9e265e0
TG
1336static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest,
1337 bool force)
e46cdb66 1338{
0de26520 1339 unsigned tcpu = cpumask_first(dest);
d5dedd45 1340
c9e265e0 1341 return rebind_irq_to_cpu(data->irq, tcpu);
e46cdb66
JF
1342}
1343
87295185 1344static int retrigger_evtchn(int evtchn)
642e0c88 1345{
87295185 1346 int masked;
642e0c88
IY
1347
1348 if (!VALID_EVTCHN(evtchn))
87295185 1349 return 0;
642e0c88 1350
3f70fa82 1351 masked = test_and_set_mask(evtchn);
76ec8d64 1352 set_evtchn(evtchn);
642e0c88
IY
1353 if (!masked)
1354 unmask_evtchn(evtchn);
1355
1356 return 1;
1357}
1358
87295185
DV
1359int resend_irq_on_evtchn(unsigned int irq)
1360{
1361 return retrigger_evtchn(evtchn_from_irq(irq));
1362}
1363
c9e265e0 1364static void enable_dynirq(struct irq_data *data)
e46cdb66 1365{
c9e265e0 1366 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1367
1368 if (VALID_EVTCHN(evtchn))
1369 unmask_evtchn(evtchn);
1370}
1371
c9e265e0 1372static void disable_dynirq(struct irq_data *data)
e46cdb66 1373{
c9e265e0 1374 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1375
1376 if (VALID_EVTCHN(evtchn))
1377 mask_evtchn(evtchn);
1378}
1379
c9e265e0 1380static void ack_dynirq(struct irq_data *data)
e46cdb66 1381{
c9e265e0 1382 int evtchn = evtchn_from_irq(data->irq);
e46cdb66 1383
7e186bdd 1384 irq_move_irq(data);
e46cdb66
JF
1385
1386 if (VALID_EVTCHN(evtchn))
7e186bdd
SS
1387 clear_evtchn(evtchn);
1388}
1389
1390static void mask_ack_dynirq(struct irq_data *data)
1391{
1392 disable_dynirq(data);
1393 ack_dynirq(data);
e46cdb66
JF
1394}
1395
c9e265e0 1396static int retrigger_dynirq(struct irq_data *data)
e46cdb66 1397{
87295185 1398 return retrigger_evtchn(evtchn_from_irq(data->irq));
e46cdb66
JF
1399}
1400
0a85226f 1401static void restore_pirqs(void)
9a069c33
SS
1402{
1403 int pirq, rc, irq, gsi;
1404 struct physdev_map_pirq map_irq;
69c358ce 1405 struct irq_info *info;
9a069c33 1406
69c358ce
IC
1407 list_for_each_entry(info, &xen_irq_list_head, list) {
1408 if (info->type != IRQT_PIRQ)
9a069c33
SS
1409 continue;
1410
69c358ce
IC
1411 pirq = info->u.pirq.pirq;
1412 gsi = info->u.pirq.gsi;
1413 irq = info->irq;
1414
9a069c33
SS
1415 /* save/restore of PT devices doesn't work, so at this point the
1416 * only devices present are GSI based emulated devices */
9a069c33
SS
1417 if (!gsi)
1418 continue;
1419
1420 map_irq.domid = DOMID_SELF;
1421 map_irq.type = MAP_PIRQ_TYPE_GSI;
1422 map_irq.index = gsi;
1423 map_irq.pirq = pirq;
1424
1425 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
1426 if (rc) {
283c0972
JP
1427 pr_warn("xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
1428 gsi, irq, pirq, rc);
9158c358 1429 xen_free_irq(irq);
9a069c33
SS
1430 continue;
1431 }
1432
1433 printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
1434
c9e265e0 1435 __startup_pirq(irq);
9a069c33
SS
1436 }
1437}
1438
0e91398f
JF
1439static void restore_cpu_virqs(unsigned int cpu)
1440{
1441 struct evtchn_bind_virq bind_virq;
1442 int virq, irq, evtchn;
1443
1444 for (virq = 0; virq < NR_VIRQS; virq++) {
1445 if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
1446 continue;
1447
ced40d0f 1448 BUG_ON(virq_from_irq(irq) != virq);
0e91398f
JF
1449
1450 /* Get a new binding from Xen. */
1451 bind_virq.virq = virq;
1452 bind_virq.vcpu = cpu;
1453 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
1454 &bind_virq) != 0)
1455 BUG();
1456 evtchn = bind_virq.port;
1457
1458 /* Record the new mapping. */
96d4c588 1459 (void)xen_irq_info_virq_setup(cpu, irq, evtchn, virq);
0e91398f 1460 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1461 }
1462}
1463
1464static void restore_cpu_ipis(unsigned int cpu)
1465{
1466 struct evtchn_bind_ipi bind_ipi;
1467 int ipi, irq, evtchn;
1468
1469 for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
1470 if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
1471 continue;
1472
ced40d0f 1473 BUG_ON(ipi_from_irq(irq) != ipi);
0e91398f
JF
1474
1475 /* Get a new binding from Xen. */
1476 bind_ipi.vcpu = cpu;
1477 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
1478 &bind_ipi) != 0)
1479 BUG();
1480 evtchn = bind_ipi.port;
1481
1482 /* Record the new mapping. */
96d4c588 1483 (void)xen_irq_info_ipi_setup(cpu, irq, evtchn, ipi);
0e91398f 1484 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1485 }
1486}
1487
2d9e1e2f
JF
1488/* Clear an irq's pending state, in preparation for polling on it */
1489void xen_clear_irq_pending(int irq)
1490{
1491 int evtchn = evtchn_from_irq(irq);
1492
1493 if (VALID_EVTCHN(evtchn))
1494 clear_evtchn(evtchn);
1495}
d9a8814f 1496EXPORT_SYMBOL(xen_clear_irq_pending);
168d2f46
JF
1497void xen_set_irq_pending(int irq)
1498{
1499 int evtchn = evtchn_from_irq(irq);
1500
1501 if (VALID_EVTCHN(evtchn))
1502 set_evtchn(evtchn);
1503}
1504
1505bool xen_test_irq_pending(int irq)
1506{
1507 int evtchn = evtchn_from_irq(irq);
1508 bool ret = false;
1509
1510 if (VALID_EVTCHN(evtchn))
1511 ret = test_evtchn(evtchn);
1512
1513 return ret;
1514}
1515
d9a8814f
KRW
1516/* Poll waiting for an irq to become pending with timeout. In the usual case,
1517 * the irq will be disabled so it won't deliver an interrupt. */
1518void xen_poll_irq_timeout(int irq, u64 timeout)
2d9e1e2f
JF
1519{
1520 evtchn_port_t evtchn = evtchn_from_irq(irq);
1521
1522 if (VALID_EVTCHN(evtchn)) {
1523 struct sched_poll poll;
1524
1525 poll.nr_ports = 1;
d9a8814f 1526 poll.timeout = timeout;
ff3c5362 1527 set_xen_guest_handle(poll.ports, &evtchn);
2d9e1e2f
JF
1528
1529 if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
1530 BUG();
1531 }
1532}
d9a8814f
KRW
1533EXPORT_SYMBOL(xen_poll_irq_timeout);
1534/* Poll waiting for an irq to become pending. In the usual case, the
1535 * irq will be disabled so it won't deliver an interrupt. */
1536void xen_poll_irq(int irq)
1537{
1538 xen_poll_irq_timeout(irq, 0 /* no timeout */);
1539}
2d9e1e2f 1540
c7c2c3a2
KRW
1541/* Check whether the IRQ line is shared with other guests. */
1542int xen_test_irq_shared(int irq)
1543{
1544 struct irq_info *info = info_for_irq(irq);
94032c50
KRW
1545 struct physdev_irq_status_query irq_status;
1546
1547 if (WARN_ON(!info))
1548 return -ENOENT;
1549
1550 irq_status.irq = info->u.pirq.pirq;
c7c2c3a2
KRW
1551
1552 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
1553 return 0;
1554 return !(irq_status.flags & XENIRQSTAT_shared);
1555}
1556EXPORT_SYMBOL_GPL(xen_test_irq_shared);
1557
0e91398f
JF
1558void xen_irq_resume(void)
1559{
fd21069d 1560 unsigned int cpu;
6cb6537d 1561 struct irq_info *info;
0e91398f 1562
0e91398f 1563 /* New event-channel space is not 'live' yet. */
fd21069d 1564 xen_evtchn_mask_all();
1fe56551 1565 xen_evtchn_resume();
0e91398f
JF
1566
1567 /* No IRQ <-> event-channel mappings. */
6cb6537d
IC
1568 list_for_each_entry(info, &xen_irq_list_head, list)
1569 info->evtchn = 0; /* zap event-channel binding */
0e91398f 1570
d0b075ff 1571 clear_evtchn_to_irq_all();
0e91398f
JF
1572
1573 for_each_possible_cpu(cpu) {
1574 restore_cpu_virqs(cpu);
1575 restore_cpu_ipis(cpu);
1576 }
6903591f 1577
0a85226f 1578 restore_pirqs();
0e91398f
JF
1579}
1580
e46cdb66 1581static struct irq_chip xen_dynamic_chip __read_mostly = {
c9e265e0 1582 .name = "xen-dyn",
54a353a0 1583
c9e265e0
TG
1584 .irq_disable = disable_dynirq,
1585 .irq_mask = disable_dynirq,
1586 .irq_unmask = enable_dynirq,
54a353a0 1587
7e186bdd
SS
1588 .irq_ack = ack_dynirq,
1589 .irq_mask_ack = mask_ack_dynirq,
1590
c9e265e0
TG
1591 .irq_set_affinity = set_affinity_irq,
1592 .irq_retrigger = retrigger_dynirq,
e46cdb66
JF
1593};
1594
d46a78b0 1595static struct irq_chip xen_pirq_chip __read_mostly = {
c9e265e0 1596 .name = "xen-pirq",
d46a78b0 1597
c9e265e0
TG
1598 .irq_startup = startup_pirq,
1599 .irq_shutdown = shutdown_pirq,
c9e265e0 1600 .irq_enable = enable_pirq,
c9e265e0 1601 .irq_disable = disable_pirq,
d46a78b0 1602
7e186bdd
SS
1603 .irq_mask = disable_dynirq,
1604 .irq_unmask = enable_dynirq,
1605
1606 .irq_ack = eoi_pirq,
1607 .irq_eoi = eoi_pirq,
1608 .irq_mask_ack = mask_ack_pirq,
d46a78b0 1609
c9e265e0 1610 .irq_set_affinity = set_affinity_irq,
d46a78b0 1611
c9e265e0 1612 .irq_retrigger = retrigger_dynirq,
d46a78b0
JF
1613};
1614
aaca4964 1615static struct irq_chip xen_percpu_chip __read_mostly = {
c9e265e0 1616 .name = "xen-percpu",
aaca4964 1617
c9e265e0
TG
1618 .irq_disable = disable_dynirq,
1619 .irq_mask = disable_dynirq,
1620 .irq_unmask = enable_dynirq,
aaca4964 1621
c9e265e0 1622 .irq_ack = ack_dynirq,
aaca4964
JF
1623};
1624
38e20b07
SY
1625int xen_set_callback_via(uint64_t via)
1626{
1627 struct xen_hvm_param a;
1628 a.domid = DOMID_SELF;
1629 a.index = HVM_PARAM_CALLBACK_IRQ;
1630 a.value = via;
1631 return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
1632}
1633EXPORT_SYMBOL_GPL(xen_set_callback_via);
1634
ca65f9fc 1635#ifdef CONFIG_XEN_PVHVM
38e20b07
SY
1636/* Vector callbacks are better than PCI interrupts to receive event
1637 * channel notifications because we can receive vector callbacks on any
1638 * vcpu and we don't need PCI support or APIC interactions. */
1639void xen_callback_vector(void)
1640{
1641 int rc;
1642 uint64_t callback_via;
1643 if (xen_have_vector_callback) {
bc2b0331 1644 callback_via = HVM_CALLBACK_VECTOR(HYPERVISOR_CALLBACK_VECTOR);
38e20b07
SY
1645 rc = xen_set_callback_via(callback_via);
1646 if (rc) {
283c0972 1647 pr_err("Request for Xen HVM callback vector failed\n");
38e20b07
SY
1648 xen_have_vector_callback = 0;
1649 return;
1650 }
283c0972 1651 pr_info("Xen HVM callback vector for event delivery is enabled\n");
38e20b07 1652 /* in the restore case the vector has already been allocated */
bc2b0331
S
1653 if (!test_bit(HYPERVISOR_CALLBACK_VECTOR, used_vectors))
1654 alloc_intr_gate(HYPERVISOR_CALLBACK_VECTOR,
1655 xen_hvm_callback_vector);
38e20b07
SY
1656 }
1657}
ca65f9fc
SS
1658#else
1659void xen_callback_vector(void) {}
1660#endif
38e20b07 1661
1fe56551
DV
1662#undef MODULE_PARAM_PREFIX
1663#define MODULE_PARAM_PREFIX "xen."
1664
1665static bool fifo_events = true;
1666module_param(fifo_events, bool, 0);
1667
2e3d8860 1668void __init xen_init_IRQ(void)
e46cdb66 1669{
1fe56551
DV
1670 int ret = -EINVAL;
1671
1672 if (fifo_events)
1673 ret = xen_evtchn_fifo_init();
1674 if (ret < 0)
1675 xen_evtchn_2l_init();
ab9a1cca 1676
d0b075ff
DV
1677 evtchn_to_irq = kcalloc(EVTCHN_ROW(xen_evtchn_max_channels()),
1678 sizeof(*evtchn_to_irq), GFP_KERNEL);
9d093e29 1679 BUG_ON(!evtchn_to_irq);
e46cdb66 1680
e46cdb66 1681 /* No event channels are 'live' right now. */
fd21069d 1682 xen_evtchn_mask_all();
e46cdb66 1683
9846ff10
SS
1684 pirq_needs_eoi = pirq_needs_eoi_flag;
1685
0ec53ecf 1686#ifdef CONFIG_X86
2771374d
MR
1687 if (xen_pv_domain()) {
1688 irq_ctx_init(smp_processor_id());
1689 if (xen_initial_domain())
1690 pci_xen_initial_domain();
1691 }
1692 if (xen_feature(XENFEAT_hvm_callback_vector))
38e20b07 1693 xen_callback_vector();
2771374d
MR
1694
1695 if (xen_hvm_domain()) {
38e20b07 1696 native_init_IRQ();
3942b740
SS
1697 /* pci_xen_hvm_init must be called after native_init_IRQ so that
1698 * __acpi_register_gsi can point at the right function */
1699 pci_xen_hvm_init();
38e20b07 1700 } else {
0ec53ecf 1701 int rc;
9846ff10
SS
1702 struct physdev_pirq_eoi_gmfn eoi_gmfn;
1703
9846ff10
SS
1704 pirq_eoi_map = (void *)__get_free_page(GFP_KERNEL|__GFP_ZERO);
1705 eoi_gmfn.gmfn = virt_to_mfn(pirq_eoi_map);
1706 rc = HYPERVISOR_physdev_op(PHYSDEVOP_pirq_eoi_gmfn_v2, &eoi_gmfn);
2771374d 1707 /* TODO: No PVH support for PIRQ EOI */
9846ff10
SS
1708 if (rc != 0) {
1709 free_page((unsigned long) pirq_eoi_map);
1710 pirq_eoi_map = NULL;
1711 } else
1712 pirq_needs_eoi = pirq_check_eoi_map;
38e20b07 1713 }
0ec53ecf 1714#endif
e46cdb66 1715}
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