drivers:xen-selfballoon:reset 'frontswap_inertia_counter' after frontswap_shrink
[deliverable/linux.git] / drivers / xen / events / events_base.c
CommitLineData
e46cdb66
JF
1/*
2 * Xen event channels
3 *
4 * Xen models interrupts with abstract event channels. Because each
5 * domain gets 1024 event channels, but NR_IRQ is not that large, we
6 * must dynamically map irqs<->event channels. The event channels
7 * interface with the rest of the kernel by defining a xen interrupt
25985edc 8 * chip. When an event is received, it is mapped to an irq and sent
e46cdb66
JF
9 * through the normal interrupt processing path.
10 *
11 * There are four kinds of events which can be mapped to an event
12 * channel:
13 *
14 * 1. Inter-domain notifications. This includes all the virtual
15 * device events, since they're driven by front-ends in another domain
16 * (typically dom0).
17 * 2. VIRQs, typically used for timers. These are per-cpu events.
18 * 3. IPIs.
d46a78b0 19 * 4. PIRQs - Hardware interrupts.
e46cdb66
JF
20 *
21 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
22 */
23
283c0972
JP
24#define pr_fmt(fmt) "xen:" KBUILD_MODNAME ": " fmt
25
e46cdb66
JF
26#include <linux/linkage.h>
27#include <linux/interrupt.h>
28#include <linux/irq.h>
29#include <linux/module.h>
30#include <linux/string.h>
28e08861 31#include <linux/bootmem.h>
5a0e3ad6 32#include <linux/slab.h>
b21ddbf5 33#include <linux/irqnr.h>
f731e3ef 34#include <linux/pci.h>
e46cdb66 35
0ec53ecf 36#ifdef CONFIG_X86
38e20b07 37#include <asm/desc.h>
e46cdb66
JF
38#include <asm/ptrace.h>
39#include <asm/irq.h>
792dc4f6 40#include <asm/idle.h>
0794bfc7 41#include <asm/io_apic.h>
9846ff10 42#include <asm/xen/page.h>
42a1de56 43#include <asm/xen/pci.h>
0ec53ecf
SS
44#endif
45#include <asm/sync_bitops.h>
e46cdb66 46#include <asm/xen/hypercall.h>
8d1b8753 47#include <asm/xen/hypervisor.h>
e46cdb66 48
38e20b07
SY
49#include <xen/xen.h>
50#include <xen/hvm.h>
e04d0d07 51#include <xen/xen-ops.h>
e46cdb66
JF
52#include <xen/events.h>
53#include <xen/interface/xen.h>
54#include <xen/interface/event_channel.h>
38e20b07
SY
55#include <xen/interface/hvm/hvm_op.h>
56#include <xen/interface/hvm/params.h>
0ec53ecf
SS
57#include <xen/interface/physdev.h>
58#include <xen/interface/sched.h>
6efa20e4 59#include <xen/interface/vcpu.h>
0ec53ecf 60#include <asm/hw_irq.h>
e46cdb66 61
9a489f45
DV
62#include "events_internal.h"
63
ab9a1cca
DV
64const struct evtchn_ops *evtchn_ops;
65
e46cdb66
JF
66/*
67 * This lock protects updates to the following mapping and reference-count
68 * arrays. The lock does not need to be acquired to read the mapping tables.
69 */
77365948 70static DEFINE_MUTEX(irq_mapping_update_lock);
e46cdb66 71
6cb6537d
IC
72static LIST_HEAD(xen_irq_list_head);
73
e46cdb66 74/* IRQ <-> VIRQ mapping. */
204fba4a 75static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
e46cdb66 76
f87e4cac 77/* IRQ <-> IPI mapping */
204fba4a 78static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
f87e4cac 79
d0b075ff 80int **evtchn_to_irq;
bf86ad80 81#ifdef CONFIG_X86
9846ff10 82static unsigned long *pirq_eoi_map;
bf86ad80 83#endif
9846ff10 84static bool (*pirq_needs_eoi)(unsigned irq);
3b32f574 85
d0b075ff
DV
86#define EVTCHN_ROW(e) (e / (PAGE_SIZE/sizeof(**evtchn_to_irq)))
87#define EVTCHN_COL(e) (e % (PAGE_SIZE/sizeof(**evtchn_to_irq)))
88#define EVTCHN_PER_ROW (PAGE_SIZE / sizeof(**evtchn_to_irq))
89
e46cdb66
JF
90/* Xen will never allocate port zero for any purpose. */
91#define VALID_EVTCHN(chn) ((chn) != 0)
92
e46cdb66 93static struct irq_chip xen_dynamic_chip;
aaca4964 94static struct irq_chip xen_percpu_chip;
d46a78b0 95static struct irq_chip xen_pirq_chip;
7e186bdd
SS
96static void enable_dynirq(struct irq_data *data);
97static void disable_dynirq(struct irq_data *data);
e46cdb66 98
d0b075ff
DV
99static void clear_evtchn_to_irq_row(unsigned row)
100{
101 unsigned col;
102
103 for (col = 0; col < EVTCHN_PER_ROW; col++)
104 evtchn_to_irq[row][col] = -1;
105}
106
107static void clear_evtchn_to_irq_all(void)
108{
109 unsigned row;
110
111 for (row = 0; row < EVTCHN_ROW(xen_evtchn_max_channels()); row++) {
112 if (evtchn_to_irq[row] == NULL)
113 continue;
114 clear_evtchn_to_irq_row(row);
115 }
116}
117
118static int set_evtchn_to_irq(unsigned evtchn, unsigned irq)
119{
120 unsigned row;
121 unsigned col;
122
123 if (evtchn >= xen_evtchn_max_channels())
124 return -EINVAL;
125
126 row = EVTCHN_ROW(evtchn);
127 col = EVTCHN_COL(evtchn);
128
129 if (evtchn_to_irq[row] == NULL) {
130 /* Unallocated irq entries return -1 anyway */
131 if (irq == -1)
132 return 0;
133
134 evtchn_to_irq[row] = (int *)get_zeroed_page(GFP_KERNEL);
135 if (evtchn_to_irq[row] == NULL)
136 return -ENOMEM;
137
138 clear_evtchn_to_irq_row(row);
139 }
140
141 evtchn_to_irq[EVTCHN_ROW(evtchn)][EVTCHN_COL(evtchn)] = irq;
142 return 0;
143}
144
145int get_evtchn_to_irq(unsigned evtchn)
146{
147 if (evtchn >= xen_evtchn_max_channels())
148 return -1;
149 if (evtchn_to_irq[EVTCHN_ROW(evtchn)] == NULL)
150 return -1;
151 return evtchn_to_irq[EVTCHN_ROW(evtchn)][EVTCHN_COL(evtchn)];
152}
153
9158c358 154/* Get info for IRQ */
9a489f45 155struct irq_info *info_for_irq(unsigned irq)
ced40d0f 156{
c442b806 157 return irq_get_handler_data(irq);
ced40d0f
JF
158}
159
9158c358 160/* Constructors for packed IRQ information. */
96d4c588 161static int xen_irq_info_common_setup(struct irq_info *info,
3d4cfa37 162 unsigned irq,
9158c358 163 enum xen_irq_type type,
d0b075ff 164 unsigned evtchn,
9158c358 165 unsigned short cpu)
ced40d0f 166{
d0b075ff 167 int ret;
9158c358
IC
168
169 BUG_ON(info->type != IRQT_UNBOUND && info->type != type);
170
171 info->type = type;
6cb6537d 172 info->irq = irq;
9158c358
IC
173 info->evtchn = evtchn;
174 info->cpu = cpu;
3d4cfa37 175
d0b075ff
DV
176 ret = set_evtchn_to_irq(evtchn, irq);
177 if (ret < 0)
178 return ret;
934f585e
JG
179
180 irq_clear_status_flags(irq, IRQ_NOREQUEST|IRQ_NOAUTOEN);
96d4c588 181
08385875 182 return xen_evtchn_port_setup(info);
ced40d0f
JF
183}
184
96d4c588 185static int xen_irq_info_evtchn_setup(unsigned irq,
d0b075ff 186 unsigned evtchn)
ced40d0f 187{
9158c358
IC
188 struct irq_info *info = info_for_irq(irq);
189
96d4c588 190 return xen_irq_info_common_setup(info, irq, IRQT_EVTCHN, evtchn, 0);
ced40d0f
JF
191}
192
96d4c588 193static int xen_irq_info_ipi_setup(unsigned cpu,
3d4cfa37 194 unsigned irq,
d0b075ff 195 unsigned evtchn,
9158c358 196 enum ipi_vector ipi)
e46cdb66 197{
9158c358
IC
198 struct irq_info *info = info_for_irq(irq);
199
9158c358 200 info->u.ipi = ipi;
3d4cfa37
IC
201
202 per_cpu(ipi_to_irq, cpu)[ipi] = irq;
96d4c588
DV
203
204 return xen_irq_info_common_setup(info, irq, IRQT_IPI, evtchn, 0);
ced40d0f
JF
205}
206
96d4c588 207static int xen_irq_info_virq_setup(unsigned cpu,
3d4cfa37 208 unsigned irq,
d0b075ff
DV
209 unsigned evtchn,
210 unsigned virq)
ced40d0f 211{
9158c358
IC
212 struct irq_info *info = info_for_irq(irq);
213
9158c358 214 info->u.virq = virq;
3d4cfa37
IC
215
216 per_cpu(virq_to_irq, cpu)[virq] = irq;
96d4c588
DV
217
218 return xen_irq_info_common_setup(info, irq, IRQT_VIRQ, evtchn, 0);
ced40d0f
JF
219}
220
96d4c588 221static int xen_irq_info_pirq_setup(unsigned irq,
d0b075ff
DV
222 unsigned evtchn,
223 unsigned pirq,
224 unsigned gsi,
beafbdc1 225 uint16_t domid,
9158c358 226 unsigned char flags)
ced40d0f 227{
9158c358
IC
228 struct irq_info *info = info_for_irq(irq);
229
9158c358
IC
230 info->u.pirq.pirq = pirq;
231 info->u.pirq.gsi = gsi;
beafbdc1 232 info->u.pirq.domid = domid;
9158c358 233 info->u.pirq.flags = flags;
96d4c588
DV
234
235 return xen_irq_info_common_setup(info, irq, IRQT_PIRQ, evtchn, 0);
e46cdb66
JF
236}
237
d0b075ff
DV
238static void xen_irq_info_cleanup(struct irq_info *info)
239{
240 set_evtchn_to_irq(info->evtchn, -1);
241 info->evtchn = 0;
242}
243
e46cdb66
JF
244/*
245 * Accessors for packed IRQ information.
246 */
9a489f45 247unsigned int evtchn_from_irq(unsigned irq)
e46cdb66 248{
110e7c7e
JJ
249 if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
250 return 0;
251
ced40d0f 252 return info_for_irq(irq)->evtchn;
e46cdb66
JF
253}
254
d4c04536
IC
255unsigned irq_from_evtchn(unsigned int evtchn)
256{
d0b075ff 257 return get_evtchn_to_irq(evtchn);
d4c04536
IC
258}
259EXPORT_SYMBOL_GPL(irq_from_evtchn);
260
9a489f45
DV
261int irq_from_virq(unsigned int cpu, unsigned int virq)
262{
263 return per_cpu(virq_to_irq, cpu)[virq];
264}
265
ced40d0f 266static enum ipi_vector ipi_from_irq(unsigned irq)
e46cdb66 267{
ced40d0f
JF
268 struct irq_info *info = info_for_irq(irq);
269
270 BUG_ON(info == NULL);
271 BUG_ON(info->type != IRQT_IPI);
272
273 return info->u.ipi;
274}
275
276static unsigned virq_from_irq(unsigned irq)
277{
278 struct irq_info *info = info_for_irq(irq);
279
280 BUG_ON(info == NULL);
281 BUG_ON(info->type != IRQT_VIRQ);
282
283 return info->u.virq;
284}
285
7a043f11
SS
286static unsigned pirq_from_irq(unsigned irq)
287{
288 struct irq_info *info = info_for_irq(irq);
289
290 BUG_ON(info == NULL);
291 BUG_ON(info->type != IRQT_PIRQ);
292
293 return info->u.pirq.pirq;
294}
295
ced40d0f
JF
296static enum xen_irq_type type_from_irq(unsigned irq)
297{
298 return info_for_irq(irq)->type;
299}
300
9a489f45 301unsigned cpu_from_irq(unsigned irq)
ced40d0f
JF
302{
303 return info_for_irq(irq)->cpu;
304}
305
9a489f45 306unsigned int cpu_from_evtchn(unsigned int evtchn)
ced40d0f 307{
d0b075ff 308 int irq = get_evtchn_to_irq(evtchn);
ced40d0f
JF
309 unsigned ret = 0;
310
311 if (irq != -1)
312 ret = cpu_from_irq(irq);
313
314 return ret;
e46cdb66
JF
315}
316
bf86ad80 317#ifdef CONFIG_X86
9846ff10 318static bool pirq_check_eoi_map(unsigned irq)
d46a78b0 319{
521394e4 320 return test_bit(pirq_from_irq(irq), pirq_eoi_map);
9846ff10 321}
bf86ad80 322#endif
d46a78b0 323
9846ff10
SS
324static bool pirq_needs_eoi_flag(unsigned irq)
325{
326 struct irq_info *info = info_for_irq(irq);
d46a78b0
JF
327 BUG_ON(info->type != IRQT_PIRQ);
328
329 return info->u.pirq.flags & PIRQ_NEEDS_EOI;
330}
331
e46cdb66
JF
332static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
333{
d0b075ff 334 int irq = get_evtchn_to_irq(chn);
9a489f45 335 struct irq_info *info = info_for_irq(irq);
e46cdb66
JF
336
337 BUG_ON(irq == -1);
338#ifdef CONFIG_SMP
c9e265e0 339 cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu));
e46cdb66
JF
340#endif
341
9a489f45 342 xen_evtchn_port_bind_to_cpu(info, cpu);
168d2f46 343
9a489f45 344 info->cpu = cpu;
3f70fa82
WL
345}
346
fd21069d
DV
347static void xen_evtchn_mask_all(void)
348{
349 unsigned int evtchn;
350
351 for (evtchn = 0; evtchn < xen_evtchn_nr_channels(); evtchn++)
352 mask_evtchn(evtchn);
353}
354
e46cdb66
JF
355/**
356 * notify_remote_via_irq - send event to remote end of event channel via irq
357 * @irq: irq of event channel to send event to
358 *
359 * Unlike notify_remote_via_evtchn(), this is safe to use across
360 * save/restore. Notifications on a broken connection are silently
361 * dropped.
362 */
363void notify_remote_via_irq(int irq)
364{
365 int evtchn = evtchn_from_irq(irq);
366
367 if (VALID_EVTCHN(evtchn))
368 notify_remote_via_evtchn(evtchn);
369}
370EXPORT_SYMBOL_GPL(notify_remote_via_irq);
371
6cb6537d
IC
372static void xen_irq_init(unsigned irq)
373{
374 struct irq_info *info;
b5328cd1 375#ifdef CONFIG_SMP
6cb6537d
IC
376 struct irq_desc *desc = irq_to_desc(irq);
377
378 /* By default all event channels notify CPU#0. */
379 cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
44626e4a 380#endif
6cb6537d 381
ca62ce8c
IC
382 info = kzalloc(sizeof(*info), GFP_KERNEL);
383 if (info == NULL)
384 panic("Unable to allocate metadata for IRQ%d\n", irq);
6cb6537d
IC
385
386 info->type = IRQT_UNBOUND;
420eb554 387 info->refcnt = -1;
6cb6537d 388
c442b806 389 irq_set_handler_data(irq, info);
ca62ce8c 390
6cb6537d
IC
391 list_add_tail(&info->list, &xen_irq_list_head);
392}
393
7bee9768 394static int __must_check xen_allocate_irq_dynamic(void)
0794bfc7 395{
89911501
IC
396 int first = 0;
397 int irq;
0794bfc7
KRW
398
399#ifdef CONFIG_X86_IO_APIC
89911501
IC
400 /*
401 * For an HVM guest or domain 0 which see "real" (emulated or
25985edc 402 * actual respectively) GSIs we allocate dynamic IRQs
89911501
IC
403 * e.g. those corresponding to event channels or MSIs
404 * etc. from the range above those "real" GSIs to avoid
405 * collisions.
406 */
407 if (xen_initial_domain() || xen_hvm_domain())
408 first = get_nr_irqs_gsi();
0794bfc7
KRW
409#endif
410
89911501 411 irq = irq_alloc_desc_from(first, -1);
3a69e916 412
e6599225
KRW
413 if (irq >= 0)
414 xen_irq_init(irq);
ced40d0f 415
e46cdb66 416 return irq;
d46a78b0
JF
417}
418
7bee9768 419static int __must_check xen_allocate_irq_gsi(unsigned gsi)
c9df1ce5
IC
420{
421 int irq;
422
89911501
IC
423 /*
424 * A PV guest has no concept of a GSI (since it has no ACPI
425 * nor access to/knowledge of the physical APICs). Therefore
426 * all IRQs are dynamically allocated from the entire IRQ
427 * space.
428 */
429 if (xen_pv_domain() && !xen_initial_domain())
c9df1ce5
IC
430 return xen_allocate_irq_dynamic();
431
432 /* Legacy IRQ descriptors are already allocated by the arch. */
433 if (gsi < NR_IRQS_LEGACY)
6cb6537d
IC
434 irq = gsi;
435 else
436 irq = irq_alloc_desc_at(gsi, -1);
c9df1ce5 437
6cb6537d 438 xen_irq_init(irq);
c9df1ce5
IC
439
440 return irq;
441}
442
443static void xen_free_irq(unsigned irq)
444{
c442b806 445 struct irq_info *info = irq_get_handler_data(irq);
6cb6537d 446
94032c50
KRW
447 if (WARN_ON(!info))
448 return;
449
6cb6537d 450 list_del(&info->list);
9158c358 451
c442b806 452 irq_set_handler_data(irq, NULL);
ca62ce8c 453
420eb554
DDG
454 WARN_ON(info->refcnt > 0);
455
ca62ce8c
IC
456 kfree(info);
457
72146104
IC
458 /* Legacy IRQ descriptors are managed by the arch. */
459 if (irq < NR_IRQS_LEGACY)
460 return;
461
c9df1ce5
IC
462 irq_free_desc(irq);
463}
464
d0b075ff
DV
465static void xen_evtchn_close(unsigned int port)
466{
467 struct evtchn_close close;
468
469 close.port = port;
470 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
471 BUG();
472
473 /* Closed ports are implicitly re-bound to VCPU0. */
474 bind_evtchn_to_cpu(port, 0);
475}
476
d46a78b0
JF
477static void pirq_query_unmask(int irq)
478{
479 struct physdev_irq_status_query irq_status;
480 struct irq_info *info = info_for_irq(irq);
481
482 BUG_ON(info->type != IRQT_PIRQ);
483
7a043f11 484 irq_status.irq = pirq_from_irq(irq);
d46a78b0
JF
485 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
486 irq_status.flags = 0;
487
488 info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
489 if (irq_status.flags & XENIRQSTAT_needs_eoi)
490 info->u.pirq.flags |= PIRQ_NEEDS_EOI;
491}
492
493static bool probing_irq(int irq)
494{
495 struct irq_desc *desc = irq_to_desc(irq);
496
497 return desc && desc->action == NULL;
498}
499
7e186bdd
SS
500static void eoi_pirq(struct irq_data *data)
501{
502 int evtchn = evtchn_from_irq(data->irq);
503 struct physdev_eoi eoi = { .irq = pirq_from_irq(data->irq) };
504 int rc = 0;
505
506 irq_move_irq(data);
507
508 if (VALID_EVTCHN(evtchn))
509 clear_evtchn(evtchn);
510
511 if (pirq_needs_eoi(data->irq)) {
512 rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
513 WARN_ON(rc);
514 }
515}
516
517static void mask_ack_pirq(struct irq_data *data)
518{
519 disable_dynirq(data);
520 eoi_pirq(data);
521}
522
c9e265e0 523static unsigned int __startup_pirq(unsigned int irq)
d46a78b0
JF
524{
525 struct evtchn_bind_pirq bind_pirq;
526 struct irq_info *info = info_for_irq(irq);
527 int evtchn = evtchn_from_irq(irq);
15ebbb82 528 int rc;
d46a78b0
JF
529
530 BUG_ON(info->type != IRQT_PIRQ);
531
532 if (VALID_EVTCHN(evtchn))
533 goto out;
534
7a043f11 535 bind_pirq.pirq = pirq_from_irq(irq);
d46a78b0 536 /* NB. We are happy to share unless we are probing. */
15ebbb82
KRW
537 bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
538 BIND_PIRQ__WILL_SHARE : 0;
539 rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
540 if (rc != 0) {
d46a78b0 541 if (!probing_irq(irq))
283c0972 542 pr_info("Failed to obtain physical IRQ %d\n", irq);
d46a78b0
JF
543 return 0;
544 }
545 evtchn = bind_pirq.port;
546
547 pirq_query_unmask(irq);
548
d0b075ff
DV
549 rc = set_evtchn_to_irq(evtchn, irq);
550 if (rc != 0) {
551 pr_err("irq%d: Failed to set port to irq mapping (%d)\n",
552 irq, rc);
553 xen_evtchn_close(evtchn);
554 return 0;
555 }
d46a78b0
JF
556 bind_evtchn_to_cpu(evtchn, 0);
557 info->evtchn = evtchn;
558
559out:
560 unmask_evtchn(evtchn);
7e186bdd 561 eoi_pirq(irq_get_irq_data(irq));
d46a78b0
JF
562
563 return 0;
564}
565
c9e265e0
TG
566static unsigned int startup_pirq(struct irq_data *data)
567{
568 return __startup_pirq(data->irq);
569}
570
571static void shutdown_pirq(struct irq_data *data)
d46a78b0 572{
c9e265e0 573 unsigned int irq = data->irq;
d46a78b0 574 struct irq_info *info = info_for_irq(irq);
d0b075ff 575 unsigned evtchn = evtchn_from_irq(irq);
d46a78b0
JF
576
577 BUG_ON(info->type != IRQT_PIRQ);
578
579 if (!VALID_EVTCHN(evtchn))
580 return;
581
582 mask_evtchn(evtchn);
d0b075ff
DV
583 xen_evtchn_close(evtchn);
584 xen_irq_info_cleanup(info);
d46a78b0
JF
585}
586
c9e265e0 587static void enable_pirq(struct irq_data *data)
d46a78b0 588{
c9e265e0 589 startup_pirq(data);
d46a78b0
JF
590}
591
c9e265e0 592static void disable_pirq(struct irq_data *data)
d46a78b0 593{
7e186bdd 594 disable_dynirq(data);
d46a78b0
JF
595}
596
68c2c39a 597int xen_irq_from_gsi(unsigned gsi)
d46a78b0 598{
6cb6537d 599 struct irq_info *info;
d46a78b0 600
6cb6537d
IC
601 list_for_each_entry(info, &xen_irq_list_head, list) {
602 if (info->type != IRQT_PIRQ)
d46a78b0
JF
603 continue;
604
6cb6537d
IC
605 if (info->u.pirq.gsi == gsi)
606 return info->irq;
d46a78b0
JF
607 }
608
609 return -1;
610}
68c2c39a 611EXPORT_SYMBOL_GPL(xen_irq_from_gsi);
d46a78b0 612
96d4c588
DV
613static void __unbind_from_irq(unsigned int irq)
614{
96d4c588
DV
615 int evtchn = evtchn_from_irq(irq);
616 struct irq_info *info = irq_get_handler_data(irq);
617
618 if (info->refcnt > 0) {
619 info->refcnt--;
620 if (info->refcnt != 0)
621 return;
622 }
623
624 if (VALID_EVTCHN(evtchn)) {
d0b075ff
DV
625 unsigned int cpu = cpu_from_irq(irq);
626
627 xen_evtchn_close(evtchn);
96d4c588
DV
628
629 switch (type_from_irq(irq)) {
630 case IRQT_VIRQ:
d0b075ff 631 per_cpu(virq_to_irq, cpu)[virq_from_irq(irq)] = -1;
96d4c588
DV
632 break;
633 case IRQT_IPI:
d0b075ff 634 per_cpu(ipi_to_irq, cpu)[ipi_from_irq(irq)] = -1;
96d4c588
DV
635 break;
636 default:
637 break;
638 }
639
d0b075ff 640 xen_irq_info_cleanup(info);
96d4c588
DV
641 }
642
643 BUG_ON(info_for_irq(irq)->type == IRQT_UNBOUND);
644
645 xen_free_irq(irq);
646}
647
653378ac
IC
648/*
649 * Do not make any assumptions regarding the relationship between the
650 * IRQ number returned here and the Xen pirq argument.
7a043f11
SS
651 *
652 * Note: We don't assign an event channel until the irq actually started
653 * up. Return an existing irq if we've already got one for the gsi.
e5ac0bda
SS
654 *
655 * Shareable implies level triggered, not shareable implies edge
656 * triggered here.
d46a78b0 657 */
f4d0635b
IC
658int xen_bind_pirq_gsi_to_irq(unsigned gsi,
659 unsigned pirq, int shareable, char *name)
d46a78b0 660{
a0e18116 661 int irq = -1;
d46a78b0 662 struct physdev_irq irq_op;
96d4c588 663 int ret;
d46a78b0 664
77365948 665 mutex_lock(&irq_mapping_update_lock);
d46a78b0 666
68c2c39a 667 irq = xen_irq_from_gsi(gsi);
d46a78b0 668 if (irq != -1) {
283c0972
JP
669 pr_info("%s: returning irq %d for gsi %u\n",
670 __func__, irq, gsi);
420eb554 671 goto out;
d46a78b0
JF
672 }
673
c9df1ce5 674 irq = xen_allocate_irq_gsi(gsi);
7bee9768
IC
675 if (irq < 0)
676 goto out;
d46a78b0 677
d46a78b0 678 irq_op.irq = irq;
b5401a96
AN
679 irq_op.vector = 0;
680
681 /* Only the privileged domain can do this. For non-priv, the pcifront
682 * driver provides a PCI bus that does the call to do exactly
683 * this in the priv domain. */
684 if (xen_initial_domain() &&
685 HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
c9df1ce5 686 xen_free_irq(irq);
d46a78b0
JF
687 irq = -ENOSPC;
688 goto out;
689 }
690
96d4c588 691 ret = xen_irq_info_pirq_setup(irq, 0, pirq, gsi, DOMID_SELF,
9158c358 692 shareable ? PIRQ_SHAREABLE : 0);
96d4c588
DV
693 if (ret < 0) {
694 __unbind_from_irq(irq);
695 irq = ret;
696 goto out;
697 }
d46a78b0 698
7e186bdd
SS
699 pirq_query_unmask(irq);
700 /* We try to use the handler with the appropriate semantic for the
e5ac0bda
SS
701 * type of interrupt: if the interrupt is an edge triggered
702 * interrupt we use handle_edge_irq.
7e186bdd 703 *
e5ac0bda
SS
704 * On the other hand if the interrupt is level triggered we use
705 * handle_fasteoi_irq like the native code does for this kind of
7e186bdd 706 * interrupts.
e5ac0bda 707 *
7e186bdd
SS
708 * Depending on the Xen version, pirq_needs_eoi might return true
709 * not only for level triggered interrupts but for edge triggered
710 * interrupts too. In any case Xen always honors the eoi mechanism,
711 * not injecting any more pirqs of the same kind if the first one
712 * hasn't received an eoi yet. Therefore using the fasteoi handler
713 * is the right choice either way.
714 */
e5ac0bda 715 if (shareable)
7e186bdd
SS
716 irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
717 handle_fasteoi_irq, name);
718 else
719 irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
720 handle_edge_irq, name);
721
d46a78b0 722out:
77365948 723 mutex_unlock(&irq_mapping_update_lock);
d46a78b0
JF
724
725 return irq;
726}
727
f731e3ef 728#ifdef CONFIG_PCI_MSI
bf480d95 729int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc)
cbf6aa89 730{
5cad61a6 731 int rc;
cbf6aa89 732 struct physdev_get_free_pirq op_get_free_pirq;
cbf6aa89 733
bf480d95 734 op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI;
cbf6aa89 735 rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
cbf6aa89 736
5cad61a6
IC
737 WARN_ONCE(rc == -ENOSYS,
738 "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n");
739
740 return rc ? -1 : op_get_free_pirq.pirq;
cbf6aa89
IC
741}
742
bf480d95 743int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc,
dec02dea 744 int pirq, const char *name, domid_t domid)
809f9267 745{
bf480d95 746 int irq, ret;
4b41df7f 747
77365948 748 mutex_lock(&irq_mapping_update_lock);
809f9267 749
4b41df7f 750 irq = xen_allocate_irq_dynamic();
e6599225 751 if (irq < 0)
bb5d079a 752 goto out;
809f9267 753
7e186bdd
SS
754 irq_set_chip_and_handler_name(irq, &xen_pirq_chip, handle_edge_irq,
755 name);
809f9267 756
96d4c588
DV
757 ret = xen_irq_info_pirq_setup(irq, 0, pirq, 0, domid, 0);
758 if (ret < 0)
759 goto error_irq;
5f6fb454 760 ret = irq_set_msi_desc(irq, msidesc);
bf480d95
IC
761 if (ret < 0)
762 goto error_irq;
809f9267 763out:
77365948 764 mutex_unlock(&irq_mapping_update_lock);
4b41df7f 765 return irq;
bf480d95 766error_irq:
96d4c588 767 __unbind_from_irq(irq);
77365948 768 mutex_unlock(&irq_mapping_update_lock);
e6599225 769 return ret;
809f9267 770}
f731e3ef
QH
771#endif
772
b5401a96
AN
773int xen_destroy_irq(int irq)
774{
775 struct irq_desc *desc;
38aa66fc
JF
776 struct physdev_unmap_pirq unmap_irq;
777 struct irq_info *info = info_for_irq(irq);
b5401a96
AN
778 int rc = -ENOENT;
779
77365948 780 mutex_lock(&irq_mapping_update_lock);
b5401a96
AN
781
782 desc = irq_to_desc(irq);
783 if (!desc)
784 goto out;
785
38aa66fc 786 if (xen_initial_domain()) {
12334715 787 unmap_irq.pirq = info->u.pirq.pirq;
beafbdc1 788 unmap_irq.domid = info->u.pirq.domid;
38aa66fc 789 rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
1eff1ad0
KRW
790 /* If another domain quits without making the pci_disable_msix
791 * call, the Xen hypervisor takes care of freeing the PIRQs
792 * (free_domain_pirqs).
793 */
794 if ((rc == -ESRCH && info->u.pirq.domid != DOMID_SELF))
283c0972 795 pr_info("domain %d does not have %d anymore\n",
1eff1ad0
KRW
796 info->u.pirq.domid, info->u.pirq.pirq);
797 else if (rc) {
283c0972 798 pr_warn("unmap irq failed %d\n", rc);
38aa66fc
JF
799 goto out;
800 }
801 }
b5401a96 802
c9df1ce5 803 xen_free_irq(irq);
b5401a96
AN
804
805out:
77365948 806 mutex_unlock(&irq_mapping_update_lock);
b5401a96
AN
807 return rc;
808}
809
af42b8d1 810int xen_irq_from_pirq(unsigned pirq)
d46a78b0 811{
69c358ce 812 int irq;
d46a78b0 813
69c358ce 814 struct irq_info *info;
e46cdb66 815
77365948 816 mutex_lock(&irq_mapping_update_lock);
69c358ce
IC
817
818 list_for_each_entry(info, &xen_irq_list_head, list) {
9bb9efe4 819 if (info->type != IRQT_PIRQ)
69c358ce
IC
820 continue;
821 irq = info->irq;
822 if (info->u.pirq.pirq == pirq)
823 goto out;
824 }
825 irq = -1;
826out:
77365948 827 mutex_unlock(&irq_mapping_update_lock);
69c358ce
IC
828
829 return irq;
af42b8d1
SS
830}
831
e6197acc
KRW
832
833int xen_pirq_from_irq(unsigned irq)
834{
835 return pirq_from_irq(irq);
836}
837EXPORT_SYMBOL_GPL(xen_pirq_from_irq);
96d4c588 838
b536b4b9 839int bind_evtchn_to_irq(unsigned int evtchn)
e46cdb66
JF
840{
841 int irq;
96d4c588 842 int ret;
e46cdb66 843
d0b075ff
DV
844 if (evtchn >= xen_evtchn_max_channels())
845 return -ENOMEM;
846
77365948 847 mutex_lock(&irq_mapping_update_lock);
e46cdb66 848
d0b075ff 849 irq = get_evtchn_to_irq(evtchn);
e46cdb66
JF
850
851 if (irq == -1) {
c9df1ce5 852 irq = xen_allocate_irq_dynamic();
68ba45ff 853 if (irq < 0)
7bee9768 854 goto out;
e46cdb66 855
c442b806 856 irq_set_chip_and_handler_name(irq, &xen_dynamic_chip,
7e186bdd 857 handle_edge_irq, "event");
e46cdb66 858
96d4c588
DV
859 ret = xen_irq_info_evtchn_setup(irq, evtchn);
860 if (ret < 0) {
861 __unbind_from_irq(irq);
862 irq = ret;
863 goto out;
864 }
97253eee
DV
865 /* New interdomain events are bound to VCPU 0. */
866 bind_evtchn_to_cpu(evtchn, 0);
5e152e6c
KRW
867 } else {
868 struct irq_info *info = info_for_irq(irq);
869 WARN_ON(info == NULL || info->type != IRQT_EVTCHN);
e46cdb66
JF
870 }
871
7bee9768 872out:
77365948 873 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
874
875 return irq;
876}
b536b4b9 877EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
e46cdb66 878
f87e4cac
JF
879static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
880{
881 struct evtchn_bind_ipi bind_ipi;
882 int evtchn, irq;
96d4c588 883 int ret;
f87e4cac 884
77365948 885 mutex_lock(&irq_mapping_update_lock);
f87e4cac
JF
886
887 irq = per_cpu(ipi_to_irq, cpu)[ipi];
90af9514 888
f87e4cac 889 if (irq == -1) {
c9df1ce5 890 irq = xen_allocate_irq_dynamic();
f87e4cac
JF
891 if (irq < 0)
892 goto out;
893
c442b806 894 irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
aaca4964 895 handle_percpu_irq, "ipi");
f87e4cac
JF
896
897 bind_ipi.vcpu = cpu;
898 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
899 &bind_ipi) != 0)
900 BUG();
901 evtchn = bind_ipi.port;
902
96d4c588
DV
903 ret = xen_irq_info_ipi_setup(cpu, irq, evtchn, ipi);
904 if (ret < 0) {
905 __unbind_from_irq(irq);
906 irq = ret;
907 goto out;
908 }
f87e4cac 909 bind_evtchn_to_cpu(evtchn, cpu);
5e152e6c
KRW
910 } else {
911 struct irq_info *info = info_for_irq(irq);
912 WARN_ON(info == NULL || info->type != IRQT_IPI);
f87e4cac
JF
913 }
914
f87e4cac 915 out:
77365948 916 mutex_unlock(&irq_mapping_update_lock);
f87e4cac
JF
917 return irq;
918}
919
2e820f58
IC
920static int bind_interdomain_evtchn_to_irq(unsigned int remote_domain,
921 unsigned int remote_port)
922{
923 struct evtchn_bind_interdomain bind_interdomain;
924 int err;
925
926 bind_interdomain.remote_dom = remote_domain;
927 bind_interdomain.remote_port = remote_port;
928
929 err = HYPERVISOR_event_channel_op(EVTCHNOP_bind_interdomain,
930 &bind_interdomain);
931
932 return err ? : bind_evtchn_to_irq(bind_interdomain.local_port);
933}
934
62cc5fc7
OH
935static int find_virq(unsigned int virq, unsigned int cpu)
936{
937 struct evtchn_status status;
938 int port, rc = -ENOENT;
939
940 memset(&status, 0, sizeof(status));
d0b075ff 941 for (port = 0; port < xen_evtchn_max_channels(); port++) {
62cc5fc7
OH
942 status.dom = DOMID_SELF;
943 status.port = port;
944 rc = HYPERVISOR_event_channel_op(EVTCHNOP_status, &status);
945 if (rc < 0)
946 continue;
947 if (status.status != EVTCHNSTAT_virq)
948 continue;
949 if (status.u.virq == virq && status.vcpu == cpu) {
950 rc = port;
951 break;
952 }
953 }
954 return rc;
955}
f87e4cac 956
0dc0064a
DV
957/**
958 * xen_evtchn_nr_channels - number of usable event channel ports
959 *
960 * This may be less than the maximum supported by the current
961 * hypervisor ABI. Use xen_evtchn_max_channels() for the maximum
962 * supported.
963 */
964unsigned xen_evtchn_nr_channels(void)
965{
966 return evtchn_ops->nr_channels();
967}
968EXPORT_SYMBOL_GPL(xen_evtchn_nr_channels);
969
4fe7d5a7 970int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
e46cdb66
JF
971{
972 struct evtchn_bind_virq bind_virq;
62cc5fc7 973 int evtchn, irq, ret;
e46cdb66 974
77365948 975 mutex_lock(&irq_mapping_update_lock);
e46cdb66
JF
976
977 irq = per_cpu(virq_to_irq, cpu)[virq];
978
979 if (irq == -1) {
c9df1ce5 980 irq = xen_allocate_irq_dynamic();
68ba45ff 981 if (irq < 0)
7bee9768 982 goto out;
a52521f1 983
c442b806 984 irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
a52521f1
JF
985 handle_percpu_irq, "virq");
986
e46cdb66
JF
987 bind_virq.virq = virq;
988 bind_virq.vcpu = cpu;
62cc5fc7
OH
989 ret = HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
990 &bind_virq);
991 if (ret == 0)
992 evtchn = bind_virq.port;
993 else {
994 if (ret == -EEXIST)
995 ret = find_virq(virq, cpu);
996 BUG_ON(ret < 0);
997 evtchn = ret;
998 }
e46cdb66 999
96d4c588
DV
1000 ret = xen_irq_info_virq_setup(cpu, irq, evtchn, virq);
1001 if (ret < 0) {
1002 __unbind_from_irq(irq);
1003 irq = ret;
1004 goto out;
1005 }
e46cdb66
JF
1006
1007 bind_evtchn_to_cpu(evtchn, cpu);
5e152e6c
KRW
1008 } else {
1009 struct irq_info *info = info_for_irq(irq);
1010 WARN_ON(info == NULL || info->type != IRQT_VIRQ);
e46cdb66
JF
1011 }
1012
7bee9768 1013out:
77365948 1014 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
1015
1016 return irq;
1017}
1018
1019static void unbind_from_irq(unsigned int irq)
1020{
77365948 1021 mutex_lock(&irq_mapping_update_lock);
96d4c588 1022 __unbind_from_irq(irq);
77365948 1023 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
1024}
1025
1026int bind_evtchn_to_irqhandler(unsigned int evtchn,
7c239975 1027 irq_handler_t handler,
e46cdb66
JF
1028 unsigned long irqflags,
1029 const char *devname, void *dev_id)
1030{
361ae8cb 1031 int irq, retval;
e46cdb66
JF
1032
1033 irq = bind_evtchn_to_irq(evtchn);
7bee9768
IC
1034 if (irq < 0)
1035 return irq;
e46cdb66
JF
1036 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1037 if (retval != 0) {
1038 unbind_from_irq(irq);
1039 return retval;
1040 }
1041
1042 return irq;
1043}
1044EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
1045
2e820f58
IC
1046int bind_interdomain_evtchn_to_irqhandler(unsigned int remote_domain,
1047 unsigned int remote_port,
1048 irq_handler_t handler,
1049 unsigned long irqflags,
1050 const char *devname,
1051 void *dev_id)
1052{
1053 int irq, retval;
1054
1055 irq = bind_interdomain_evtchn_to_irq(remote_domain, remote_port);
1056 if (irq < 0)
1057 return irq;
1058
1059 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1060 if (retval != 0) {
1061 unbind_from_irq(irq);
1062 return retval;
1063 }
1064
1065 return irq;
1066}
1067EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irqhandler);
1068
e46cdb66 1069int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
7c239975 1070 irq_handler_t handler,
e46cdb66
JF
1071 unsigned long irqflags, const char *devname, void *dev_id)
1072{
361ae8cb 1073 int irq, retval;
e46cdb66
JF
1074
1075 irq = bind_virq_to_irq(virq, cpu);
7bee9768
IC
1076 if (irq < 0)
1077 return irq;
e46cdb66
JF
1078 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1079 if (retval != 0) {
1080 unbind_from_irq(irq);
1081 return retval;
1082 }
1083
1084 return irq;
1085}
1086EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
1087
f87e4cac
JF
1088int bind_ipi_to_irqhandler(enum ipi_vector ipi,
1089 unsigned int cpu,
1090 irq_handler_t handler,
1091 unsigned long irqflags,
1092 const char *devname,
1093 void *dev_id)
1094{
1095 int irq, retval;
1096
1097 irq = bind_ipi_to_irq(ipi, cpu);
1098 if (irq < 0)
1099 return irq;
1100
9bab0b7f 1101 irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME | IRQF_EARLY_RESUME;
f87e4cac
JF
1102 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1103 if (retval != 0) {
1104 unbind_from_irq(irq);
1105 return retval;
1106 }
1107
1108 return irq;
1109}
1110
e46cdb66
JF
1111void unbind_from_irqhandler(unsigned int irq, void *dev_id)
1112{
94032c50
KRW
1113 struct irq_info *info = irq_get_handler_data(irq);
1114
1115 if (WARN_ON(!info))
1116 return;
e46cdb66
JF
1117 free_irq(irq, dev_id);
1118 unbind_from_irq(irq);
1119}
1120EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
1121
6ccecb0f
DV
1122/**
1123 * xen_set_irq_priority() - set an event channel priority.
1124 * @irq:irq bound to an event channel.
1125 * @priority: priority between XEN_IRQ_PRIORITY_MAX and XEN_IRQ_PRIORITY_MIN.
1126 */
1127int xen_set_irq_priority(unsigned irq, unsigned priority)
1128{
1129 struct evtchn_set_priority set_priority;
1130
1131 set_priority.port = evtchn_from_irq(irq);
1132 set_priority.priority = priority;
1133
1134 return HYPERVISOR_event_channel_op(EVTCHNOP_set_priority,
1135 &set_priority);
1136}
1137EXPORT_SYMBOL_GPL(xen_set_irq_priority);
1138
420eb554
DDG
1139int evtchn_make_refcounted(unsigned int evtchn)
1140{
d0b075ff 1141 int irq = get_evtchn_to_irq(evtchn);
420eb554
DDG
1142 struct irq_info *info;
1143
1144 if (irq == -1)
1145 return -ENOENT;
1146
1147 info = irq_get_handler_data(irq);
1148
1149 if (!info)
1150 return -ENOENT;
1151
1152 WARN_ON(info->refcnt != -1);
1153
1154 info->refcnt = 1;
1155
1156 return 0;
1157}
1158EXPORT_SYMBOL_GPL(evtchn_make_refcounted);
1159
1160int evtchn_get(unsigned int evtchn)
1161{
1162 int irq;
1163 struct irq_info *info;
1164 int err = -ENOENT;
1165
d0b075ff 1166 if (evtchn >= xen_evtchn_max_channels())
c3b3f16d
DDG
1167 return -EINVAL;
1168
420eb554
DDG
1169 mutex_lock(&irq_mapping_update_lock);
1170
d0b075ff 1171 irq = get_evtchn_to_irq(evtchn);
420eb554
DDG
1172 if (irq == -1)
1173 goto done;
1174
1175 info = irq_get_handler_data(irq);
1176
1177 if (!info)
1178 goto done;
1179
1180 err = -EINVAL;
1181 if (info->refcnt <= 0)
1182 goto done;
1183
1184 info->refcnt++;
1185 err = 0;
1186 done:
1187 mutex_unlock(&irq_mapping_update_lock);
1188
1189 return err;
1190}
1191EXPORT_SYMBOL_GPL(evtchn_get);
1192
1193void evtchn_put(unsigned int evtchn)
1194{
d0b075ff 1195 int irq = get_evtchn_to_irq(evtchn);
420eb554
DDG
1196 if (WARN_ON(irq == -1))
1197 return;
1198 unbind_from_irq(irq);
1199}
1200EXPORT_SYMBOL_GPL(evtchn_put);
1201
f87e4cac
JF
1202void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
1203{
6efa20e4
KRW
1204 int irq;
1205
072b2064 1206#ifdef CONFIG_X86
6efa20e4
KRW
1207 if (unlikely(vector == XEN_NMI_VECTOR)) {
1208 int rc = HYPERVISOR_vcpu_op(VCPUOP_send_nmi, cpu, NULL);
1209 if (rc < 0)
1210 printk(KERN_WARNING "Sending nmi to CPU%d failed (rc:%d)\n", cpu, rc);
1211 return;
1212 }
072b2064 1213#endif
6efa20e4 1214 irq = per_cpu(ipi_to_irq, cpu)[vector];
f87e4cac
JF
1215 BUG_ON(irq < 0);
1216 notify_remote_via_irq(irq);
1217}
1218
245b2e70
TH
1219static DEFINE_PER_CPU(unsigned, xed_nesting_count);
1220
38e20b07 1221static void __xen_evtchn_do_upcall(void)
e46cdb66 1222{
780f36d8 1223 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
9a489f45 1224 int cpu = get_cpu();
088c05a8 1225 unsigned count;
e46cdb66 1226
229664be 1227 do {
229664be 1228 vcpu_info->evtchn_upcall_pending = 0;
e46cdb66 1229
b2e4ae69 1230 if (__this_cpu_inc_return(xed_nesting_count) - 1)
229664be 1231 goto out;
e46cdb66 1232
9a489f45 1233 xen_evtchn_handle_events(cpu);
e46cdb66 1234
229664be
JF
1235 BUG_ON(!irqs_disabled());
1236
780f36d8
CL
1237 count = __this_cpu_read(xed_nesting_count);
1238 __this_cpu_write(xed_nesting_count, 0);
183d03cc 1239 } while (count != 1 || vcpu_info->evtchn_upcall_pending);
229664be
JF
1240
1241out:
38e20b07
SY
1242
1243 put_cpu();
1244}
1245
1246void xen_evtchn_do_upcall(struct pt_regs *regs)
1247{
1248 struct pt_regs *old_regs = set_irq_regs(regs);
1249
772aebce 1250 irq_enter();
0ec53ecf 1251#ifdef CONFIG_X86
38e20b07 1252 exit_idle();
0ec53ecf 1253#endif
38e20b07
SY
1254
1255 __xen_evtchn_do_upcall();
1256
3445a8fd
JF
1257 irq_exit();
1258 set_irq_regs(old_regs);
38e20b07 1259}
3445a8fd 1260
38e20b07
SY
1261void xen_hvm_evtchn_do_upcall(void)
1262{
1263 __xen_evtchn_do_upcall();
e46cdb66 1264}
183d03cc 1265EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
e46cdb66 1266
eb1e305f
JF
1267/* Rebind a new event channel to an existing irq. */
1268void rebind_evtchn_irq(int evtchn, int irq)
1269{
d77bbd4d
JF
1270 struct irq_info *info = info_for_irq(irq);
1271
94032c50
KRW
1272 if (WARN_ON(!info))
1273 return;
1274
eb1e305f
JF
1275 /* Make sure the irq is masked, since the new event channel
1276 will also be masked. */
1277 disable_irq(irq);
1278
77365948 1279 mutex_lock(&irq_mapping_update_lock);
eb1e305f
JF
1280
1281 /* After resume the irq<->evtchn mappings are all cleared out */
d0b075ff 1282 BUG_ON(get_evtchn_to_irq(evtchn) != -1);
eb1e305f 1283 /* Expect irq to have been bound before,
d77bbd4d
JF
1284 so there should be a proper type */
1285 BUG_ON(info->type == IRQT_UNBOUND);
eb1e305f 1286
96d4c588 1287 (void)xen_irq_info_evtchn_setup(irq, evtchn);
eb1e305f 1288
77365948 1289 mutex_unlock(&irq_mapping_update_lock);
eb1e305f
JF
1290
1291 /* new event channels are always bound to cpu 0 */
0de26520 1292 irq_set_affinity(irq, cpumask_of(0));
eb1e305f
JF
1293
1294 /* Unmask the event channel. */
1295 enable_irq(irq);
1296}
1297
e46cdb66 1298/* Rebind an evtchn so that it gets delivered to a specific cpu */
d5dedd45 1299static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
e46cdb66
JF
1300{
1301 struct evtchn_bind_vcpu bind_vcpu;
1302 int evtchn = evtchn_from_irq(irq);
4704fe4f 1303 int masked;
e46cdb66 1304
be49472f
IC
1305 if (!VALID_EVTCHN(evtchn))
1306 return -1;
1307
1308 /*
1309 * Events delivered via platform PCI interrupts are always
1310 * routed to vcpu 0 and hence cannot be rebound.
1311 */
1312 if (xen_hvm_domain() && !xen_have_vector_callback)
d5dedd45 1313 return -1;
e46cdb66
JF
1314
1315 /* Send future instances of this interrupt to other vcpu. */
1316 bind_vcpu.port = evtchn;
1317 bind_vcpu.vcpu = tcpu;
1318
4704fe4f
DV
1319 /*
1320 * Mask the event while changing the VCPU binding to prevent
1321 * it being delivered on an unexpected VCPU.
1322 */
3f70fa82 1323 masked = test_and_set_mask(evtchn);
4704fe4f 1324
e46cdb66
JF
1325 /*
1326 * If this fails, it usually just indicates that we're dealing with a
1327 * virq or IPI channel, which don't actually need to be rebound. Ignore
1328 * it, but don't do the xenlinux-level rebind in that case.
1329 */
1330 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
1331 bind_evtchn_to_cpu(evtchn, tcpu);
e46cdb66 1332
4704fe4f
DV
1333 if (!masked)
1334 unmask_evtchn(evtchn);
1335
d5dedd45
YL
1336 return 0;
1337}
e46cdb66 1338
c9e265e0
TG
1339static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest,
1340 bool force)
e46cdb66 1341{
0de26520 1342 unsigned tcpu = cpumask_first(dest);
d5dedd45 1343
c9e265e0 1344 return rebind_irq_to_cpu(data->irq, tcpu);
e46cdb66
JF
1345}
1346
87295185 1347static int retrigger_evtchn(int evtchn)
642e0c88 1348{
87295185 1349 int masked;
642e0c88
IY
1350
1351 if (!VALID_EVTCHN(evtchn))
87295185 1352 return 0;
642e0c88 1353
3f70fa82 1354 masked = test_and_set_mask(evtchn);
76ec8d64 1355 set_evtchn(evtchn);
642e0c88
IY
1356 if (!masked)
1357 unmask_evtchn(evtchn);
1358
1359 return 1;
1360}
1361
87295185
DV
1362int resend_irq_on_evtchn(unsigned int irq)
1363{
1364 return retrigger_evtchn(evtchn_from_irq(irq));
1365}
1366
c9e265e0 1367static void enable_dynirq(struct irq_data *data)
e46cdb66 1368{
c9e265e0 1369 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1370
1371 if (VALID_EVTCHN(evtchn))
1372 unmask_evtchn(evtchn);
1373}
1374
c9e265e0 1375static void disable_dynirq(struct irq_data *data)
e46cdb66 1376{
c9e265e0 1377 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1378
1379 if (VALID_EVTCHN(evtchn))
1380 mask_evtchn(evtchn);
1381}
1382
c9e265e0 1383static void ack_dynirq(struct irq_data *data)
e46cdb66 1384{
c9e265e0 1385 int evtchn = evtchn_from_irq(data->irq);
e46cdb66 1386
7e186bdd 1387 irq_move_irq(data);
e46cdb66
JF
1388
1389 if (VALID_EVTCHN(evtchn))
7e186bdd
SS
1390 clear_evtchn(evtchn);
1391}
1392
1393static void mask_ack_dynirq(struct irq_data *data)
1394{
1395 disable_dynirq(data);
1396 ack_dynirq(data);
e46cdb66
JF
1397}
1398
c9e265e0 1399static int retrigger_dynirq(struct irq_data *data)
e46cdb66 1400{
87295185 1401 return retrigger_evtchn(evtchn_from_irq(data->irq));
e46cdb66
JF
1402}
1403
0a85226f 1404static void restore_pirqs(void)
9a069c33
SS
1405{
1406 int pirq, rc, irq, gsi;
1407 struct physdev_map_pirq map_irq;
69c358ce 1408 struct irq_info *info;
9a069c33 1409
69c358ce
IC
1410 list_for_each_entry(info, &xen_irq_list_head, list) {
1411 if (info->type != IRQT_PIRQ)
9a069c33
SS
1412 continue;
1413
69c358ce
IC
1414 pirq = info->u.pirq.pirq;
1415 gsi = info->u.pirq.gsi;
1416 irq = info->irq;
1417
9a069c33
SS
1418 /* save/restore of PT devices doesn't work, so at this point the
1419 * only devices present are GSI based emulated devices */
9a069c33
SS
1420 if (!gsi)
1421 continue;
1422
1423 map_irq.domid = DOMID_SELF;
1424 map_irq.type = MAP_PIRQ_TYPE_GSI;
1425 map_irq.index = gsi;
1426 map_irq.pirq = pirq;
1427
1428 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
1429 if (rc) {
283c0972
JP
1430 pr_warn("xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
1431 gsi, irq, pirq, rc);
9158c358 1432 xen_free_irq(irq);
9a069c33
SS
1433 continue;
1434 }
1435
1436 printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
1437
c9e265e0 1438 __startup_pirq(irq);
9a069c33
SS
1439 }
1440}
1441
0e91398f
JF
1442static void restore_cpu_virqs(unsigned int cpu)
1443{
1444 struct evtchn_bind_virq bind_virq;
1445 int virq, irq, evtchn;
1446
1447 for (virq = 0; virq < NR_VIRQS; virq++) {
1448 if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
1449 continue;
1450
ced40d0f 1451 BUG_ON(virq_from_irq(irq) != virq);
0e91398f
JF
1452
1453 /* Get a new binding from Xen. */
1454 bind_virq.virq = virq;
1455 bind_virq.vcpu = cpu;
1456 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
1457 &bind_virq) != 0)
1458 BUG();
1459 evtchn = bind_virq.port;
1460
1461 /* Record the new mapping. */
96d4c588 1462 (void)xen_irq_info_virq_setup(cpu, irq, evtchn, virq);
0e91398f 1463 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1464 }
1465}
1466
1467static void restore_cpu_ipis(unsigned int cpu)
1468{
1469 struct evtchn_bind_ipi bind_ipi;
1470 int ipi, irq, evtchn;
1471
1472 for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
1473 if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
1474 continue;
1475
ced40d0f 1476 BUG_ON(ipi_from_irq(irq) != ipi);
0e91398f
JF
1477
1478 /* Get a new binding from Xen. */
1479 bind_ipi.vcpu = cpu;
1480 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
1481 &bind_ipi) != 0)
1482 BUG();
1483 evtchn = bind_ipi.port;
1484
1485 /* Record the new mapping. */
96d4c588 1486 (void)xen_irq_info_ipi_setup(cpu, irq, evtchn, ipi);
0e91398f 1487 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1488 }
1489}
1490
2d9e1e2f
JF
1491/* Clear an irq's pending state, in preparation for polling on it */
1492void xen_clear_irq_pending(int irq)
1493{
1494 int evtchn = evtchn_from_irq(irq);
1495
1496 if (VALID_EVTCHN(evtchn))
1497 clear_evtchn(evtchn);
1498}
d9a8814f 1499EXPORT_SYMBOL(xen_clear_irq_pending);
168d2f46
JF
1500void xen_set_irq_pending(int irq)
1501{
1502 int evtchn = evtchn_from_irq(irq);
1503
1504 if (VALID_EVTCHN(evtchn))
1505 set_evtchn(evtchn);
1506}
1507
1508bool xen_test_irq_pending(int irq)
1509{
1510 int evtchn = evtchn_from_irq(irq);
1511 bool ret = false;
1512
1513 if (VALID_EVTCHN(evtchn))
1514 ret = test_evtchn(evtchn);
1515
1516 return ret;
1517}
1518
d9a8814f
KRW
1519/* Poll waiting for an irq to become pending with timeout. In the usual case,
1520 * the irq will be disabled so it won't deliver an interrupt. */
1521void xen_poll_irq_timeout(int irq, u64 timeout)
2d9e1e2f
JF
1522{
1523 evtchn_port_t evtchn = evtchn_from_irq(irq);
1524
1525 if (VALID_EVTCHN(evtchn)) {
1526 struct sched_poll poll;
1527
1528 poll.nr_ports = 1;
d9a8814f 1529 poll.timeout = timeout;
ff3c5362 1530 set_xen_guest_handle(poll.ports, &evtchn);
2d9e1e2f
JF
1531
1532 if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
1533 BUG();
1534 }
1535}
d9a8814f
KRW
1536EXPORT_SYMBOL(xen_poll_irq_timeout);
1537/* Poll waiting for an irq to become pending. In the usual case, the
1538 * irq will be disabled so it won't deliver an interrupt. */
1539void xen_poll_irq(int irq)
1540{
1541 xen_poll_irq_timeout(irq, 0 /* no timeout */);
1542}
2d9e1e2f 1543
c7c2c3a2
KRW
1544/* Check whether the IRQ line is shared with other guests. */
1545int xen_test_irq_shared(int irq)
1546{
1547 struct irq_info *info = info_for_irq(irq);
94032c50
KRW
1548 struct physdev_irq_status_query irq_status;
1549
1550 if (WARN_ON(!info))
1551 return -ENOENT;
1552
1553 irq_status.irq = info->u.pirq.pirq;
c7c2c3a2
KRW
1554
1555 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
1556 return 0;
1557 return !(irq_status.flags & XENIRQSTAT_shared);
1558}
1559EXPORT_SYMBOL_GPL(xen_test_irq_shared);
1560
0e91398f
JF
1561void xen_irq_resume(void)
1562{
fd21069d 1563 unsigned int cpu;
6cb6537d 1564 struct irq_info *info;
0e91398f 1565
0e91398f 1566 /* New event-channel space is not 'live' yet. */
fd21069d 1567 xen_evtchn_mask_all();
1fe56551 1568 xen_evtchn_resume();
0e91398f
JF
1569
1570 /* No IRQ <-> event-channel mappings. */
6cb6537d
IC
1571 list_for_each_entry(info, &xen_irq_list_head, list)
1572 info->evtchn = 0; /* zap event-channel binding */
0e91398f 1573
d0b075ff 1574 clear_evtchn_to_irq_all();
0e91398f
JF
1575
1576 for_each_possible_cpu(cpu) {
1577 restore_cpu_virqs(cpu);
1578 restore_cpu_ipis(cpu);
1579 }
6903591f 1580
0a85226f 1581 restore_pirqs();
0e91398f
JF
1582}
1583
e46cdb66 1584static struct irq_chip xen_dynamic_chip __read_mostly = {
c9e265e0 1585 .name = "xen-dyn",
54a353a0 1586
c9e265e0
TG
1587 .irq_disable = disable_dynirq,
1588 .irq_mask = disable_dynirq,
1589 .irq_unmask = enable_dynirq,
54a353a0 1590
7e186bdd
SS
1591 .irq_ack = ack_dynirq,
1592 .irq_mask_ack = mask_ack_dynirq,
1593
c9e265e0
TG
1594 .irq_set_affinity = set_affinity_irq,
1595 .irq_retrigger = retrigger_dynirq,
e46cdb66
JF
1596};
1597
d46a78b0 1598static struct irq_chip xen_pirq_chip __read_mostly = {
c9e265e0 1599 .name = "xen-pirq",
d46a78b0 1600
c9e265e0
TG
1601 .irq_startup = startup_pirq,
1602 .irq_shutdown = shutdown_pirq,
c9e265e0 1603 .irq_enable = enable_pirq,
c9e265e0 1604 .irq_disable = disable_pirq,
d46a78b0 1605
7e186bdd
SS
1606 .irq_mask = disable_dynirq,
1607 .irq_unmask = enable_dynirq,
1608
1609 .irq_ack = eoi_pirq,
1610 .irq_eoi = eoi_pirq,
1611 .irq_mask_ack = mask_ack_pirq,
d46a78b0 1612
c9e265e0 1613 .irq_set_affinity = set_affinity_irq,
d46a78b0 1614
c9e265e0 1615 .irq_retrigger = retrigger_dynirq,
d46a78b0
JF
1616};
1617
aaca4964 1618static struct irq_chip xen_percpu_chip __read_mostly = {
c9e265e0 1619 .name = "xen-percpu",
aaca4964 1620
c9e265e0
TG
1621 .irq_disable = disable_dynirq,
1622 .irq_mask = disable_dynirq,
1623 .irq_unmask = enable_dynirq,
aaca4964 1624
c9e265e0 1625 .irq_ack = ack_dynirq,
aaca4964
JF
1626};
1627
38e20b07
SY
1628int xen_set_callback_via(uint64_t via)
1629{
1630 struct xen_hvm_param a;
1631 a.domid = DOMID_SELF;
1632 a.index = HVM_PARAM_CALLBACK_IRQ;
1633 a.value = via;
1634 return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
1635}
1636EXPORT_SYMBOL_GPL(xen_set_callback_via);
1637
ca65f9fc 1638#ifdef CONFIG_XEN_PVHVM
38e20b07
SY
1639/* Vector callbacks are better than PCI interrupts to receive event
1640 * channel notifications because we can receive vector callbacks on any
1641 * vcpu and we don't need PCI support or APIC interactions. */
1642void xen_callback_vector(void)
1643{
1644 int rc;
1645 uint64_t callback_via;
1646 if (xen_have_vector_callback) {
bc2b0331 1647 callback_via = HVM_CALLBACK_VECTOR(HYPERVISOR_CALLBACK_VECTOR);
38e20b07
SY
1648 rc = xen_set_callback_via(callback_via);
1649 if (rc) {
283c0972 1650 pr_err("Request for Xen HVM callback vector failed\n");
38e20b07
SY
1651 xen_have_vector_callback = 0;
1652 return;
1653 }
283c0972 1654 pr_info("Xen HVM callback vector for event delivery is enabled\n");
38e20b07 1655 /* in the restore case the vector has already been allocated */
bc2b0331
S
1656 if (!test_bit(HYPERVISOR_CALLBACK_VECTOR, used_vectors))
1657 alloc_intr_gate(HYPERVISOR_CALLBACK_VECTOR,
1658 xen_hvm_callback_vector);
38e20b07
SY
1659 }
1660}
ca65f9fc
SS
1661#else
1662void xen_callback_vector(void) {}
1663#endif
38e20b07 1664
1fe56551
DV
1665#undef MODULE_PARAM_PREFIX
1666#define MODULE_PARAM_PREFIX "xen."
1667
1668static bool fifo_events = true;
1669module_param(fifo_events, bool, 0);
1670
2e3d8860 1671void __init xen_init_IRQ(void)
e46cdb66 1672{
1fe56551
DV
1673 int ret = -EINVAL;
1674
1675 if (fifo_events)
1676 ret = xen_evtchn_fifo_init();
1677 if (ret < 0)
1678 xen_evtchn_2l_init();
ab9a1cca 1679
d0b075ff
DV
1680 evtchn_to_irq = kcalloc(EVTCHN_ROW(xen_evtchn_max_channels()),
1681 sizeof(*evtchn_to_irq), GFP_KERNEL);
9d093e29 1682 BUG_ON(!evtchn_to_irq);
e46cdb66 1683
e46cdb66 1684 /* No event channels are 'live' right now. */
fd21069d 1685 xen_evtchn_mask_all();
e46cdb66 1686
9846ff10
SS
1687 pirq_needs_eoi = pirq_needs_eoi_flag;
1688
0ec53ecf 1689#ifdef CONFIG_X86
2771374d
MR
1690 if (xen_pv_domain()) {
1691 irq_ctx_init(smp_processor_id());
1692 if (xen_initial_domain())
1693 pci_xen_initial_domain();
1694 }
1695 if (xen_feature(XENFEAT_hvm_callback_vector))
38e20b07 1696 xen_callback_vector();
2771374d
MR
1697
1698 if (xen_hvm_domain()) {
38e20b07 1699 native_init_IRQ();
3942b740
SS
1700 /* pci_xen_hvm_init must be called after native_init_IRQ so that
1701 * __acpi_register_gsi can point at the right function */
1702 pci_xen_hvm_init();
38e20b07 1703 } else {
0ec53ecf 1704 int rc;
9846ff10
SS
1705 struct physdev_pirq_eoi_gmfn eoi_gmfn;
1706
9846ff10
SS
1707 pirq_eoi_map = (void *)__get_free_page(GFP_KERNEL|__GFP_ZERO);
1708 eoi_gmfn.gmfn = virt_to_mfn(pirq_eoi_map);
1709 rc = HYPERVISOR_physdev_op(PHYSDEVOP_pirq_eoi_gmfn_v2, &eoi_gmfn);
2771374d 1710 /* TODO: No PVH support for PIRQ EOI */
9846ff10
SS
1711 if (rc != 0) {
1712 free_page((unsigned long) pirq_eoi_map);
1713 pirq_eoi_map = NULL;
1714 } else
1715 pirq_needs_eoi = pirq_check_eoi_map;
38e20b07 1716 }
0ec53ecf 1717#endif
e46cdb66 1718}
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