Commit | Line | Data |
---|---|---|
e46cdb66 JF |
1 | /* |
2 | * Xen event channels | |
3 | * | |
4 | * Xen models interrupts with abstract event channels. Because each | |
5 | * domain gets 1024 event channels, but NR_IRQ is not that large, we | |
6 | * must dynamically map irqs<->event channels. The event channels | |
7 | * interface with the rest of the kernel by defining a xen interrupt | |
25985edc | 8 | * chip. When an event is received, it is mapped to an irq and sent |
e46cdb66 JF |
9 | * through the normal interrupt processing path. |
10 | * | |
11 | * There are four kinds of events which can be mapped to an event | |
12 | * channel: | |
13 | * | |
14 | * 1. Inter-domain notifications. This includes all the virtual | |
15 | * device events, since they're driven by front-ends in another domain | |
16 | * (typically dom0). | |
17 | * 2. VIRQs, typically used for timers. These are per-cpu events. | |
18 | * 3. IPIs. | |
d46a78b0 | 19 | * 4. PIRQs - Hardware interrupts. |
e46cdb66 JF |
20 | * |
21 | * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007 | |
22 | */ | |
23 | ||
283c0972 JP |
24 | #define pr_fmt(fmt) "xen:" KBUILD_MODNAME ": " fmt |
25 | ||
e46cdb66 JF |
26 | #include <linux/linkage.h> |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/irq.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/string.h> | |
28e08861 | 31 | #include <linux/bootmem.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
b21ddbf5 | 33 | #include <linux/irqnr.h> |
f731e3ef | 34 | #include <linux/pci.h> |
e46cdb66 | 35 | |
0ec53ecf | 36 | #ifdef CONFIG_X86 |
38e20b07 | 37 | #include <asm/desc.h> |
e46cdb66 JF |
38 | #include <asm/ptrace.h> |
39 | #include <asm/irq.h> | |
792dc4f6 | 40 | #include <asm/idle.h> |
0794bfc7 | 41 | #include <asm/io_apic.h> |
42a1de56 | 42 | #include <asm/xen/pci.h> |
a9fd60e2 | 43 | #include <xen/page.h> |
0ec53ecf SS |
44 | #endif |
45 | #include <asm/sync_bitops.h> | |
e46cdb66 | 46 | #include <asm/xen/hypercall.h> |
8d1b8753 | 47 | #include <asm/xen/hypervisor.h> |
e46cdb66 | 48 | |
38e20b07 SY |
49 | #include <xen/xen.h> |
50 | #include <xen/hvm.h> | |
e04d0d07 | 51 | #include <xen/xen-ops.h> |
e46cdb66 JF |
52 | #include <xen/events.h> |
53 | #include <xen/interface/xen.h> | |
54 | #include <xen/interface/event_channel.h> | |
38e20b07 SY |
55 | #include <xen/interface/hvm/hvm_op.h> |
56 | #include <xen/interface/hvm/params.h> | |
0ec53ecf SS |
57 | #include <xen/interface/physdev.h> |
58 | #include <xen/interface/sched.h> | |
6efa20e4 | 59 | #include <xen/interface/vcpu.h> |
0ec53ecf | 60 | #include <asm/hw_irq.h> |
e46cdb66 | 61 | |
9a489f45 DV |
62 | #include "events_internal.h" |
63 | ||
ab9a1cca DV |
64 | const struct evtchn_ops *evtchn_ops; |
65 | ||
e46cdb66 JF |
66 | /* |
67 | * This lock protects updates to the following mapping and reference-count | |
68 | * arrays. The lock does not need to be acquired to read the mapping tables. | |
69 | */ | |
77365948 | 70 | static DEFINE_MUTEX(irq_mapping_update_lock); |
e46cdb66 | 71 | |
6cb6537d IC |
72 | static LIST_HEAD(xen_irq_list_head); |
73 | ||
e46cdb66 | 74 | /* IRQ <-> VIRQ mapping. */ |
204fba4a | 75 | static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1}; |
e46cdb66 | 76 | |
f87e4cac | 77 | /* IRQ <-> IPI mapping */ |
204fba4a | 78 | static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1}; |
f87e4cac | 79 | |
d0b075ff | 80 | int **evtchn_to_irq; |
bf86ad80 | 81 | #ifdef CONFIG_X86 |
9846ff10 | 82 | static unsigned long *pirq_eoi_map; |
bf86ad80 | 83 | #endif |
9846ff10 | 84 | static bool (*pirq_needs_eoi)(unsigned irq); |
3b32f574 | 85 | |
d0b075ff DV |
86 | #define EVTCHN_ROW(e) (e / (PAGE_SIZE/sizeof(**evtchn_to_irq))) |
87 | #define EVTCHN_COL(e) (e % (PAGE_SIZE/sizeof(**evtchn_to_irq))) | |
88 | #define EVTCHN_PER_ROW (PAGE_SIZE / sizeof(**evtchn_to_irq)) | |
89 | ||
e46cdb66 JF |
90 | /* Xen will never allocate port zero for any purpose. */ |
91 | #define VALID_EVTCHN(chn) ((chn) != 0) | |
92 | ||
e46cdb66 | 93 | static struct irq_chip xen_dynamic_chip; |
aaca4964 | 94 | static struct irq_chip xen_percpu_chip; |
d46a78b0 | 95 | static struct irq_chip xen_pirq_chip; |
7e186bdd SS |
96 | static void enable_dynirq(struct irq_data *data); |
97 | static void disable_dynirq(struct irq_data *data); | |
e46cdb66 | 98 | |
d0b075ff DV |
99 | static void clear_evtchn_to_irq_row(unsigned row) |
100 | { | |
101 | unsigned col; | |
102 | ||
103 | for (col = 0; col < EVTCHN_PER_ROW; col++) | |
104 | evtchn_to_irq[row][col] = -1; | |
105 | } | |
106 | ||
107 | static void clear_evtchn_to_irq_all(void) | |
108 | { | |
109 | unsigned row; | |
110 | ||
111 | for (row = 0; row < EVTCHN_ROW(xen_evtchn_max_channels()); row++) { | |
112 | if (evtchn_to_irq[row] == NULL) | |
113 | continue; | |
114 | clear_evtchn_to_irq_row(row); | |
115 | } | |
116 | } | |
117 | ||
118 | static int set_evtchn_to_irq(unsigned evtchn, unsigned irq) | |
119 | { | |
120 | unsigned row; | |
121 | unsigned col; | |
122 | ||
123 | if (evtchn >= xen_evtchn_max_channels()) | |
124 | return -EINVAL; | |
125 | ||
126 | row = EVTCHN_ROW(evtchn); | |
127 | col = EVTCHN_COL(evtchn); | |
128 | ||
129 | if (evtchn_to_irq[row] == NULL) { | |
130 | /* Unallocated irq entries return -1 anyway */ | |
131 | if (irq == -1) | |
132 | return 0; | |
133 | ||
134 | evtchn_to_irq[row] = (int *)get_zeroed_page(GFP_KERNEL); | |
135 | if (evtchn_to_irq[row] == NULL) | |
136 | return -ENOMEM; | |
137 | ||
138 | clear_evtchn_to_irq_row(row); | |
139 | } | |
140 | ||
141 | evtchn_to_irq[EVTCHN_ROW(evtchn)][EVTCHN_COL(evtchn)] = irq; | |
142 | return 0; | |
143 | } | |
144 | ||
145 | int get_evtchn_to_irq(unsigned evtchn) | |
146 | { | |
147 | if (evtchn >= xen_evtchn_max_channels()) | |
148 | return -1; | |
149 | if (evtchn_to_irq[EVTCHN_ROW(evtchn)] == NULL) | |
150 | return -1; | |
151 | return evtchn_to_irq[EVTCHN_ROW(evtchn)][EVTCHN_COL(evtchn)]; | |
152 | } | |
153 | ||
9158c358 | 154 | /* Get info for IRQ */ |
9a489f45 | 155 | struct irq_info *info_for_irq(unsigned irq) |
ced40d0f | 156 | { |
c442b806 | 157 | return irq_get_handler_data(irq); |
ced40d0f JF |
158 | } |
159 | ||
9158c358 | 160 | /* Constructors for packed IRQ information. */ |
96d4c588 | 161 | static int xen_irq_info_common_setup(struct irq_info *info, |
3d4cfa37 | 162 | unsigned irq, |
9158c358 | 163 | enum xen_irq_type type, |
d0b075ff | 164 | unsigned evtchn, |
9158c358 | 165 | unsigned short cpu) |
ced40d0f | 166 | { |
d0b075ff | 167 | int ret; |
9158c358 IC |
168 | |
169 | BUG_ON(info->type != IRQT_UNBOUND && info->type != type); | |
170 | ||
171 | info->type = type; | |
6cb6537d | 172 | info->irq = irq; |
9158c358 IC |
173 | info->evtchn = evtchn; |
174 | info->cpu = cpu; | |
3d4cfa37 | 175 | |
d0b075ff DV |
176 | ret = set_evtchn_to_irq(evtchn, irq); |
177 | if (ret < 0) | |
178 | return ret; | |
934f585e JG |
179 | |
180 | irq_clear_status_flags(irq, IRQ_NOREQUEST|IRQ_NOAUTOEN); | |
96d4c588 | 181 | |
08385875 | 182 | return xen_evtchn_port_setup(info); |
ced40d0f JF |
183 | } |
184 | ||
96d4c588 | 185 | static int xen_irq_info_evtchn_setup(unsigned irq, |
d0b075ff | 186 | unsigned evtchn) |
ced40d0f | 187 | { |
9158c358 IC |
188 | struct irq_info *info = info_for_irq(irq); |
189 | ||
96d4c588 | 190 | return xen_irq_info_common_setup(info, irq, IRQT_EVTCHN, evtchn, 0); |
ced40d0f JF |
191 | } |
192 | ||
96d4c588 | 193 | static int xen_irq_info_ipi_setup(unsigned cpu, |
3d4cfa37 | 194 | unsigned irq, |
d0b075ff | 195 | unsigned evtchn, |
9158c358 | 196 | enum ipi_vector ipi) |
e46cdb66 | 197 | { |
9158c358 IC |
198 | struct irq_info *info = info_for_irq(irq); |
199 | ||
9158c358 | 200 | info->u.ipi = ipi; |
3d4cfa37 IC |
201 | |
202 | per_cpu(ipi_to_irq, cpu)[ipi] = irq; | |
96d4c588 DV |
203 | |
204 | return xen_irq_info_common_setup(info, irq, IRQT_IPI, evtchn, 0); | |
ced40d0f JF |
205 | } |
206 | ||
96d4c588 | 207 | static int xen_irq_info_virq_setup(unsigned cpu, |
3d4cfa37 | 208 | unsigned irq, |
d0b075ff DV |
209 | unsigned evtchn, |
210 | unsigned virq) | |
ced40d0f | 211 | { |
9158c358 IC |
212 | struct irq_info *info = info_for_irq(irq); |
213 | ||
9158c358 | 214 | info->u.virq = virq; |
3d4cfa37 IC |
215 | |
216 | per_cpu(virq_to_irq, cpu)[virq] = irq; | |
96d4c588 DV |
217 | |
218 | return xen_irq_info_common_setup(info, irq, IRQT_VIRQ, evtchn, 0); | |
ced40d0f JF |
219 | } |
220 | ||
96d4c588 | 221 | static int xen_irq_info_pirq_setup(unsigned irq, |
d0b075ff DV |
222 | unsigned evtchn, |
223 | unsigned pirq, | |
224 | unsigned gsi, | |
beafbdc1 | 225 | uint16_t domid, |
9158c358 | 226 | unsigned char flags) |
ced40d0f | 227 | { |
9158c358 IC |
228 | struct irq_info *info = info_for_irq(irq); |
229 | ||
9158c358 IC |
230 | info->u.pirq.pirq = pirq; |
231 | info->u.pirq.gsi = gsi; | |
beafbdc1 | 232 | info->u.pirq.domid = domid; |
9158c358 | 233 | info->u.pirq.flags = flags; |
96d4c588 DV |
234 | |
235 | return xen_irq_info_common_setup(info, irq, IRQT_PIRQ, evtchn, 0); | |
e46cdb66 JF |
236 | } |
237 | ||
d0b075ff DV |
238 | static void xen_irq_info_cleanup(struct irq_info *info) |
239 | { | |
240 | set_evtchn_to_irq(info->evtchn, -1); | |
241 | info->evtchn = 0; | |
242 | } | |
243 | ||
e46cdb66 JF |
244 | /* |
245 | * Accessors for packed IRQ information. | |
246 | */ | |
9a489f45 | 247 | unsigned int evtchn_from_irq(unsigned irq) |
e46cdb66 | 248 | { |
474b8fea | 249 | if (unlikely(WARN(irq >= nr_irqs, "Invalid irq %d!\n", irq))) |
110e7c7e JJ |
250 | return 0; |
251 | ||
ced40d0f | 252 | return info_for_irq(irq)->evtchn; |
e46cdb66 JF |
253 | } |
254 | ||
d4c04536 IC |
255 | unsigned irq_from_evtchn(unsigned int evtchn) |
256 | { | |
d0b075ff | 257 | return get_evtchn_to_irq(evtchn); |
d4c04536 IC |
258 | } |
259 | EXPORT_SYMBOL_GPL(irq_from_evtchn); | |
260 | ||
9a489f45 DV |
261 | int irq_from_virq(unsigned int cpu, unsigned int virq) |
262 | { | |
263 | return per_cpu(virq_to_irq, cpu)[virq]; | |
264 | } | |
265 | ||
ced40d0f | 266 | static enum ipi_vector ipi_from_irq(unsigned irq) |
e46cdb66 | 267 | { |
ced40d0f JF |
268 | struct irq_info *info = info_for_irq(irq); |
269 | ||
270 | BUG_ON(info == NULL); | |
271 | BUG_ON(info->type != IRQT_IPI); | |
272 | ||
273 | return info->u.ipi; | |
274 | } | |
275 | ||
276 | static unsigned virq_from_irq(unsigned irq) | |
277 | { | |
278 | struct irq_info *info = info_for_irq(irq); | |
279 | ||
280 | BUG_ON(info == NULL); | |
281 | BUG_ON(info->type != IRQT_VIRQ); | |
282 | ||
283 | return info->u.virq; | |
284 | } | |
285 | ||
7a043f11 SS |
286 | static unsigned pirq_from_irq(unsigned irq) |
287 | { | |
288 | struct irq_info *info = info_for_irq(irq); | |
289 | ||
290 | BUG_ON(info == NULL); | |
291 | BUG_ON(info->type != IRQT_PIRQ); | |
292 | ||
293 | return info->u.pirq.pirq; | |
294 | } | |
295 | ||
ced40d0f JF |
296 | static enum xen_irq_type type_from_irq(unsigned irq) |
297 | { | |
298 | return info_for_irq(irq)->type; | |
299 | } | |
300 | ||
9a489f45 | 301 | unsigned cpu_from_irq(unsigned irq) |
ced40d0f JF |
302 | { |
303 | return info_for_irq(irq)->cpu; | |
304 | } | |
305 | ||
9a489f45 | 306 | unsigned int cpu_from_evtchn(unsigned int evtchn) |
ced40d0f | 307 | { |
d0b075ff | 308 | int irq = get_evtchn_to_irq(evtchn); |
ced40d0f JF |
309 | unsigned ret = 0; |
310 | ||
311 | if (irq != -1) | |
312 | ret = cpu_from_irq(irq); | |
313 | ||
314 | return ret; | |
e46cdb66 JF |
315 | } |
316 | ||
bf86ad80 | 317 | #ifdef CONFIG_X86 |
9846ff10 | 318 | static bool pirq_check_eoi_map(unsigned irq) |
d46a78b0 | 319 | { |
521394e4 | 320 | return test_bit(pirq_from_irq(irq), pirq_eoi_map); |
9846ff10 | 321 | } |
bf86ad80 | 322 | #endif |
d46a78b0 | 323 | |
9846ff10 SS |
324 | static bool pirq_needs_eoi_flag(unsigned irq) |
325 | { | |
326 | struct irq_info *info = info_for_irq(irq); | |
d46a78b0 JF |
327 | BUG_ON(info->type != IRQT_PIRQ); |
328 | ||
329 | return info->u.pirq.flags & PIRQ_NEEDS_EOI; | |
330 | } | |
331 | ||
e46cdb66 JF |
332 | static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu) |
333 | { | |
d0b075ff | 334 | int irq = get_evtchn_to_irq(chn); |
9a489f45 | 335 | struct irq_info *info = info_for_irq(irq); |
e46cdb66 JF |
336 | |
337 | BUG_ON(irq == -1); | |
338 | #ifdef CONFIG_SMP | |
589d03e9 | 339 | cpumask_copy(irq_get_irq_data(irq)->affinity, cpumask_of(cpu)); |
e46cdb66 | 340 | #endif |
9a489f45 | 341 | xen_evtchn_port_bind_to_cpu(info, cpu); |
168d2f46 | 342 | |
9a489f45 | 343 | info->cpu = cpu; |
3f70fa82 WL |
344 | } |
345 | ||
fd21069d DV |
346 | static void xen_evtchn_mask_all(void) |
347 | { | |
348 | unsigned int evtchn; | |
349 | ||
350 | for (evtchn = 0; evtchn < xen_evtchn_nr_channels(); evtchn++) | |
351 | mask_evtchn(evtchn); | |
352 | } | |
353 | ||
e46cdb66 JF |
354 | /** |
355 | * notify_remote_via_irq - send event to remote end of event channel via irq | |
356 | * @irq: irq of event channel to send event to | |
357 | * | |
358 | * Unlike notify_remote_via_evtchn(), this is safe to use across | |
359 | * save/restore. Notifications on a broken connection are silently | |
360 | * dropped. | |
361 | */ | |
362 | void notify_remote_via_irq(int irq) | |
363 | { | |
364 | int evtchn = evtchn_from_irq(irq); | |
365 | ||
366 | if (VALID_EVTCHN(evtchn)) | |
367 | notify_remote_via_evtchn(evtchn); | |
368 | } | |
369 | EXPORT_SYMBOL_GPL(notify_remote_via_irq); | |
370 | ||
6cb6537d IC |
371 | static void xen_irq_init(unsigned irq) |
372 | { | |
373 | struct irq_info *info; | |
b5328cd1 | 374 | #ifdef CONFIG_SMP |
6cb6537d | 375 | /* By default all event channels notify CPU#0. */ |
589d03e9 | 376 | cpumask_copy(irq_get_irq_data(irq)->affinity, cpumask_of(0)); |
44626e4a | 377 | #endif |
6cb6537d | 378 | |
ca62ce8c IC |
379 | info = kzalloc(sizeof(*info), GFP_KERNEL); |
380 | if (info == NULL) | |
381 | panic("Unable to allocate metadata for IRQ%d\n", irq); | |
6cb6537d IC |
382 | |
383 | info->type = IRQT_UNBOUND; | |
420eb554 | 384 | info->refcnt = -1; |
6cb6537d | 385 | |
c442b806 | 386 | irq_set_handler_data(irq, info); |
ca62ce8c | 387 | |
6cb6537d IC |
388 | list_add_tail(&info->list, &xen_irq_list_head); |
389 | } | |
390 | ||
4892c9b4 | 391 | static int __must_check xen_allocate_irqs_dynamic(int nvec) |
0794bfc7 | 392 | { |
d07c9f18 | 393 | int i, irq = irq_alloc_descs(-1, 0, nvec, -1); |
3a69e916 | 394 | |
4892c9b4 RPM |
395 | if (irq >= 0) { |
396 | for (i = 0; i < nvec; i++) | |
397 | xen_irq_init(irq + i); | |
398 | } | |
ced40d0f | 399 | |
e46cdb66 | 400 | return irq; |
d46a78b0 JF |
401 | } |
402 | ||
4892c9b4 RPM |
403 | static inline int __must_check xen_allocate_irq_dynamic(void) |
404 | { | |
405 | ||
406 | return xen_allocate_irqs_dynamic(1); | |
407 | } | |
408 | ||
7bee9768 | 409 | static int __must_check xen_allocate_irq_gsi(unsigned gsi) |
c9df1ce5 IC |
410 | { |
411 | int irq; | |
412 | ||
89911501 IC |
413 | /* |
414 | * A PV guest has no concept of a GSI (since it has no ACPI | |
415 | * nor access to/knowledge of the physical APICs). Therefore | |
416 | * all IRQs are dynamically allocated from the entire IRQ | |
417 | * space. | |
418 | */ | |
419 | if (xen_pv_domain() && !xen_initial_domain()) | |
c9df1ce5 IC |
420 | return xen_allocate_irq_dynamic(); |
421 | ||
422 | /* Legacy IRQ descriptors are already allocated by the arch. */ | |
423 | if (gsi < NR_IRQS_LEGACY) | |
6cb6537d IC |
424 | irq = gsi; |
425 | else | |
426 | irq = irq_alloc_desc_at(gsi, -1); | |
c9df1ce5 | 427 | |
6cb6537d | 428 | xen_irq_init(irq); |
c9df1ce5 IC |
429 | |
430 | return irq; | |
431 | } | |
432 | ||
433 | static void xen_free_irq(unsigned irq) | |
434 | { | |
c442b806 | 435 | struct irq_info *info = irq_get_handler_data(irq); |
6cb6537d | 436 | |
94032c50 KRW |
437 | if (WARN_ON(!info)) |
438 | return; | |
439 | ||
6cb6537d | 440 | list_del(&info->list); |
9158c358 | 441 | |
c442b806 | 442 | irq_set_handler_data(irq, NULL); |
ca62ce8c | 443 | |
420eb554 DDG |
444 | WARN_ON(info->refcnt > 0); |
445 | ||
ca62ce8c IC |
446 | kfree(info); |
447 | ||
72146104 IC |
448 | /* Legacy IRQ descriptors are managed by the arch. */ |
449 | if (irq < NR_IRQS_LEGACY) | |
450 | return; | |
451 | ||
c9df1ce5 IC |
452 | irq_free_desc(irq); |
453 | } | |
454 | ||
fcdf31a7 | 455 | static void xen_evtchn_close(unsigned int port, unsigned int cpu) |
d0b075ff DV |
456 | { |
457 | struct evtchn_close close; | |
458 | ||
fcdf31a7 RL |
459 | xen_evtchn_op_close(port, cpu); |
460 | ||
d0b075ff DV |
461 | close.port = port; |
462 | if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0) | |
463 | BUG(); | |
d0b075ff DV |
464 | } |
465 | ||
d46a78b0 JF |
466 | static void pirq_query_unmask(int irq) |
467 | { | |
468 | struct physdev_irq_status_query irq_status; | |
469 | struct irq_info *info = info_for_irq(irq); | |
470 | ||
471 | BUG_ON(info->type != IRQT_PIRQ); | |
472 | ||
7a043f11 | 473 | irq_status.irq = pirq_from_irq(irq); |
d46a78b0 JF |
474 | if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status)) |
475 | irq_status.flags = 0; | |
476 | ||
477 | info->u.pirq.flags &= ~PIRQ_NEEDS_EOI; | |
478 | if (irq_status.flags & XENIRQSTAT_needs_eoi) | |
479 | info->u.pirq.flags |= PIRQ_NEEDS_EOI; | |
480 | } | |
481 | ||
7e186bdd SS |
482 | static void eoi_pirq(struct irq_data *data) |
483 | { | |
484 | int evtchn = evtchn_from_irq(data->irq); | |
485 | struct physdev_eoi eoi = { .irq = pirq_from_irq(data->irq) }; | |
486 | int rc = 0; | |
487 | ||
488 | irq_move_irq(data); | |
489 | ||
490 | if (VALID_EVTCHN(evtchn)) | |
491 | clear_evtchn(evtchn); | |
492 | ||
493 | if (pirq_needs_eoi(data->irq)) { | |
494 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi); | |
495 | WARN_ON(rc); | |
496 | } | |
497 | } | |
498 | ||
499 | static void mask_ack_pirq(struct irq_data *data) | |
500 | { | |
501 | disable_dynirq(data); | |
502 | eoi_pirq(data); | |
503 | } | |
504 | ||
c9e265e0 | 505 | static unsigned int __startup_pirq(unsigned int irq) |
d46a78b0 JF |
506 | { |
507 | struct evtchn_bind_pirq bind_pirq; | |
508 | struct irq_info *info = info_for_irq(irq); | |
509 | int evtchn = evtchn_from_irq(irq); | |
15ebbb82 | 510 | int rc; |
d46a78b0 JF |
511 | |
512 | BUG_ON(info->type != IRQT_PIRQ); | |
513 | ||
514 | if (VALID_EVTCHN(evtchn)) | |
515 | goto out; | |
516 | ||
7a043f11 | 517 | bind_pirq.pirq = pirq_from_irq(irq); |
d46a78b0 | 518 | /* NB. We are happy to share unless we are probing. */ |
15ebbb82 KRW |
519 | bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ? |
520 | BIND_PIRQ__WILL_SHARE : 0; | |
521 | rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq); | |
522 | if (rc != 0) { | |
02893afd | 523 | pr_warn("Failed to obtain physical IRQ %d\n", irq); |
d46a78b0 JF |
524 | return 0; |
525 | } | |
526 | evtchn = bind_pirq.port; | |
527 | ||
528 | pirq_query_unmask(irq); | |
529 | ||
d0b075ff | 530 | rc = set_evtchn_to_irq(evtchn, irq); |
85e40b05 JG |
531 | if (rc) |
532 | goto err; | |
533 | ||
d46a78b0 | 534 | info->evtchn = evtchn; |
16e6bd59 | 535 | bind_evtchn_to_cpu(evtchn, 0); |
d46a78b0 | 536 | |
85e40b05 JG |
537 | rc = xen_evtchn_port_setup(info); |
538 | if (rc) | |
539 | goto err; | |
540 | ||
d46a78b0 JF |
541 | out: |
542 | unmask_evtchn(evtchn); | |
7e186bdd | 543 | eoi_pirq(irq_get_irq_data(irq)); |
d46a78b0 JF |
544 | |
545 | return 0; | |
85e40b05 JG |
546 | |
547 | err: | |
548 | pr_err("irq%d: Failed to set port to irq mapping (%d)\n", irq, rc); | |
fcdf31a7 | 549 | xen_evtchn_close(evtchn, NR_CPUS); |
85e40b05 | 550 | return 0; |
d46a78b0 JF |
551 | } |
552 | ||
c9e265e0 TG |
553 | static unsigned int startup_pirq(struct irq_data *data) |
554 | { | |
555 | return __startup_pirq(data->irq); | |
556 | } | |
557 | ||
558 | static void shutdown_pirq(struct irq_data *data) | |
d46a78b0 | 559 | { |
c9e265e0 | 560 | unsigned int irq = data->irq; |
d46a78b0 | 561 | struct irq_info *info = info_for_irq(irq); |
d0b075ff | 562 | unsigned evtchn = evtchn_from_irq(irq); |
d46a78b0 JF |
563 | |
564 | BUG_ON(info->type != IRQT_PIRQ); | |
565 | ||
566 | if (!VALID_EVTCHN(evtchn)) | |
567 | return; | |
568 | ||
569 | mask_evtchn(evtchn); | |
fcdf31a7 | 570 | xen_evtchn_close(evtchn, cpu_from_evtchn(evtchn)); |
d0b075ff | 571 | xen_irq_info_cleanup(info); |
d46a78b0 JF |
572 | } |
573 | ||
c9e265e0 | 574 | static void enable_pirq(struct irq_data *data) |
d46a78b0 | 575 | { |
c9e265e0 | 576 | startup_pirq(data); |
d46a78b0 JF |
577 | } |
578 | ||
c9e265e0 | 579 | static void disable_pirq(struct irq_data *data) |
d46a78b0 | 580 | { |
7e186bdd | 581 | disable_dynirq(data); |
d46a78b0 JF |
582 | } |
583 | ||
68c2c39a | 584 | int xen_irq_from_gsi(unsigned gsi) |
d46a78b0 | 585 | { |
6cb6537d | 586 | struct irq_info *info; |
d46a78b0 | 587 | |
6cb6537d IC |
588 | list_for_each_entry(info, &xen_irq_list_head, list) { |
589 | if (info->type != IRQT_PIRQ) | |
d46a78b0 JF |
590 | continue; |
591 | ||
6cb6537d IC |
592 | if (info->u.pirq.gsi == gsi) |
593 | return info->irq; | |
d46a78b0 JF |
594 | } |
595 | ||
596 | return -1; | |
597 | } | |
68c2c39a | 598 | EXPORT_SYMBOL_GPL(xen_irq_from_gsi); |
d46a78b0 | 599 | |
96d4c588 DV |
600 | static void __unbind_from_irq(unsigned int irq) |
601 | { | |
96d4c588 DV |
602 | int evtchn = evtchn_from_irq(irq); |
603 | struct irq_info *info = irq_get_handler_data(irq); | |
604 | ||
605 | if (info->refcnt > 0) { | |
606 | info->refcnt--; | |
607 | if (info->refcnt != 0) | |
608 | return; | |
609 | } | |
610 | ||
611 | if (VALID_EVTCHN(evtchn)) { | |
d0b075ff DV |
612 | unsigned int cpu = cpu_from_irq(irq); |
613 | ||
fcdf31a7 | 614 | xen_evtchn_close(evtchn, cpu); |
96d4c588 DV |
615 | |
616 | switch (type_from_irq(irq)) { | |
617 | case IRQT_VIRQ: | |
d0b075ff | 618 | per_cpu(virq_to_irq, cpu)[virq_from_irq(irq)] = -1; |
96d4c588 DV |
619 | break; |
620 | case IRQT_IPI: | |
d0b075ff | 621 | per_cpu(ipi_to_irq, cpu)[ipi_from_irq(irq)] = -1; |
96d4c588 DV |
622 | break; |
623 | default: | |
624 | break; | |
625 | } | |
626 | ||
d0b075ff | 627 | xen_irq_info_cleanup(info); |
96d4c588 DV |
628 | } |
629 | ||
630 | BUG_ON(info_for_irq(irq)->type == IRQT_UNBOUND); | |
631 | ||
632 | xen_free_irq(irq); | |
633 | } | |
634 | ||
653378ac IC |
635 | /* |
636 | * Do not make any assumptions regarding the relationship between the | |
637 | * IRQ number returned here and the Xen pirq argument. | |
7a043f11 SS |
638 | * |
639 | * Note: We don't assign an event channel until the irq actually started | |
640 | * up. Return an existing irq if we've already got one for the gsi. | |
e5ac0bda SS |
641 | * |
642 | * Shareable implies level triggered, not shareable implies edge | |
643 | * triggered here. | |
d46a78b0 | 644 | */ |
f4d0635b IC |
645 | int xen_bind_pirq_gsi_to_irq(unsigned gsi, |
646 | unsigned pirq, int shareable, char *name) | |
d46a78b0 | 647 | { |
a0e18116 | 648 | int irq = -1; |
d46a78b0 | 649 | struct physdev_irq irq_op; |
96d4c588 | 650 | int ret; |
d46a78b0 | 651 | |
77365948 | 652 | mutex_lock(&irq_mapping_update_lock); |
d46a78b0 | 653 | |
68c2c39a | 654 | irq = xen_irq_from_gsi(gsi); |
d46a78b0 | 655 | if (irq != -1) { |
283c0972 JP |
656 | pr_info("%s: returning irq %d for gsi %u\n", |
657 | __func__, irq, gsi); | |
420eb554 | 658 | goto out; |
d46a78b0 JF |
659 | } |
660 | ||
c9df1ce5 | 661 | irq = xen_allocate_irq_gsi(gsi); |
7bee9768 IC |
662 | if (irq < 0) |
663 | goto out; | |
d46a78b0 | 664 | |
d46a78b0 | 665 | irq_op.irq = irq; |
b5401a96 AN |
666 | irq_op.vector = 0; |
667 | ||
668 | /* Only the privileged domain can do this. For non-priv, the pcifront | |
669 | * driver provides a PCI bus that does the call to do exactly | |
670 | * this in the priv domain. */ | |
671 | if (xen_initial_domain() && | |
672 | HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) { | |
c9df1ce5 | 673 | xen_free_irq(irq); |
d46a78b0 JF |
674 | irq = -ENOSPC; |
675 | goto out; | |
676 | } | |
677 | ||
96d4c588 | 678 | ret = xen_irq_info_pirq_setup(irq, 0, pirq, gsi, DOMID_SELF, |
9158c358 | 679 | shareable ? PIRQ_SHAREABLE : 0); |
96d4c588 DV |
680 | if (ret < 0) { |
681 | __unbind_from_irq(irq); | |
682 | irq = ret; | |
683 | goto out; | |
684 | } | |
d46a78b0 | 685 | |
7e186bdd SS |
686 | pirq_query_unmask(irq); |
687 | /* We try to use the handler with the appropriate semantic for the | |
e5ac0bda SS |
688 | * type of interrupt: if the interrupt is an edge triggered |
689 | * interrupt we use handle_edge_irq. | |
7e186bdd | 690 | * |
e5ac0bda SS |
691 | * On the other hand if the interrupt is level triggered we use |
692 | * handle_fasteoi_irq like the native code does for this kind of | |
7e186bdd | 693 | * interrupts. |
e5ac0bda | 694 | * |
7e186bdd SS |
695 | * Depending on the Xen version, pirq_needs_eoi might return true |
696 | * not only for level triggered interrupts but for edge triggered | |
697 | * interrupts too. In any case Xen always honors the eoi mechanism, | |
698 | * not injecting any more pirqs of the same kind if the first one | |
699 | * hasn't received an eoi yet. Therefore using the fasteoi handler | |
700 | * is the right choice either way. | |
701 | */ | |
e5ac0bda | 702 | if (shareable) |
7e186bdd SS |
703 | irq_set_chip_and_handler_name(irq, &xen_pirq_chip, |
704 | handle_fasteoi_irq, name); | |
705 | else | |
706 | irq_set_chip_and_handler_name(irq, &xen_pirq_chip, | |
707 | handle_edge_irq, name); | |
708 | ||
d46a78b0 | 709 | out: |
77365948 | 710 | mutex_unlock(&irq_mapping_update_lock); |
d46a78b0 JF |
711 | |
712 | return irq; | |
713 | } | |
714 | ||
f731e3ef | 715 | #ifdef CONFIG_PCI_MSI |
bf480d95 | 716 | int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc) |
cbf6aa89 | 717 | { |
5cad61a6 | 718 | int rc; |
cbf6aa89 | 719 | struct physdev_get_free_pirq op_get_free_pirq; |
cbf6aa89 | 720 | |
bf480d95 | 721 | op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI; |
cbf6aa89 | 722 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq); |
cbf6aa89 | 723 | |
5cad61a6 IC |
724 | WARN_ONCE(rc == -ENOSYS, |
725 | "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n"); | |
726 | ||
727 | return rc ? -1 : op_get_free_pirq.pirq; | |
cbf6aa89 IC |
728 | } |
729 | ||
bf480d95 | 730 | int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc, |
4892c9b4 | 731 | int pirq, int nvec, const char *name, domid_t domid) |
809f9267 | 732 | { |
4892c9b4 | 733 | int i, irq, ret; |
4b41df7f | 734 | |
77365948 | 735 | mutex_lock(&irq_mapping_update_lock); |
809f9267 | 736 | |
4892c9b4 | 737 | irq = xen_allocate_irqs_dynamic(nvec); |
e6599225 | 738 | if (irq < 0) |
bb5d079a | 739 | goto out; |
809f9267 | 740 | |
4892c9b4 RPM |
741 | for (i = 0; i < nvec; i++) { |
742 | irq_set_chip_and_handler_name(irq + i, &xen_pirq_chip, handle_edge_irq, name); | |
743 | ||
744 | ret = xen_irq_info_pirq_setup(irq + i, 0, pirq + i, 0, domid, | |
745 | i == 0 ? 0 : PIRQ_MSI_GROUP); | |
746 | if (ret < 0) | |
747 | goto error_irq; | |
748 | } | |
809f9267 | 749 | |
5f6fb454 | 750 | ret = irq_set_msi_desc(irq, msidesc); |
bf480d95 IC |
751 | if (ret < 0) |
752 | goto error_irq; | |
809f9267 | 753 | out: |
77365948 | 754 | mutex_unlock(&irq_mapping_update_lock); |
4b41df7f | 755 | return irq; |
bf480d95 | 756 | error_irq: |
4892c9b4 RPM |
757 | for (; i >= 0; i--) |
758 | __unbind_from_irq(irq + i); | |
77365948 | 759 | mutex_unlock(&irq_mapping_update_lock); |
e6599225 | 760 | return ret; |
809f9267 | 761 | } |
f731e3ef QH |
762 | #endif |
763 | ||
b5401a96 AN |
764 | int xen_destroy_irq(int irq) |
765 | { | |
38aa66fc JF |
766 | struct physdev_unmap_pirq unmap_irq; |
767 | struct irq_info *info = info_for_irq(irq); | |
b5401a96 AN |
768 | int rc = -ENOENT; |
769 | ||
77365948 | 770 | mutex_lock(&irq_mapping_update_lock); |
b5401a96 | 771 | |
4892c9b4 RPM |
772 | /* |
773 | * If trying to remove a vector in a MSI group different | |
774 | * than the first one skip the PIRQ unmap unless this vector | |
775 | * is the first one in the group. | |
776 | */ | |
777 | if (xen_initial_domain() && !(info->u.pirq.flags & PIRQ_MSI_GROUP)) { | |
12334715 | 778 | unmap_irq.pirq = info->u.pirq.pirq; |
beafbdc1 | 779 | unmap_irq.domid = info->u.pirq.domid; |
38aa66fc | 780 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq); |
1eff1ad0 KRW |
781 | /* If another domain quits without making the pci_disable_msix |
782 | * call, the Xen hypervisor takes care of freeing the PIRQs | |
783 | * (free_domain_pirqs). | |
784 | */ | |
785 | if ((rc == -ESRCH && info->u.pirq.domid != DOMID_SELF)) | |
283c0972 | 786 | pr_info("domain %d does not have %d anymore\n", |
1eff1ad0 KRW |
787 | info->u.pirq.domid, info->u.pirq.pirq); |
788 | else if (rc) { | |
283c0972 | 789 | pr_warn("unmap irq failed %d\n", rc); |
38aa66fc JF |
790 | goto out; |
791 | } | |
792 | } | |
b5401a96 | 793 | |
c9df1ce5 | 794 | xen_free_irq(irq); |
b5401a96 AN |
795 | |
796 | out: | |
77365948 | 797 | mutex_unlock(&irq_mapping_update_lock); |
b5401a96 AN |
798 | return rc; |
799 | } | |
800 | ||
af42b8d1 | 801 | int xen_irq_from_pirq(unsigned pirq) |
d46a78b0 | 802 | { |
69c358ce | 803 | int irq; |
d46a78b0 | 804 | |
69c358ce | 805 | struct irq_info *info; |
e46cdb66 | 806 | |
77365948 | 807 | mutex_lock(&irq_mapping_update_lock); |
69c358ce IC |
808 | |
809 | list_for_each_entry(info, &xen_irq_list_head, list) { | |
9bb9efe4 | 810 | if (info->type != IRQT_PIRQ) |
69c358ce IC |
811 | continue; |
812 | irq = info->irq; | |
813 | if (info->u.pirq.pirq == pirq) | |
814 | goto out; | |
815 | } | |
816 | irq = -1; | |
817 | out: | |
77365948 | 818 | mutex_unlock(&irq_mapping_update_lock); |
69c358ce IC |
819 | |
820 | return irq; | |
af42b8d1 SS |
821 | } |
822 | ||
e6197acc KRW |
823 | |
824 | int xen_pirq_from_irq(unsigned irq) | |
825 | { | |
826 | return pirq_from_irq(irq); | |
827 | } | |
828 | EXPORT_SYMBOL_GPL(xen_pirq_from_irq); | |
96d4c588 | 829 | |
b536b4b9 | 830 | int bind_evtchn_to_irq(unsigned int evtchn) |
e46cdb66 JF |
831 | { |
832 | int irq; | |
96d4c588 | 833 | int ret; |
e46cdb66 | 834 | |
d0b075ff DV |
835 | if (evtchn >= xen_evtchn_max_channels()) |
836 | return -ENOMEM; | |
837 | ||
77365948 | 838 | mutex_lock(&irq_mapping_update_lock); |
e46cdb66 | 839 | |
d0b075ff | 840 | irq = get_evtchn_to_irq(evtchn); |
e46cdb66 JF |
841 | |
842 | if (irq == -1) { | |
c9df1ce5 | 843 | irq = xen_allocate_irq_dynamic(); |
68ba45ff | 844 | if (irq < 0) |
7bee9768 | 845 | goto out; |
e46cdb66 | 846 | |
c442b806 | 847 | irq_set_chip_and_handler_name(irq, &xen_dynamic_chip, |
7e186bdd | 848 | handle_edge_irq, "event"); |
e46cdb66 | 849 | |
96d4c588 DV |
850 | ret = xen_irq_info_evtchn_setup(irq, evtchn); |
851 | if (ret < 0) { | |
852 | __unbind_from_irq(irq); | |
853 | irq = ret; | |
854 | goto out; | |
855 | } | |
97253eee DV |
856 | /* New interdomain events are bound to VCPU 0. */ |
857 | bind_evtchn_to_cpu(evtchn, 0); | |
5e152e6c KRW |
858 | } else { |
859 | struct irq_info *info = info_for_irq(irq); | |
860 | WARN_ON(info == NULL || info->type != IRQT_EVTCHN); | |
e46cdb66 JF |
861 | } |
862 | ||
7bee9768 | 863 | out: |
77365948 | 864 | mutex_unlock(&irq_mapping_update_lock); |
e46cdb66 JF |
865 | |
866 | return irq; | |
867 | } | |
b536b4b9 | 868 | EXPORT_SYMBOL_GPL(bind_evtchn_to_irq); |
e46cdb66 | 869 | |
f87e4cac JF |
870 | static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu) |
871 | { | |
872 | struct evtchn_bind_ipi bind_ipi; | |
873 | int evtchn, irq; | |
96d4c588 | 874 | int ret; |
f87e4cac | 875 | |
77365948 | 876 | mutex_lock(&irq_mapping_update_lock); |
f87e4cac JF |
877 | |
878 | irq = per_cpu(ipi_to_irq, cpu)[ipi]; | |
90af9514 | 879 | |
f87e4cac | 880 | if (irq == -1) { |
c9df1ce5 | 881 | irq = xen_allocate_irq_dynamic(); |
f87e4cac JF |
882 | if (irq < 0) |
883 | goto out; | |
884 | ||
c442b806 | 885 | irq_set_chip_and_handler_name(irq, &xen_percpu_chip, |
aaca4964 | 886 | handle_percpu_irq, "ipi"); |
f87e4cac JF |
887 | |
888 | bind_ipi.vcpu = cpu; | |
889 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi, | |
890 | &bind_ipi) != 0) | |
891 | BUG(); | |
892 | evtchn = bind_ipi.port; | |
893 | ||
96d4c588 DV |
894 | ret = xen_irq_info_ipi_setup(cpu, irq, evtchn, ipi); |
895 | if (ret < 0) { | |
896 | __unbind_from_irq(irq); | |
897 | irq = ret; | |
898 | goto out; | |
899 | } | |
f87e4cac | 900 | bind_evtchn_to_cpu(evtchn, cpu); |
5e152e6c KRW |
901 | } else { |
902 | struct irq_info *info = info_for_irq(irq); | |
903 | WARN_ON(info == NULL || info->type != IRQT_IPI); | |
f87e4cac JF |
904 | } |
905 | ||
f87e4cac | 906 | out: |
77365948 | 907 | mutex_unlock(&irq_mapping_update_lock); |
f87e4cac JF |
908 | return irq; |
909 | } | |
910 | ||
854072dd JG |
911 | int bind_interdomain_evtchn_to_irq(unsigned int remote_domain, |
912 | unsigned int remote_port) | |
2e820f58 IC |
913 | { |
914 | struct evtchn_bind_interdomain bind_interdomain; | |
915 | int err; | |
916 | ||
917 | bind_interdomain.remote_dom = remote_domain; | |
918 | bind_interdomain.remote_port = remote_port; | |
919 | ||
920 | err = HYPERVISOR_event_channel_op(EVTCHNOP_bind_interdomain, | |
921 | &bind_interdomain); | |
922 | ||
923 | return err ? : bind_evtchn_to_irq(bind_interdomain.local_port); | |
924 | } | |
854072dd | 925 | EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irq); |
2e820f58 | 926 | |
62cc5fc7 OH |
927 | static int find_virq(unsigned int virq, unsigned int cpu) |
928 | { | |
929 | struct evtchn_status status; | |
930 | int port, rc = -ENOENT; | |
931 | ||
932 | memset(&status, 0, sizeof(status)); | |
d0b075ff | 933 | for (port = 0; port < xen_evtchn_max_channels(); port++) { |
62cc5fc7 OH |
934 | status.dom = DOMID_SELF; |
935 | status.port = port; | |
936 | rc = HYPERVISOR_event_channel_op(EVTCHNOP_status, &status); | |
937 | if (rc < 0) | |
938 | continue; | |
939 | if (status.status != EVTCHNSTAT_virq) | |
940 | continue; | |
941 | if (status.u.virq == virq && status.vcpu == cpu) { | |
942 | rc = port; | |
943 | break; | |
944 | } | |
945 | } | |
946 | return rc; | |
947 | } | |
f87e4cac | 948 | |
0dc0064a DV |
949 | /** |
950 | * xen_evtchn_nr_channels - number of usable event channel ports | |
951 | * | |
952 | * This may be less than the maximum supported by the current | |
953 | * hypervisor ABI. Use xen_evtchn_max_channels() for the maximum | |
954 | * supported. | |
955 | */ | |
956 | unsigned xen_evtchn_nr_channels(void) | |
957 | { | |
958 | return evtchn_ops->nr_channels(); | |
959 | } | |
960 | EXPORT_SYMBOL_GPL(xen_evtchn_nr_channels); | |
961 | ||
77bb3dfd | 962 | int bind_virq_to_irq(unsigned int virq, unsigned int cpu, bool percpu) |
e46cdb66 JF |
963 | { |
964 | struct evtchn_bind_virq bind_virq; | |
62cc5fc7 | 965 | int evtchn, irq, ret; |
e46cdb66 | 966 | |
77365948 | 967 | mutex_lock(&irq_mapping_update_lock); |
e46cdb66 JF |
968 | |
969 | irq = per_cpu(virq_to_irq, cpu)[virq]; | |
970 | ||
971 | if (irq == -1) { | |
c9df1ce5 | 972 | irq = xen_allocate_irq_dynamic(); |
68ba45ff | 973 | if (irq < 0) |
7bee9768 | 974 | goto out; |
a52521f1 | 975 | |
77bb3dfd DV |
976 | if (percpu) |
977 | irq_set_chip_and_handler_name(irq, &xen_percpu_chip, | |
978 | handle_percpu_irq, "virq"); | |
979 | else | |
980 | irq_set_chip_and_handler_name(irq, &xen_dynamic_chip, | |
981 | handle_edge_irq, "virq"); | |
a52521f1 | 982 | |
e46cdb66 JF |
983 | bind_virq.virq = virq; |
984 | bind_virq.vcpu = cpu; | |
62cc5fc7 OH |
985 | ret = HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq, |
986 | &bind_virq); | |
987 | if (ret == 0) | |
988 | evtchn = bind_virq.port; | |
989 | else { | |
990 | if (ret == -EEXIST) | |
991 | ret = find_virq(virq, cpu); | |
992 | BUG_ON(ret < 0); | |
993 | evtchn = ret; | |
994 | } | |
e46cdb66 | 995 | |
96d4c588 DV |
996 | ret = xen_irq_info_virq_setup(cpu, irq, evtchn, virq); |
997 | if (ret < 0) { | |
998 | __unbind_from_irq(irq); | |
999 | irq = ret; | |
1000 | goto out; | |
1001 | } | |
e46cdb66 JF |
1002 | |
1003 | bind_evtchn_to_cpu(evtchn, cpu); | |
5e152e6c KRW |
1004 | } else { |
1005 | struct irq_info *info = info_for_irq(irq); | |
1006 | WARN_ON(info == NULL || info->type != IRQT_VIRQ); | |
e46cdb66 JF |
1007 | } |
1008 | ||
7bee9768 | 1009 | out: |
77365948 | 1010 | mutex_unlock(&irq_mapping_update_lock); |
e46cdb66 JF |
1011 | |
1012 | return irq; | |
1013 | } | |
1014 | ||
1015 | static void unbind_from_irq(unsigned int irq) | |
1016 | { | |
77365948 | 1017 | mutex_lock(&irq_mapping_update_lock); |
96d4c588 | 1018 | __unbind_from_irq(irq); |
77365948 | 1019 | mutex_unlock(&irq_mapping_update_lock); |
e46cdb66 JF |
1020 | } |
1021 | ||
1022 | int bind_evtchn_to_irqhandler(unsigned int evtchn, | |
7c239975 | 1023 | irq_handler_t handler, |
e46cdb66 JF |
1024 | unsigned long irqflags, |
1025 | const char *devname, void *dev_id) | |
1026 | { | |
361ae8cb | 1027 | int irq, retval; |
e46cdb66 JF |
1028 | |
1029 | irq = bind_evtchn_to_irq(evtchn); | |
7bee9768 IC |
1030 | if (irq < 0) |
1031 | return irq; | |
e46cdb66 JF |
1032 | retval = request_irq(irq, handler, irqflags, devname, dev_id); |
1033 | if (retval != 0) { | |
1034 | unbind_from_irq(irq); | |
1035 | return retval; | |
1036 | } | |
1037 | ||
1038 | return irq; | |
1039 | } | |
1040 | EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler); | |
1041 | ||
2e820f58 IC |
1042 | int bind_interdomain_evtchn_to_irqhandler(unsigned int remote_domain, |
1043 | unsigned int remote_port, | |
1044 | irq_handler_t handler, | |
1045 | unsigned long irqflags, | |
1046 | const char *devname, | |
1047 | void *dev_id) | |
1048 | { | |
1049 | int irq, retval; | |
1050 | ||
1051 | irq = bind_interdomain_evtchn_to_irq(remote_domain, remote_port); | |
1052 | if (irq < 0) | |
1053 | return irq; | |
1054 | ||
1055 | retval = request_irq(irq, handler, irqflags, devname, dev_id); | |
1056 | if (retval != 0) { | |
1057 | unbind_from_irq(irq); | |
1058 | return retval; | |
1059 | } | |
1060 | ||
1061 | return irq; | |
1062 | } | |
1063 | EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irqhandler); | |
1064 | ||
e46cdb66 | 1065 | int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu, |
7c239975 | 1066 | irq_handler_t handler, |
e46cdb66 JF |
1067 | unsigned long irqflags, const char *devname, void *dev_id) |
1068 | { | |
361ae8cb | 1069 | int irq, retval; |
e46cdb66 | 1070 | |
77bb3dfd | 1071 | irq = bind_virq_to_irq(virq, cpu, irqflags & IRQF_PERCPU); |
7bee9768 IC |
1072 | if (irq < 0) |
1073 | return irq; | |
e46cdb66 JF |
1074 | retval = request_irq(irq, handler, irqflags, devname, dev_id); |
1075 | if (retval != 0) { | |
1076 | unbind_from_irq(irq); | |
1077 | return retval; | |
1078 | } | |
1079 | ||
1080 | return irq; | |
1081 | } | |
1082 | EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler); | |
1083 | ||
f87e4cac JF |
1084 | int bind_ipi_to_irqhandler(enum ipi_vector ipi, |
1085 | unsigned int cpu, | |
1086 | irq_handler_t handler, | |
1087 | unsigned long irqflags, | |
1088 | const char *devname, | |
1089 | void *dev_id) | |
1090 | { | |
1091 | int irq, retval; | |
1092 | ||
1093 | irq = bind_ipi_to_irq(ipi, cpu); | |
1094 | if (irq < 0) | |
1095 | return irq; | |
1096 | ||
9bab0b7f | 1097 | irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME | IRQF_EARLY_RESUME; |
f87e4cac JF |
1098 | retval = request_irq(irq, handler, irqflags, devname, dev_id); |
1099 | if (retval != 0) { | |
1100 | unbind_from_irq(irq); | |
1101 | return retval; | |
1102 | } | |
1103 | ||
1104 | return irq; | |
1105 | } | |
1106 | ||
e46cdb66 JF |
1107 | void unbind_from_irqhandler(unsigned int irq, void *dev_id) |
1108 | { | |
94032c50 KRW |
1109 | struct irq_info *info = irq_get_handler_data(irq); |
1110 | ||
1111 | if (WARN_ON(!info)) | |
1112 | return; | |
e46cdb66 JF |
1113 | free_irq(irq, dev_id); |
1114 | unbind_from_irq(irq); | |
1115 | } | |
1116 | EXPORT_SYMBOL_GPL(unbind_from_irqhandler); | |
1117 | ||
6ccecb0f DV |
1118 | /** |
1119 | * xen_set_irq_priority() - set an event channel priority. | |
1120 | * @irq:irq bound to an event channel. | |
1121 | * @priority: priority between XEN_IRQ_PRIORITY_MAX and XEN_IRQ_PRIORITY_MIN. | |
1122 | */ | |
1123 | int xen_set_irq_priority(unsigned irq, unsigned priority) | |
1124 | { | |
1125 | struct evtchn_set_priority set_priority; | |
1126 | ||
1127 | set_priority.port = evtchn_from_irq(irq); | |
1128 | set_priority.priority = priority; | |
1129 | ||
1130 | return HYPERVISOR_event_channel_op(EVTCHNOP_set_priority, | |
1131 | &set_priority); | |
1132 | } | |
1133 | EXPORT_SYMBOL_GPL(xen_set_irq_priority); | |
1134 | ||
420eb554 DDG |
1135 | int evtchn_make_refcounted(unsigned int evtchn) |
1136 | { | |
d0b075ff | 1137 | int irq = get_evtchn_to_irq(evtchn); |
420eb554 DDG |
1138 | struct irq_info *info; |
1139 | ||
1140 | if (irq == -1) | |
1141 | return -ENOENT; | |
1142 | ||
1143 | info = irq_get_handler_data(irq); | |
1144 | ||
1145 | if (!info) | |
1146 | return -ENOENT; | |
1147 | ||
1148 | WARN_ON(info->refcnt != -1); | |
1149 | ||
1150 | info->refcnt = 1; | |
1151 | ||
1152 | return 0; | |
1153 | } | |
1154 | EXPORT_SYMBOL_GPL(evtchn_make_refcounted); | |
1155 | ||
1156 | int evtchn_get(unsigned int evtchn) | |
1157 | { | |
1158 | int irq; | |
1159 | struct irq_info *info; | |
1160 | int err = -ENOENT; | |
1161 | ||
d0b075ff | 1162 | if (evtchn >= xen_evtchn_max_channels()) |
c3b3f16d DDG |
1163 | return -EINVAL; |
1164 | ||
420eb554 DDG |
1165 | mutex_lock(&irq_mapping_update_lock); |
1166 | ||
d0b075ff | 1167 | irq = get_evtchn_to_irq(evtchn); |
420eb554 DDG |
1168 | if (irq == -1) |
1169 | goto done; | |
1170 | ||
1171 | info = irq_get_handler_data(irq); | |
1172 | ||
1173 | if (!info) | |
1174 | goto done; | |
1175 | ||
1176 | err = -EINVAL; | |
1177 | if (info->refcnt <= 0) | |
1178 | goto done; | |
1179 | ||
1180 | info->refcnt++; | |
1181 | err = 0; | |
1182 | done: | |
1183 | mutex_unlock(&irq_mapping_update_lock); | |
1184 | ||
1185 | return err; | |
1186 | } | |
1187 | EXPORT_SYMBOL_GPL(evtchn_get); | |
1188 | ||
1189 | void evtchn_put(unsigned int evtchn) | |
1190 | { | |
d0b075ff | 1191 | int irq = get_evtchn_to_irq(evtchn); |
420eb554 DDG |
1192 | if (WARN_ON(irq == -1)) |
1193 | return; | |
1194 | unbind_from_irq(irq); | |
1195 | } | |
1196 | EXPORT_SYMBOL_GPL(evtchn_put); | |
1197 | ||
f87e4cac JF |
1198 | void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector) |
1199 | { | |
6efa20e4 KRW |
1200 | int irq; |
1201 | ||
072b2064 | 1202 | #ifdef CONFIG_X86 |
6efa20e4 KRW |
1203 | if (unlikely(vector == XEN_NMI_VECTOR)) { |
1204 | int rc = HYPERVISOR_vcpu_op(VCPUOP_send_nmi, cpu, NULL); | |
1205 | if (rc < 0) | |
1206 | printk(KERN_WARNING "Sending nmi to CPU%d failed (rc:%d)\n", cpu, rc); | |
1207 | return; | |
1208 | } | |
072b2064 | 1209 | #endif |
6efa20e4 | 1210 | irq = per_cpu(ipi_to_irq, cpu)[vector]; |
f87e4cac JF |
1211 | BUG_ON(irq < 0); |
1212 | notify_remote_via_irq(irq); | |
1213 | } | |
1214 | ||
245b2e70 TH |
1215 | static DEFINE_PER_CPU(unsigned, xed_nesting_count); |
1216 | ||
38e20b07 | 1217 | static void __xen_evtchn_do_upcall(void) |
e46cdb66 | 1218 | { |
780f36d8 | 1219 | struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu); |
9a489f45 | 1220 | int cpu = get_cpu(); |
088c05a8 | 1221 | unsigned count; |
e46cdb66 | 1222 | |
229664be | 1223 | do { |
229664be | 1224 | vcpu_info->evtchn_upcall_pending = 0; |
e46cdb66 | 1225 | |
b2e4ae69 | 1226 | if (__this_cpu_inc_return(xed_nesting_count) - 1) |
229664be | 1227 | goto out; |
e46cdb66 | 1228 | |
9a489f45 | 1229 | xen_evtchn_handle_events(cpu); |
e46cdb66 | 1230 | |
229664be JF |
1231 | BUG_ON(!irqs_disabled()); |
1232 | ||
780f36d8 CL |
1233 | count = __this_cpu_read(xed_nesting_count); |
1234 | __this_cpu_write(xed_nesting_count, 0); | |
183d03cc | 1235 | } while (count != 1 || vcpu_info->evtchn_upcall_pending); |
229664be JF |
1236 | |
1237 | out: | |
38e20b07 SY |
1238 | |
1239 | put_cpu(); | |
1240 | } | |
1241 | ||
1242 | void xen_evtchn_do_upcall(struct pt_regs *regs) | |
1243 | { | |
1244 | struct pt_regs *old_regs = set_irq_regs(regs); | |
1245 | ||
772aebce | 1246 | irq_enter(); |
0ec53ecf | 1247 | #ifdef CONFIG_X86 |
38e20b07 | 1248 | exit_idle(); |
99c8b79d | 1249 | inc_irq_stat(irq_hv_callback_count); |
d06eb3ee | 1250 | #endif |
38e20b07 SY |
1251 | |
1252 | __xen_evtchn_do_upcall(); | |
1253 | ||
3445a8fd JF |
1254 | irq_exit(); |
1255 | set_irq_regs(old_regs); | |
38e20b07 | 1256 | } |
3445a8fd | 1257 | |
38e20b07 SY |
1258 | void xen_hvm_evtchn_do_upcall(void) |
1259 | { | |
1260 | __xen_evtchn_do_upcall(); | |
e46cdb66 | 1261 | } |
183d03cc | 1262 | EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall); |
e46cdb66 | 1263 | |
eb1e305f JF |
1264 | /* Rebind a new event channel to an existing irq. */ |
1265 | void rebind_evtchn_irq(int evtchn, int irq) | |
1266 | { | |
d77bbd4d JF |
1267 | struct irq_info *info = info_for_irq(irq); |
1268 | ||
94032c50 KRW |
1269 | if (WARN_ON(!info)) |
1270 | return; | |
1271 | ||
eb1e305f JF |
1272 | /* Make sure the irq is masked, since the new event channel |
1273 | will also be masked. */ | |
1274 | disable_irq(irq); | |
1275 | ||
77365948 | 1276 | mutex_lock(&irq_mapping_update_lock); |
eb1e305f JF |
1277 | |
1278 | /* After resume the irq<->evtchn mappings are all cleared out */ | |
d0b075ff | 1279 | BUG_ON(get_evtchn_to_irq(evtchn) != -1); |
eb1e305f | 1280 | /* Expect irq to have been bound before, |
d77bbd4d JF |
1281 | so there should be a proper type */ |
1282 | BUG_ON(info->type == IRQT_UNBOUND); | |
eb1e305f | 1283 | |
96d4c588 | 1284 | (void)xen_irq_info_evtchn_setup(irq, evtchn); |
eb1e305f | 1285 | |
77365948 | 1286 | mutex_unlock(&irq_mapping_update_lock); |
eb1e305f | 1287 | |
5cec9883 BO |
1288 | bind_evtchn_to_cpu(evtchn, info->cpu); |
1289 | /* This will be deferred until interrupt is processed */ | |
1290 | irq_set_affinity(irq, cpumask_of(info->cpu)); | |
eb1e305f JF |
1291 | |
1292 | /* Unmask the event channel. */ | |
1293 | enable_irq(irq); | |
1294 | } | |
1295 | ||
e46cdb66 | 1296 | /* Rebind an evtchn so that it gets delivered to a specific cpu */ |
d5dedd45 | 1297 | static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu) |
e46cdb66 JF |
1298 | { |
1299 | struct evtchn_bind_vcpu bind_vcpu; | |
1300 | int evtchn = evtchn_from_irq(irq); | |
4704fe4f | 1301 | int masked; |
e46cdb66 | 1302 | |
be49472f IC |
1303 | if (!VALID_EVTCHN(evtchn)) |
1304 | return -1; | |
1305 | ||
1306 | /* | |
1307 | * Events delivered via platform PCI interrupts are always | |
1308 | * routed to vcpu 0 and hence cannot be rebound. | |
1309 | */ | |
1310 | if (xen_hvm_domain() && !xen_have_vector_callback) | |
d5dedd45 | 1311 | return -1; |
e46cdb66 JF |
1312 | |
1313 | /* Send future instances of this interrupt to other vcpu. */ | |
1314 | bind_vcpu.port = evtchn; | |
1315 | bind_vcpu.vcpu = tcpu; | |
1316 | ||
4704fe4f DV |
1317 | /* |
1318 | * Mask the event while changing the VCPU binding to prevent | |
1319 | * it being delivered on an unexpected VCPU. | |
1320 | */ | |
3f70fa82 | 1321 | masked = test_and_set_mask(evtchn); |
4704fe4f | 1322 | |
e46cdb66 JF |
1323 | /* |
1324 | * If this fails, it usually just indicates that we're dealing with a | |
1325 | * virq or IPI channel, which don't actually need to be rebound. Ignore | |
1326 | * it, but don't do the xenlinux-level rebind in that case. | |
1327 | */ | |
1328 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0) | |
1329 | bind_evtchn_to_cpu(evtchn, tcpu); | |
e46cdb66 | 1330 | |
4704fe4f DV |
1331 | if (!masked) |
1332 | unmask_evtchn(evtchn); | |
1333 | ||
d5dedd45 YL |
1334 | return 0; |
1335 | } | |
e46cdb66 | 1336 | |
c9e265e0 TG |
1337 | static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest, |
1338 | bool force) | |
e46cdb66 | 1339 | { |
753fbd23 | 1340 | unsigned tcpu = cpumask_first_and(dest, cpu_online_mask); |
d5dedd45 | 1341 | |
c9e265e0 | 1342 | return rebind_irq_to_cpu(data->irq, tcpu); |
e46cdb66 JF |
1343 | } |
1344 | ||
c9e265e0 | 1345 | static void enable_dynirq(struct irq_data *data) |
e46cdb66 | 1346 | { |
c9e265e0 | 1347 | int evtchn = evtchn_from_irq(data->irq); |
e46cdb66 JF |
1348 | |
1349 | if (VALID_EVTCHN(evtchn)) | |
1350 | unmask_evtchn(evtchn); | |
1351 | } | |
1352 | ||
c9e265e0 | 1353 | static void disable_dynirq(struct irq_data *data) |
e46cdb66 | 1354 | { |
c9e265e0 | 1355 | int evtchn = evtchn_from_irq(data->irq); |
e46cdb66 JF |
1356 | |
1357 | if (VALID_EVTCHN(evtchn)) | |
1358 | mask_evtchn(evtchn); | |
1359 | } | |
1360 | ||
c9e265e0 | 1361 | static void ack_dynirq(struct irq_data *data) |
e46cdb66 | 1362 | { |
c9e265e0 | 1363 | int evtchn = evtchn_from_irq(data->irq); |
e46cdb66 | 1364 | |
7e186bdd | 1365 | irq_move_irq(data); |
e46cdb66 JF |
1366 | |
1367 | if (VALID_EVTCHN(evtchn)) | |
7e186bdd SS |
1368 | clear_evtchn(evtchn); |
1369 | } | |
1370 | ||
1371 | static void mask_ack_dynirq(struct irq_data *data) | |
1372 | { | |
1373 | disable_dynirq(data); | |
1374 | ack_dynirq(data); | |
e46cdb66 JF |
1375 | } |
1376 | ||
c9e265e0 | 1377 | static int retrigger_dynirq(struct irq_data *data) |
e46cdb66 | 1378 | { |
4640ddf5 DV |
1379 | unsigned int evtchn = evtchn_from_irq(data->irq); |
1380 | int masked; | |
1381 | ||
1382 | if (!VALID_EVTCHN(evtchn)) | |
1383 | return 0; | |
1384 | ||
1385 | masked = test_and_set_mask(evtchn); | |
1386 | set_evtchn(evtchn); | |
1387 | if (!masked) | |
1388 | unmask_evtchn(evtchn); | |
1389 | ||
1390 | return 1; | |
e46cdb66 JF |
1391 | } |
1392 | ||
0a85226f | 1393 | static void restore_pirqs(void) |
9a069c33 SS |
1394 | { |
1395 | int pirq, rc, irq, gsi; | |
1396 | struct physdev_map_pirq map_irq; | |
69c358ce | 1397 | struct irq_info *info; |
9a069c33 | 1398 | |
69c358ce IC |
1399 | list_for_each_entry(info, &xen_irq_list_head, list) { |
1400 | if (info->type != IRQT_PIRQ) | |
9a069c33 SS |
1401 | continue; |
1402 | ||
69c358ce IC |
1403 | pirq = info->u.pirq.pirq; |
1404 | gsi = info->u.pirq.gsi; | |
1405 | irq = info->irq; | |
1406 | ||
9a069c33 SS |
1407 | /* save/restore of PT devices doesn't work, so at this point the |
1408 | * only devices present are GSI based emulated devices */ | |
9a069c33 SS |
1409 | if (!gsi) |
1410 | continue; | |
1411 | ||
1412 | map_irq.domid = DOMID_SELF; | |
1413 | map_irq.type = MAP_PIRQ_TYPE_GSI; | |
1414 | map_irq.index = gsi; | |
1415 | map_irq.pirq = pirq; | |
1416 | ||
1417 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq); | |
1418 | if (rc) { | |
283c0972 JP |
1419 | pr_warn("xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n", |
1420 | gsi, irq, pirq, rc); | |
9158c358 | 1421 | xen_free_irq(irq); |
9a069c33 SS |
1422 | continue; |
1423 | } | |
1424 | ||
1425 | printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq); | |
1426 | ||
c9e265e0 | 1427 | __startup_pirq(irq); |
9a069c33 SS |
1428 | } |
1429 | } | |
1430 | ||
0e91398f JF |
1431 | static void restore_cpu_virqs(unsigned int cpu) |
1432 | { | |
1433 | struct evtchn_bind_virq bind_virq; | |
1434 | int virq, irq, evtchn; | |
1435 | ||
1436 | for (virq = 0; virq < NR_VIRQS; virq++) { | |
1437 | if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1) | |
1438 | continue; | |
1439 | ||
ced40d0f | 1440 | BUG_ON(virq_from_irq(irq) != virq); |
0e91398f JF |
1441 | |
1442 | /* Get a new binding from Xen. */ | |
1443 | bind_virq.virq = virq; | |
1444 | bind_virq.vcpu = cpu; | |
1445 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq, | |
1446 | &bind_virq) != 0) | |
1447 | BUG(); | |
1448 | evtchn = bind_virq.port; | |
1449 | ||
1450 | /* Record the new mapping. */ | |
96d4c588 | 1451 | (void)xen_irq_info_virq_setup(cpu, irq, evtchn, virq); |
0e91398f | 1452 | bind_evtchn_to_cpu(evtchn, cpu); |
0e91398f JF |
1453 | } |
1454 | } | |
1455 | ||
1456 | static void restore_cpu_ipis(unsigned int cpu) | |
1457 | { | |
1458 | struct evtchn_bind_ipi bind_ipi; | |
1459 | int ipi, irq, evtchn; | |
1460 | ||
1461 | for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) { | |
1462 | if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1) | |
1463 | continue; | |
1464 | ||
ced40d0f | 1465 | BUG_ON(ipi_from_irq(irq) != ipi); |
0e91398f JF |
1466 | |
1467 | /* Get a new binding from Xen. */ | |
1468 | bind_ipi.vcpu = cpu; | |
1469 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi, | |
1470 | &bind_ipi) != 0) | |
1471 | BUG(); | |
1472 | evtchn = bind_ipi.port; | |
1473 | ||
1474 | /* Record the new mapping. */ | |
96d4c588 | 1475 | (void)xen_irq_info_ipi_setup(cpu, irq, evtchn, ipi); |
0e91398f | 1476 | bind_evtchn_to_cpu(evtchn, cpu); |
0e91398f JF |
1477 | } |
1478 | } | |
1479 | ||
2d9e1e2f JF |
1480 | /* Clear an irq's pending state, in preparation for polling on it */ |
1481 | void xen_clear_irq_pending(int irq) | |
1482 | { | |
1483 | int evtchn = evtchn_from_irq(irq); | |
1484 | ||
1485 | if (VALID_EVTCHN(evtchn)) | |
1486 | clear_evtchn(evtchn); | |
1487 | } | |
d9a8814f | 1488 | EXPORT_SYMBOL(xen_clear_irq_pending); |
168d2f46 JF |
1489 | void xen_set_irq_pending(int irq) |
1490 | { | |
1491 | int evtchn = evtchn_from_irq(irq); | |
1492 | ||
1493 | if (VALID_EVTCHN(evtchn)) | |
1494 | set_evtchn(evtchn); | |
1495 | } | |
1496 | ||
1497 | bool xen_test_irq_pending(int irq) | |
1498 | { | |
1499 | int evtchn = evtchn_from_irq(irq); | |
1500 | bool ret = false; | |
1501 | ||
1502 | if (VALID_EVTCHN(evtchn)) | |
1503 | ret = test_evtchn(evtchn); | |
1504 | ||
1505 | return ret; | |
1506 | } | |
1507 | ||
d9a8814f KRW |
1508 | /* Poll waiting for an irq to become pending with timeout. In the usual case, |
1509 | * the irq will be disabled so it won't deliver an interrupt. */ | |
1510 | void xen_poll_irq_timeout(int irq, u64 timeout) | |
2d9e1e2f JF |
1511 | { |
1512 | evtchn_port_t evtchn = evtchn_from_irq(irq); | |
1513 | ||
1514 | if (VALID_EVTCHN(evtchn)) { | |
1515 | struct sched_poll poll; | |
1516 | ||
1517 | poll.nr_ports = 1; | |
d9a8814f | 1518 | poll.timeout = timeout; |
ff3c5362 | 1519 | set_xen_guest_handle(poll.ports, &evtchn); |
2d9e1e2f JF |
1520 | |
1521 | if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0) | |
1522 | BUG(); | |
1523 | } | |
1524 | } | |
d9a8814f KRW |
1525 | EXPORT_SYMBOL(xen_poll_irq_timeout); |
1526 | /* Poll waiting for an irq to become pending. In the usual case, the | |
1527 | * irq will be disabled so it won't deliver an interrupt. */ | |
1528 | void xen_poll_irq(int irq) | |
1529 | { | |
1530 | xen_poll_irq_timeout(irq, 0 /* no timeout */); | |
1531 | } | |
2d9e1e2f | 1532 | |
c7c2c3a2 KRW |
1533 | /* Check whether the IRQ line is shared with other guests. */ |
1534 | int xen_test_irq_shared(int irq) | |
1535 | { | |
1536 | struct irq_info *info = info_for_irq(irq); | |
94032c50 KRW |
1537 | struct physdev_irq_status_query irq_status; |
1538 | ||
1539 | if (WARN_ON(!info)) | |
1540 | return -ENOENT; | |
1541 | ||
1542 | irq_status.irq = info->u.pirq.pirq; | |
c7c2c3a2 KRW |
1543 | |
1544 | if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status)) | |
1545 | return 0; | |
1546 | return !(irq_status.flags & XENIRQSTAT_shared); | |
1547 | } | |
1548 | EXPORT_SYMBOL_GPL(xen_test_irq_shared); | |
1549 | ||
0e91398f JF |
1550 | void xen_irq_resume(void) |
1551 | { | |
fd21069d | 1552 | unsigned int cpu; |
6cb6537d | 1553 | struct irq_info *info; |
0e91398f | 1554 | |
0e91398f | 1555 | /* New event-channel space is not 'live' yet. */ |
fd21069d | 1556 | xen_evtchn_mask_all(); |
1fe56551 | 1557 | xen_evtchn_resume(); |
0e91398f JF |
1558 | |
1559 | /* No IRQ <-> event-channel mappings. */ | |
6cb6537d IC |
1560 | list_for_each_entry(info, &xen_irq_list_head, list) |
1561 | info->evtchn = 0; /* zap event-channel binding */ | |
0e91398f | 1562 | |
d0b075ff | 1563 | clear_evtchn_to_irq_all(); |
0e91398f JF |
1564 | |
1565 | for_each_possible_cpu(cpu) { | |
1566 | restore_cpu_virqs(cpu); | |
1567 | restore_cpu_ipis(cpu); | |
1568 | } | |
6903591f | 1569 | |
0a85226f | 1570 | restore_pirqs(); |
0e91398f JF |
1571 | } |
1572 | ||
e46cdb66 | 1573 | static struct irq_chip xen_dynamic_chip __read_mostly = { |
c9e265e0 | 1574 | .name = "xen-dyn", |
54a353a0 | 1575 | |
c9e265e0 TG |
1576 | .irq_disable = disable_dynirq, |
1577 | .irq_mask = disable_dynirq, | |
1578 | .irq_unmask = enable_dynirq, | |
54a353a0 | 1579 | |
7e186bdd SS |
1580 | .irq_ack = ack_dynirq, |
1581 | .irq_mask_ack = mask_ack_dynirq, | |
1582 | ||
c9e265e0 TG |
1583 | .irq_set_affinity = set_affinity_irq, |
1584 | .irq_retrigger = retrigger_dynirq, | |
e46cdb66 JF |
1585 | }; |
1586 | ||
d46a78b0 | 1587 | static struct irq_chip xen_pirq_chip __read_mostly = { |
c9e265e0 | 1588 | .name = "xen-pirq", |
d46a78b0 | 1589 | |
c9e265e0 TG |
1590 | .irq_startup = startup_pirq, |
1591 | .irq_shutdown = shutdown_pirq, | |
c9e265e0 | 1592 | .irq_enable = enable_pirq, |
c9e265e0 | 1593 | .irq_disable = disable_pirq, |
d46a78b0 | 1594 | |
7e186bdd SS |
1595 | .irq_mask = disable_dynirq, |
1596 | .irq_unmask = enable_dynirq, | |
1597 | ||
1598 | .irq_ack = eoi_pirq, | |
1599 | .irq_eoi = eoi_pirq, | |
1600 | .irq_mask_ack = mask_ack_pirq, | |
d46a78b0 | 1601 | |
c9e265e0 | 1602 | .irq_set_affinity = set_affinity_irq, |
d46a78b0 | 1603 | |
c9e265e0 | 1604 | .irq_retrigger = retrigger_dynirq, |
d46a78b0 JF |
1605 | }; |
1606 | ||
aaca4964 | 1607 | static struct irq_chip xen_percpu_chip __read_mostly = { |
c9e265e0 | 1608 | .name = "xen-percpu", |
aaca4964 | 1609 | |
c9e265e0 TG |
1610 | .irq_disable = disable_dynirq, |
1611 | .irq_mask = disable_dynirq, | |
1612 | .irq_unmask = enable_dynirq, | |
aaca4964 | 1613 | |
c9e265e0 | 1614 | .irq_ack = ack_dynirq, |
aaca4964 JF |
1615 | }; |
1616 | ||
38e20b07 SY |
1617 | int xen_set_callback_via(uint64_t via) |
1618 | { | |
1619 | struct xen_hvm_param a; | |
1620 | a.domid = DOMID_SELF; | |
1621 | a.index = HVM_PARAM_CALLBACK_IRQ; | |
1622 | a.value = via; | |
1623 | return HYPERVISOR_hvm_op(HVMOP_set_param, &a); | |
1624 | } | |
1625 | EXPORT_SYMBOL_GPL(xen_set_callback_via); | |
1626 | ||
ca65f9fc | 1627 | #ifdef CONFIG_XEN_PVHVM |
38e20b07 SY |
1628 | /* Vector callbacks are better than PCI interrupts to receive event |
1629 | * channel notifications because we can receive vector callbacks on any | |
1630 | * vcpu and we don't need PCI support or APIC interactions. */ | |
1631 | void xen_callback_vector(void) | |
1632 | { | |
1633 | int rc; | |
1634 | uint64_t callback_via; | |
1635 | if (xen_have_vector_callback) { | |
bc2b0331 | 1636 | callback_via = HVM_CALLBACK_VECTOR(HYPERVISOR_CALLBACK_VECTOR); |
38e20b07 SY |
1637 | rc = xen_set_callback_via(callback_via); |
1638 | if (rc) { | |
283c0972 | 1639 | pr_err("Request for Xen HVM callback vector failed\n"); |
38e20b07 SY |
1640 | xen_have_vector_callback = 0; |
1641 | return; | |
1642 | } | |
283c0972 | 1643 | pr_info("Xen HVM callback vector for event delivery is enabled\n"); |
38e20b07 | 1644 | /* in the restore case the vector has already been allocated */ |
bc2b0331 S |
1645 | if (!test_bit(HYPERVISOR_CALLBACK_VECTOR, used_vectors)) |
1646 | alloc_intr_gate(HYPERVISOR_CALLBACK_VECTOR, | |
1647 | xen_hvm_callback_vector); | |
38e20b07 SY |
1648 | } |
1649 | } | |
ca65f9fc SS |
1650 | #else |
1651 | void xen_callback_vector(void) {} | |
1652 | #endif | |
38e20b07 | 1653 | |
1fe56551 DV |
1654 | #undef MODULE_PARAM_PREFIX |
1655 | #define MODULE_PARAM_PREFIX "xen." | |
1656 | ||
1657 | static bool fifo_events = true; | |
1658 | module_param(fifo_events, bool, 0); | |
1659 | ||
2e3d8860 | 1660 | void __init xen_init_IRQ(void) |
e46cdb66 | 1661 | { |
1fe56551 DV |
1662 | int ret = -EINVAL; |
1663 | ||
1664 | if (fifo_events) | |
1665 | ret = xen_evtchn_fifo_init(); | |
1666 | if (ret < 0) | |
1667 | xen_evtchn_2l_init(); | |
ab9a1cca | 1668 | |
d0b075ff DV |
1669 | evtchn_to_irq = kcalloc(EVTCHN_ROW(xen_evtchn_max_channels()), |
1670 | sizeof(*evtchn_to_irq), GFP_KERNEL); | |
9d093e29 | 1671 | BUG_ON(!evtchn_to_irq); |
e46cdb66 | 1672 | |
e46cdb66 | 1673 | /* No event channels are 'live' right now. */ |
fd21069d | 1674 | xen_evtchn_mask_all(); |
e46cdb66 | 1675 | |
9846ff10 SS |
1676 | pirq_needs_eoi = pirq_needs_eoi_flag; |
1677 | ||
0ec53ecf | 1678 | #ifdef CONFIG_X86 |
2771374d MR |
1679 | if (xen_pv_domain()) { |
1680 | irq_ctx_init(smp_processor_id()); | |
1681 | if (xen_initial_domain()) | |
1682 | pci_xen_initial_domain(); | |
1683 | } | |
1684 | if (xen_feature(XENFEAT_hvm_callback_vector)) | |
38e20b07 | 1685 | xen_callback_vector(); |
2771374d MR |
1686 | |
1687 | if (xen_hvm_domain()) { | |
38e20b07 | 1688 | native_init_IRQ(); |
3942b740 SS |
1689 | /* pci_xen_hvm_init must be called after native_init_IRQ so that |
1690 | * __acpi_register_gsi can point at the right function */ | |
1691 | pci_xen_hvm_init(); | |
38e20b07 | 1692 | } else { |
0ec53ecf | 1693 | int rc; |
9846ff10 SS |
1694 | struct physdev_pirq_eoi_gmfn eoi_gmfn; |
1695 | ||
9846ff10 SS |
1696 | pirq_eoi_map = (void *)__get_free_page(GFP_KERNEL|__GFP_ZERO); |
1697 | eoi_gmfn.gmfn = virt_to_mfn(pirq_eoi_map); | |
1698 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_pirq_eoi_gmfn_v2, &eoi_gmfn); | |
2771374d | 1699 | /* TODO: No PVH support for PIRQ EOI */ |
9846ff10 SS |
1700 | if (rc != 0) { |
1701 | free_page((unsigned long) pirq_eoi_map); | |
1702 | pirq_eoi_map = NULL; | |
1703 | } else | |
1704 | pirq_needs_eoi = pirq_check_eoi_map; | |
38e20b07 | 1705 | } |
0ec53ecf | 1706 | #endif |
e46cdb66 | 1707 | } |