Merge tag 'gpio-v3.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw...
[deliverable/linux.git] / drivers / xen / events.c
CommitLineData
e46cdb66
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1/*
2 * Xen event channels
3 *
4 * Xen models interrupts with abstract event channels. Because each
5 * domain gets 1024 event channels, but NR_IRQ is not that large, we
6 * must dynamically map irqs<->event channels. The event channels
7 * interface with the rest of the kernel by defining a xen interrupt
25985edc 8 * chip. When an event is received, it is mapped to an irq and sent
e46cdb66
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9 * through the normal interrupt processing path.
10 *
11 * There are four kinds of events which can be mapped to an event
12 * channel:
13 *
14 * 1. Inter-domain notifications. This includes all the virtual
15 * device events, since they're driven by front-ends in another domain
16 * (typically dom0).
17 * 2. VIRQs, typically used for timers. These are per-cpu events.
18 * 3. IPIs.
d46a78b0 19 * 4. PIRQs - Hardware interrupts.
e46cdb66
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20 *
21 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
22 */
23
283c0972
JP
24#define pr_fmt(fmt) "xen:" KBUILD_MODNAME ": " fmt
25
e46cdb66
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26#include <linux/linkage.h>
27#include <linux/interrupt.h>
28#include <linux/irq.h>
29#include <linux/module.h>
30#include <linux/string.h>
28e08861 31#include <linux/bootmem.h>
5a0e3ad6 32#include <linux/slab.h>
b21ddbf5 33#include <linux/irqnr.h>
f731e3ef 34#include <linux/pci.h>
e46cdb66 35
0ec53ecf 36#ifdef CONFIG_X86
38e20b07 37#include <asm/desc.h>
e46cdb66
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38#include <asm/ptrace.h>
39#include <asm/irq.h>
792dc4f6 40#include <asm/idle.h>
0794bfc7 41#include <asm/io_apic.h>
9846ff10 42#include <asm/xen/page.h>
42a1de56 43#include <asm/xen/pci.h>
0ec53ecf
SS
44#endif
45#include <asm/sync_bitops.h>
e46cdb66 46#include <asm/xen/hypercall.h>
8d1b8753 47#include <asm/xen/hypervisor.h>
e46cdb66 48
38e20b07
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49#include <xen/xen.h>
50#include <xen/hvm.h>
e04d0d07 51#include <xen/xen-ops.h>
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52#include <xen/events.h>
53#include <xen/interface/xen.h>
54#include <xen/interface/event_channel.h>
38e20b07
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55#include <xen/interface/hvm/hvm_op.h>
56#include <xen/interface/hvm/params.h>
0ec53ecf
SS
57#include <xen/interface/physdev.h>
58#include <xen/interface/sched.h>
6efa20e4 59#include <xen/interface/vcpu.h>
0ec53ecf 60#include <asm/hw_irq.h>
e46cdb66 61
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62/*
63 * This lock protects updates to the following mapping and reference-count
64 * arrays. The lock does not need to be acquired to read the mapping tables.
65 */
77365948 66static DEFINE_MUTEX(irq_mapping_update_lock);
e46cdb66 67
6cb6537d
IC
68static LIST_HEAD(xen_irq_list_head);
69
e46cdb66 70/* IRQ <-> VIRQ mapping. */
204fba4a 71static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
e46cdb66 72
f87e4cac 73/* IRQ <-> IPI mapping */
204fba4a 74static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
f87e4cac 75
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76/* Interrupt types. */
77enum xen_irq_type {
d77bbd4d 78 IRQT_UNBOUND = 0,
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79 IRQT_PIRQ,
80 IRQT_VIRQ,
81 IRQT_IPI,
82 IRQT_EVTCHN
83};
e46cdb66 84
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85/*
86 * Packed IRQ information:
87 * type - enum xen_irq_type
88 * event channel - irq->event channel mapping
89 * cpu - cpu this event channel is bound to
90 * index - type-specific information:
dec02dea 91 * PIRQ - physical IRQ, GSI, flags, and owner domain
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92 * VIRQ - virq number
93 * IPI - IPI vector
94 * EVTCHN -
95 */
088c05a8 96struct irq_info {
6cb6537d 97 struct list_head list;
420eb554 98 int refcnt;
ced40d0f 99 enum xen_irq_type type; /* type */
6cb6537d 100 unsigned irq;
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101 unsigned short evtchn; /* event channel */
102 unsigned short cpu; /* cpu bound */
103
104 union {
105 unsigned short virq;
106 enum ipi_vector ipi;
107 struct {
7a043f11 108 unsigned short pirq;
ced40d0f 109 unsigned short gsi;
d46a78b0 110 unsigned char flags;
beafbdc1 111 uint16_t domid;
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112 } pirq;
113 } u;
114};
d46a78b0 115#define PIRQ_NEEDS_EOI (1 << 0)
15ebbb82 116#define PIRQ_SHAREABLE (1 << 1)
ced40d0f 117
b21ddbf5 118static int *evtchn_to_irq;
bf86ad80 119#ifdef CONFIG_X86
9846ff10 120static unsigned long *pirq_eoi_map;
bf86ad80 121#endif
9846ff10 122static bool (*pirq_needs_eoi)(unsigned irq);
3b32f574 123
c81611c4
IC
124/*
125 * Note sizeof(xen_ulong_t) can be more than sizeof(unsigned long). Be
126 * careful to only use bitops which allow for this (e.g
127 * test_bit/find_first_bit and friends but not __ffs) and to pass
128 * BITS_PER_EVTCHN_WORD as the bitmask length.
129 */
130#define BITS_PER_EVTCHN_WORD (sizeof(xen_ulong_t)*8)
131/*
132 * Make a bitmask (i.e. unsigned long *) of a xen_ulong_t
133 * array. Primarily to avoid long lines (hence the terse name).
134 */
135#define BM(x) (unsigned long *)(x)
136/* Find the first set bit in a evtchn mask */
137#define EVTCHN_FIRST_BIT(w) find_first_bit(BM(&(w)), BITS_PER_EVTCHN_WORD)
138
139static DEFINE_PER_CPU(xen_ulong_t [NR_EVENT_CHANNELS/BITS_PER_EVTCHN_WORD],
cb60d114 140 cpu_evtchn_mask);
e46cdb66 141
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142/* Xen will never allocate port zero for any purpose. */
143#define VALID_EVTCHN(chn) ((chn) != 0)
144
e46cdb66 145static struct irq_chip xen_dynamic_chip;
aaca4964 146static struct irq_chip xen_percpu_chip;
d46a78b0 147static struct irq_chip xen_pirq_chip;
7e186bdd
SS
148static void enable_dynirq(struct irq_data *data);
149static void disable_dynirq(struct irq_data *data);
e46cdb66 150
9158c358
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151/* Get info for IRQ */
152static struct irq_info *info_for_irq(unsigned irq)
ced40d0f 153{
c442b806 154 return irq_get_handler_data(irq);
ced40d0f
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155}
156
9158c358
IC
157/* Constructors for packed IRQ information. */
158static void xen_irq_info_common_init(struct irq_info *info,
3d4cfa37 159 unsigned irq,
9158c358
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160 enum xen_irq_type type,
161 unsigned short evtchn,
162 unsigned short cpu)
ced40d0f 163{
9158c358
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164
165 BUG_ON(info->type != IRQT_UNBOUND && info->type != type);
166
167 info->type = type;
6cb6537d 168 info->irq = irq;
9158c358
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169 info->evtchn = evtchn;
170 info->cpu = cpu;
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171
172 evtchn_to_irq[evtchn] = irq;
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173
174 irq_clear_status_flags(irq, IRQ_NOREQUEST|IRQ_NOAUTOEN);
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175}
176
9158c358
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177static void xen_irq_info_evtchn_init(unsigned irq,
178 unsigned short evtchn)
ced40d0f 179{
9158c358
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180 struct irq_info *info = info_for_irq(irq);
181
3d4cfa37 182 xen_irq_info_common_init(info, irq, IRQT_EVTCHN, evtchn, 0);
ced40d0f
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183}
184
3d4cfa37
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185static void xen_irq_info_ipi_init(unsigned cpu,
186 unsigned irq,
9158c358
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187 unsigned short evtchn,
188 enum ipi_vector ipi)
e46cdb66 189{
9158c358
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190 struct irq_info *info = info_for_irq(irq);
191
3d4cfa37 192 xen_irq_info_common_init(info, irq, IRQT_IPI, evtchn, 0);
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193
194 info->u.ipi = ipi;
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195
196 per_cpu(ipi_to_irq, cpu)[ipi] = irq;
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197}
198
3d4cfa37
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199static void xen_irq_info_virq_init(unsigned cpu,
200 unsigned irq,
9158c358
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201 unsigned short evtchn,
202 unsigned short virq)
ced40d0f 203{
9158c358
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204 struct irq_info *info = info_for_irq(irq);
205
3d4cfa37 206 xen_irq_info_common_init(info, irq, IRQT_VIRQ, evtchn, 0);
9158c358
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207
208 info->u.virq = virq;
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209
210 per_cpu(virq_to_irq, cpu)[virq] = irq;
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211}
212
9158c358
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213static void xen_irq_info_pirq_init(unsigned irq,
214 unsigned short evtchn,
215 unsigned short pirq,
216 unsigned short gsi,
beafbdc1 217 uint16_t domid,
9158c358 218 unsigned char flags)
ced40d0f 219{
9158c358
IC
220 struct irq_info *info = info_for_irq(irq);
221
3d4cfa37 222 xen_irq_info_common_init(info, irq, IRQT_PIRQ, evtchn, 0);
9158c358
IC
223
224 info->u.pirq.pirq = pirq;
225 info->u.pirq.gsi = gsi;
beafbdc1 226 info->u.pirq.domid = domid;
9158c358 227 info->u.pirq.flags = flags;
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228}
229
230/*
231 * Accessors for packed IRQ information.
232 */
ced40d0f 233static unsigned int evtchn_from_irq(unsigned irq)
e46cdb66 234{
110e7c7e
JJ
235 if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
236 return 0;
237
ced40d0f 238 return info_for_irq(irq)->evtchn;
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239}
240
d4c04536
IC
241unsigned irq_from_evtchn(unsigned int evtchn)
242{
243 return evtchn_to_irq[evtchn];
244}
245EXPORT_SYMBOL_GPL(irq_from_evtchn);
246
ced40d0f 247static enum ipi_vector ipi_from_irq(unsigned irq)
e46cdb66 248{
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249 struct irq_info *info = info_for_irq(irq);
250
251 BUG_ON(info == NULL);
252 BUG_ON(info->type != IRQT_IPI);
253
254 return info->u.ipi;
255}
256
257static unsigned virq_from_irq(unsigned irq)
258{
259 struct irq_info *info = info_for_irq(irq);
260
261 BUG_ON(info == NULL);
262 BUG_ON(info->type != IRQT_VIRQ);
263
264 return info->u.virq;
265}
266
7a043f11
SS
267static unsigned pirq_from_irq(unsigned irq)
268{
269 struct irq_info *info = info_for_irq(irq);
270
271 BUG_ON(info == NULL);
272 BUG_ON(info->type != IRQT_PIRQ);
273
274 return info->u.pirq.pirq;
275}
276
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277static enum xen_irq_type type_from_irq(unsigned irq)
278{
279 return info_for_irq(irq)->type;
280}
281
282static unsigned cpu_from_irq(unsigned irq)
283{
284 return info_for_irq(irq)->cpu;
285}
286
287static unsigned int cpu_from_evtchn(unsigned int evtchn)
288{
289 int irq = evtchn_to_irq[evtchn];
290 unsigned ret = 0;
291
292 if (irq != -1)
293 ret = cpu_from_irq(irq);
294
295 return ret;
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296}
297
bf86ad80 298#ifdef CONFIG_X86
9846ff10 299static bool pirq_check_eoi_map(unsigned irq)
d46a78b0 300{
521394e4 301 return test_bit(pirq_from_irq(irq), pirq_eoi_map);
9846ff10 302}
bf86ad80 303#endif
d46a78b0 304
9846ff10
SS
305static bool pirq_needs_eoi_flag(unsigned irq)
306{
307 struct irq_info *info = info_for_irq(irq);
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308 BUG_ON(info->type != IRQT_PIRQ);
309
310 return info->u.pirq.flags & PIRQ_NEEDS_EOI;
311}
312
c81611c4
IC
313static inline xen_ulong_t active_evtchns(unsigned int cpu,
314 struct shared_info *sh,
315 unsigned int idx)
e46cdb66 316{
088c05a8 317 return sh->evtchn_pending[idx] &
cb60d114 318 per_cpu(cpu_evtchn_mask, cpu)[idx] &
088c05a8 319 ~sh->evtchn_mask[idx];
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320}
321
322static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
323{
324 int irq = evtchn_to_irq[chn];
325
326 BUG_ON(irq == -1);
327#ifdef CONFIG_SMP
c9e265e0 328 cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu));
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329#endif
330
c81611c4
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331 clear_bit(chn, BM(per_cpu(cpu_evtchn_mask, cpu_from_irq(irq))));
332 set_bit(chn, BM(per_cpu(cpu_evtchn_mask, cpu)));
e46cdb66 333
ca62ce8c 334 info_for_irq(irq)->cpu = cpu;
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335}
336
337static void init_evtchn_cpu_bindings(void)
338{
1c6969ec 339 int i;
e46cdb66 340#ifdef CONFIG_SMP
6cb6537d 341 struct irq_info *info;
10e58084 342
e46cdb66 343 /* By default all event channels notify CPU#0. */
6cb6537d
IC
344 list_for_each_entry(info, &xen_irq_list_head, list) {
345 struct irq_desc *desc = irq_to_desc(info->irq);
c9e265e0 346 cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
0b8f1efa 347 }
e46cdb66
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348#endif
349
1c6969ec 350 for_each_possible_cpu(i)
cb60d114 351 memset(per_cpu(cpu_evtchn_mask, i),
84ca7a8e 352 (i == 0) ? ~0 : 0, NR_EVENT_CHANNELS/8);
e46cdb66
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353}
354
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355static inline void clear_evtchn(int port)
356{
357 struct shared_info *s = HYPERVISOR_shared_info;
c81611c4 358 sync_clear_bit(port, BM(&s->evtchn_pending[0]));
e46cdb66
JF
359}
360
361static inline void set_evtchn(int port)
362{
363 struct shared_info *s = HYPERVISOR_shared_info;
c81611c4 364 sync_set_bit(port, BM(&s->evtchn_pending[0]));
e46cdb66
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365}
366
168d2f46
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367static inline int test_evtchn(int port)
368{
369 struct shared_info *s = HYPERVISOR_shared_info;
c81611c4 370 return sync_test_bit(port, BM(&s->evtchn_pending[0]));
168d2f46
JF
371}
372
e46cdb66
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373
374/**
375 * notify_remote_via_irq - send event to remote end of event channel via irq
376 * @irq: irq of event channel to send event to
377 *
378 * Unlike notify_remote_via_evtchn(), this is safe to use across
379 * save/restore. Notifications on a broken connection are silently
380 * dropped.
381 */
382void notify_remote_via_irq(int irq)
383{
384 int evtchn = evtchn_from_irq(irq);
385
386 if (VALID_EVTCHN(evtchn))
387 notify_remote_via_evtchn(evtchn);
388}
389EXPORT_SYMBOL_GPL(notify_remote_via_irq);
390
391static void mask_evtchn(int port)
392{
393 struct shared_info *s = HYPERVISOR_shared_info;
c81611c4 394 sync_set_bit(port, BM(&s->evtchn_mask[0]));
e46cdb66
JF
395}
396
397static void unmask_evtchn(int port)
398{
399 struct shared_info *s = HYPERVISOR_shared_info;
400 unsigned int cpu = get_cpu();
b5e57923 401 int do_hypercall = 0, evtchn_pending = 0;
e46cdb66
JF
402
403 BUG_ON(!irqs_disabled());
404
b5e57923
SS
405 if (unlikely((cpu != cpu_from_evtchn(port))))
406 do_hypercall = 1;
c26377e6
DV
407 else {
408 /*
409 * Need to clear the mask before checking pending to
410 * avoid a race with an event becoming pending.
411 *
412 * EVTCHNOP_unmask will only trigger an upcall if the
413 * mask bit was set, so if a hypercall is needed
414 * remask the event.
415 */
416 sync_clear_bit(port, BM(&s->evtchn_mask[0]));
c81611c4 417 evtchn_pending = sync_test_bit(port, BM(&s->evtchn_pending[0]));
b5e57923 418
c26377e6
DV
419 if (unlikely(evtchn_pending && xen_hvm_domain())) {
420 sync_set_bit(port, BM(&s->evtchn_mask[0]));
421 do_hypercall = 1;
422 }
423 }
b5e57923
SS
424
425 /* Slow path (hypercall) if this is a non-local port or if this is
426 * an hvm domain and an event is pending (hvm domains don't have
427 * their own implementation of irq_enable). */
428 if (do_hypercall) {
e46cdb66
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429 struct evtchn_unmask unmask = { .port = port };
430 (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
431 } else {
780f36d8 432 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
e46cdb66 433
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434 /*
435 * The following is basically the equivalent of
436 * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
437 * the interrupt edge' if the channel is masked.
438 */
b5e57923 439 if (evtchn_pending &&
c81611c4
IC
440 !sync_test_and_set_bit(port / BITS_PER_EVTCHN_WORD,
441 BM(&vcpu_info->evtchn_pending_sel)))
e46cdb66
JF
442 vcpu_info->evtchn_upcall_pending = 1;
443 }
444
445 put_cpu();
446}
447
6cb6537d
IC
448static void xen_irq_init(unsigned irq)
449{
450 struct irq_info *info;
b5328cd1 451#ifdef CONFIG_SMP
6cb6537d
IC
452 struct irq_desc *desc = irq_to_desc(irq);
453
454 /* By default all event channels notify CPU#0. */
455 cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
44626e4a 456#endif
6cb6537d 457
ca62ce8c
IC
458 info = kzalloc(sizeof(*info), GFP_KERNEL);
459 if (info == NULL)
460 panic("Unable to allocate metadata for IRQ%d\n", irq);
6cb6537d
IC
461
462 info->type = IRQT_UNBOUND;
420eb554 463 info->refcnt = -1;
6cb6537d 464
c442b806 465 irq_set_handler_data(irq, info);
ca62ce8c 466
6cb6537d
IC
467 list_add_tail(&info->list, &xen_irq_list_head);
468}
469
7bee9768 470static int __must_check xen_allocate_irq_dynamic(void)
0794bfc7 471{
89911501
IC
472 int first = 0;
473 int irq;
0794bfc7
KRW
474
475#ifdef CONFIG_X86_IO_APIC
89911501
IC
476 /*
477 * For an HVM guest or domain 0 which see "real" (emulated or
25985edc 478 * actual respectively) GSIs we allocate dynamic IRQs
89911501
IC
479 * e.g. those corresponding to event channels or MSIs
480 * etc. from the range above those "real" GSIs to avoid
481 * collisions.
482 */
483 if (xen_initial_domain() || xen_hvm_domain())
484 first = get_nr_irqs_gsi();
0794bfc7
KRW
485#endif
486
89911501 487 irq = irq_alloc_desc_from(first, -1);
3a69e916 488
e6599225
KRW
489 if (irq >= 0)
490 xen_irq_init(irq);
ced40d0f 491
e46cdb66 492 return irq;
d46a78b0
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493}
494
7bee9768 495static int __must_check xen_allocate_irq_gsi(unsigned gsi)
c9df1ce5
IC
496{
497 int irq;
498
89911501
IC
499 /*
500 * A PV guest has no concept of a GSI (since it has no ACPI
501 * nor access to/knowledge of the physical APICs). Therefore
502 * all IRQs are dynamically allocated from the entire IRQ
503 * space.
504 */
505 if (xen_pv_domain() && !xen_initial_domain())
c9df1ce5
IC
506 return xen_allocate_irq_dynamic();
507
508 /* Legacy IRQ descriptors are already allocated by the arch. */
509 if (gsi < NR_IRQS_LEGACY)
6cb6537d
IC
510 irq = gsi;
511 else
512 irq = irq_alloc_desc_at(gsi, -1);
c9df1ce5 513
6cb6537d 514 xen_irq_init(irq);
c9df1ce5
IC
515
516 return irq;
517}
518
519static void xen_free_irq(unsigned irq)
520{
c442b806 521 struct irq_info *info = irq_get_handler_data(irq);
6cb6537d 522
94032c50
KRW
523 if (WARN_ON(!info))
524 return;
525
6cb6537d 526 list_del(&info->list);
9158c358 527
c442b806 528 irq_set_handler_data(irq, NULL);
ca62ce8c 529
420eb554
DDG
530 WARN_ON(info->refcnt > 0);
531
ca62ce8c
IC
532 kfree(info);
533
72146104
IC
534 /* Legacy IRQ descriptors are managed by the arch. */
535 if (irq < NR_IRQS_LEGACY)
536 return;
537
c9df1ce5
IC
538 irq_free_desc(irq);
539}
540
d46a78b0
JF
541static void pirq_query_unmask(int irq)
542{
543 struct physdev_irq_status_query irq_status;
544 struct irq_info *info = info_for_irq(irq);
545
546 BUG_ON(info->type != IRQT_PIRQ);
547
7a043f11 548 irq_status.irq = pirq_from_irq(irq);
d46a78b0
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549 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
550 irq_status.flags = 0;
551
552 info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
553 if (irq_status.flags & XENIRQSTAT_needs_eoi)
554 info->u.pirq.flags |= PIRQ_NEEDS_EOI;
555}
556
557static bool probing_irq(int irq)
558{
559 struct irq_desc *desc = irq_to_desc(irq);
560
561 return desc && desc->action == NULL;
562}
563
7e186bdd
SS
564static void eoi_pirq(struct irq_data *data)
565{
566 int evtchn = evtchn_from_irq(data->irq);
567 struct physdev_eoi eoi = { .irq = pirq_from_irq(data->irq) };
568 int rc = 0;
569
570 irq_move_irq(data);
571
572 if (VALID_EVTCHN(evtchn))
573 clear_evtchn(evtchn);
574
575 if (pirq_needs_eoi(data->irq)) {
576 rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
577 WARN_ON(rc);
578 }
579}
580
581static void mask_ack_pirq(struct irq_data *data)
582{
583 disable_dynirq(data);
584 eoi_pirq(data);
585}
586
c9e265e0 587static unsigned int __startup_pirq(unsigned int irq)
d46a78b0
JF
588{
589 struct evtchn_bind_pirq bind_pirq;
590 struct irq_info *info = info_for_irq(irq);
591 int evtchn = evtchn_from_irq(irq);
15ebbb82 592 int rc;
d46a78b0
JF
593
594 BUG_ON(info->type != IRQT_PIRQ);
595
596 if (VALID_EVTCHN(evtchn))
597 goto out;
598
7a043f11 599 bind_pirq.pirq = pirq_from_irq(irq);
d46a78b0 600 /* NB. We are happy to share unless we are probing. */
15ebbb82
KRW
601 bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
602 BIND_PIRQ__WILL_SHARE : 0;
603 rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
604 if (rc != 0) {
d46a78b0 605 if (!probing_irq(irq))
283c0972 606 pr_info("Failed to obtain physical IRQ %d\n", irq);
d46a78b0
JF
607 return 0;
608 }
609 evtchn = bind_pirq.port;
610
611 pirq_query_unmask(irq);
612
613 evtchn_to_irq[evtchn] = irq;
614 bind_evtchn_to_cpu(evtchn, 0);
615 info->evtchn = evtchn;
616
617out:
618 unmask_evtchn(evtchn);
7e186bdd 619 eoi_pirq(irq_get_irq_data(irq));
d46a78b0
JF
620
621 return 0;
622}
623
c9e265e0
TG
624static unsigned int startup_pirq(struct irq_data *data)
625{
626 return __startup_pirq(data->irq);
627}
628
629static void shutdown_pirq(struct irq_data *data)
d46a78b0
JF
630{
631 struct evtchn_close close;
c9e265e0 632 unsigned int irq = data->irq;
d46a78b0
JF
633 struct irq_info *info = info_for_irq(irq);
634 int evtchn = evtchn_from_irq(irq);
635
636 BUG_ON(info->type != IRQT_PIRQ);
637
638 if (!VALID_EVTCHN(evtchn))
639 return;
640
641 mask_evtchn(evtchn);
642
643 close.port = evtchn;
644 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
645 BUG();
646
647 bind_evtchn_to_cpu(evtchn, 0);
648 evtchn_to_irq[evtchn] = -1;
649 info->evtchn = 0;
650}
651
c9e265e0 652static void enable_pirq(struct irq_data *data)
d46a78b0 653{
c9e265e0 654 startup_pirq(data);
d46a78b0
JF
655}
656
c9e265e0 657static void disable_pirq(struct irq_data *data)
d46a78b0 658{
7e186bdd 659 disable_dynirq(data);
d46a78b0
JF
660}
661
68c2c39a 662int xen_irq_from_gsi(unsigned gsi)
d46a78b0 663{
6cb6537d 664 struct irq_info *info;
d46a78b0 665
6cb6537d
IC
666 list_for_each_entry(info, &xen_irq_list_head, list) {
667 if (info->type != IRQT_PIRQ)
d46a78b0
JF
668 continue;
669
6cb6537d
IC
670 if (info->u.pirq.gsi == gsi)
671 return info->irq;
d46a78b0
JF
672 }
673
674 return -1;
675}
68c2c39a 676EXPORT_SYMBOL_GPL(xen_irq_from_gsi);
d46a78b0 677
653378ac
IC
678/*
679 * Do not make any assumptions regarding the relationship between the
680 * IRQ number returned here and the Xen pirq argument.
7a043f11
SS
681 *
682 * Note: We don't assign an event channel until the irq actually started
683 * up. Return an existing irq if we've already got one for the gsi.
e5ac0bda
SS
684 *
685 * Shareable implies level triggered, not shareable implies edge
686 * triggered here.
d46a78b0 687 */
f4d0635b
IC
688int xen_bind_pirq_gsi_to_irq(unsigned gsi,
689 unsigned pirq, int shareable, char *name)
d46a78b0 690{
a0e18116 691 int irq = -1;
d46a78b0
JF
692 struct physdev_irq irq_op;
693
77365948 694 mutex_lock(&irq_mapping_update_lock);
d46a78b0 695
68c2c39a 696 irq = xen_irq_from_gsi(gsi);
d46a78b0 697 if (irq != -1) {
283c0972
JP
698 pr_info("%s: returning irq %d for gsi %u\n",
699 __func__, irq, gsi);
420eb554 700 goto out;
d46a78b0
JF
701 }
702
c9df1ce5 703 irq = xen_allocate_irq_gsi(gsi);
7bee9768
IC
704 if (irq < 0)
705 goto out;
d46a78b0 706
d46a78b0 707 irq_op.irq = irq;
b5401a96
AN
708 irq_op.vector = 0;
709
710 /* Only the privileged domain can do this. For non-priv, the pcifront
711 * driver provides a PCI bus that does the call to do exactly
712 * this in the priv domain. */
713 if (xen_initial_domain() &&
714 HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
c9df1ce5 715 xen_free_irq(irq);
d46a78b0
JF
716 irq = -ENOSPC;
717 goto out;
718 }
719
dec02dea 720 xen_irq_info_pirq_init(irq, 0, pirq, gsi, DOMID_SELF,
9158c358 721 shareable ? PIRQ_SHAREABLE : 0);
d46a78b0 722
7e186bdd
SS
723 pirq_query_unmask(irq);
724 /* We try to use the handler with the appropriate semantic for the
e5ac0bda
SS
725 * type of interrupt: if the interrupt is an edge triggered
726 * interrupt we use handle_edge_irq.
7e186bdd 727 *
e5ac0bda
SS
728 * On the other hand if the interrupt is level triggered we use
729 * handle_fasteoi_irq like the native code does for this kind of
7e186bdd 730 * interrupts.
e5ac0bda 731 *
7e186bdd
SS
732 * Depending on the Xen version, pirq_needs_eoi might return true
733 * not only for level triggered interrupts but for edge triggered
734 * interrupts too. In any case Xen always honors the eoi mechanism,
735 * not injecting any more pirqs of the same kind if the first one
736 * hasn't received an eoi yet. Therefore using the fasteoi handler
737 * is the right choice either way.
738 */
e5ac0bda 739 if (shareable)
7e186bdd
SS
740 irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
741 handle_fasteoi_irq, name);
742 else
743 irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
744 handle_edge_irq, name);
745
d46a78b0 746out:
77365948 747 mutex_unlock(&irq_mapping_update_lock);
d46a78b0
JF
748
749 return irq;
750}
751
f731e3ef 752#ifdef CONFIG_PCI_MSI
bf480d95 753int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc)
cbf6aa89 754{
5cad61a6 755 int rc;
cbf6aa89 756 struct physdev_get_free_pirq op_get_free_pirq;
cbf6aa89 757
bf480d95 758 op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI;
cbf6aa89 759 rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
cbf6aa89 760
5cad61a6
IC
761 WARN_ONCE(rc == -ENOSYS,
762 "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n");
763
764 return rc ? -1 : op_get_free_pirq.pirq;
cbf6aa89
IC
765}
766
bf480d95 767int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc,
dec02dea 768 int pirq, const char *name, domid_t domid)
809f9267 769{
bf480d95 770 int irq, ret;
4b41df7f 771
77365948 772 mutex_lock(&irq_mapping_update_lock);
809f9267 773
4b41df7f 774 irq = xen_allocate_irq_dynamic();
e6599225 775 if (irq < 0)
bb5d079a 776 goto out;
809f9267 777
7e186bdd
SS
778 irq_set_chip_and_handler_name(irq, &xen_pirq_chip, handle_edge_irq,
779 name);
809f9267 780
dec02dea 781 xen_irq_info_pirq_init(irq, 0, pirq, 0, domid, 0);
5f6fb454 782 ret = irq_set_msi_desc(irq, msidesc);
bf480d95
IC
783 if (ret < 0)
784 goto error_irq;
809f9267 785out:
77365948 786 mutex_unlock(&irq_mapping_update_lock);
4b41df7f 787 return irq;
bf480d95 788error_irq:
77365948 789 mutex_unlock(&irq_mapping_update_lock);
bf480d95 790 xen_free_irq(irq);
e6599225 791 return ret;
809f9267 792}
f731e3ef
QH
793#endif
794
b5401a96
AN
795int xen_destroy_irq(int irq)
796{
797 struct irq_desc *desc;
38aa66fc
JF
798 struct physdev_unmap_pirq unmap_irq;
799 struct irq_info *info = info_for_irq(irq);
b5401a96
AN
800 int rc = -ENOENT;
801
77365948 802 mutex_lock(&irq_mapping_update_lock);
b5401a96
AN
803
804 desc = irq_to_desc(irq);
805 if (!desc)
806 goto out;
807
38aa66fc 808 if (xen_initial_domain()) {
12334715 809 unmap_irq.pirq = info->u.pirq.pirq;
beafbdc1 810 unmap_irq.domid = info->u.pirq.domid;
38aa66fc 811 rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
1eff1ad0
KRW
812 /* If another domain quits without making the pci_disable_msix
813 * call, the Xen hypervisor takes care of freeing the PIRQs
814 * (free_domain_pirqs).
815 */
816 if ((rc == -ESRCH && info->u.pirq.domid != DOMID_SELF))
283c0972 817 pr_info("domain %d does not have %d anymore\n",
1eff1ad0
KRW
818 info->u.pirq.domid, info->u.pirq.pirq);
819 else if (rc) {
283c0972 820 pr_warn("unmap irq failed %d\n", rc);
38aa66fc
JF
821 goto out;
822 }
823 }
b5401a96 824
c9df1ce5 825 xen_free_irq(irq);
b5401a96
AN
826
827out:
77365948 828 mutex_unlock(&irq_mapping_update_lock);
b5401a96
AN
829 return rc;
830}
831
af42b8d1 832int xen_irq_from_pirq(unsigned pirq)
d46a78b0 833{
69c358ce 834 int irq;
d46a78b0 835
69c358ce 836 struct irq_info *info;
e46cdb66 837
77365948 838 mutex_lock(&irq_mapping_update_lock);
69c358ce
IC
839
840 list_for_each_entry(info, &xen_irq_list_head, list) {
9bb9efe4 841 if (info->type != IRQT_PIRQ)
69c358ce
IC
842 continue;
843 irq = info->irq;
844 if (info->u.pirq.pirq == pirq)
845 goto out;
846 }
847 irq = -1;
848out:
77365948 849 mutex_unlock(&irq_mapping_update_lock);
69c358ce
IC
850
851 return irq;
af42b8d1
SS
852}
853
e6197acc
KRW
854
855int xen_pirq_from_irq(unsigned irq)
856{
857 return pirq_from_irq(irq);
858}
859EXPORT_SYMBOL_GPL(xen_pirq_from_irq);
b536b4b9 860int bind_evtchn_to_irq(unsigned int evtchn)
e46cdb66
JF
861{
862 int irq;
863
77365948 864 mutex_lock(&irq_mapping_update_lock);
e46cdb66
JF
865
866 irq = evtchn_to_irq[evtchn];
867
868 if (irq == -1) {
c9df1ce5 869 irq = xen_allocate_irq_dynamic();
68ba45ff 870 if (irq < 0)
7bee9768 871 goto out;
e46cdb66 872
c442b806 873 irq_set_chip_and_handler_name(irq, &xen_dynamic_chip,
7e186bdd 874 handle_edge_irq, "event");
e46cdb66 875
9158c358 876 xen_irq_info_evtchn_init(irq, evtchn);
5e152e6c
KRW
877 } else {
878 struct irq_info *info = info_for_irq(irq);
879 WARN_ON(info == NULL || info->type != IRQT_EVTCHN);
e46cdb66
JF
880 }
881
7bee9768 882out:
77365948 883 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
884
885 return irq;
886}
b536b4b9 887EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
e46cdb66 888
f87e4cac
JF
889static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
890{
891 struct evtchn_bind_ipi bind_ipi;
892 int evtchn, irq;
893
77365948 894 mutex_lock(&irq_mapping_update_lock);
f87e4cac
JF
895
896 irq = per_cpu(ipi_to_irq, cpu)[ipi];
90af9514 897
f87e4cac 898 if (irq == -1) {
c9df1ce5 899 irq = xen_allocate_irq_dynamic();
f87e4cac
JF
900 if (irq < 0)
901 goto out;
902
c442b806 903 irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
aaca4964 904 handle_percpu_irq, "ipi");
f87e4cac
JF
905
906 bind_ipi.vcpu = cpu;
907 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
908 &bind_ipi) != 0)
909 BUG();
910 evtchn = bind_ipi.port;
911
3d4cfa37 912 xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
f87e4cac
JF
913
914 bind_evtchn_to_cpu(evtchn, cpu);
5e152e6c
KRW
915 } else {
916 struct irq_info *info = info_for_irq(irq);
917 WARN_ON(info == NULL || info->type != IRQT_IPI);
f87e4cac
JF
918 }
919
f87e4cac 920 out:
77365948 921 mutex_unlock(&irq_mapping_update_lock);
f87e4cac
JF
922 return irq;
923}
924
2e820f58
IC
925static int bind_interdomain_evtchn_to_irq(unsigned int remote_domain,
926 unsigned int remote_port)
927{
928 struct evtchn_bind_interdomain bind_interdomain;
929 int err;
930
931 bind_interdomain.remote_dom = remote_domain;
932 bind_interdomain.remote_port = remote_port;
933
934 err = HYPERVISOR_event_channel_op(EVTCHNOP_bind_interdomain,
935 &bind_interdomain);
936
937 return err ? : bind_evtchn_to_irq(bind_interdomain.local_port);
938}
939
62cc5fc7
OH
940static int find_virq(unsigned int virq, unsigned int cpu)
941{
942 struct evtchn_status status;
943 int port, rc = -ENOENT;
944
945 memset(&status, 0, sizeof(status));
946 for (port = 0; port <= NR_EVENT_CHANNELS; port++) {
947 status.dom = DOMID_SELF;
948 status.port = port;
949 rc = HYPERVISOR_event_channel_op(EVTCHNOP_status, &status);
950 if (rc < 0)
951 continue;
952 if (status.status != EVTCHNSTAT_virq)
953 continue;
954 if (status.u.virq == virq && status.vcpu == cpu) {
955 rc = port;
956 break;
957 }
958 }
959 return rc;
960}
f87e4cac 961
4fe7d5a7 962int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
e46cdb66
JF
963{
964 struct evtchn_bind_virq bind_virq;
62cc5fc7 965 int evtchn, irq, ret;
e46cdb66 966
77365948 967 mutex_lock(&irq_mapping_update_lock);
e46cdb66
JF
968
969 irq = per_cpu(virq_to_irq, cpu)[virq];
970
971 if (irq == -1) {
c9df1ce5 972 irq = xen_allocate_irq_dynamic();
68ba45ff 973 if (irq < 0)
7bee9768 974 goto out;
a52521f1 975
c442b806 976 irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
a52521f1
JF
977 handle_percpu_irq, "virq");
978
e46cdb66
JF
979 bind_virq.virq = virq;
980 bind_virq.vcpu = cpu;
62cc5fc7
OH
981 ret = HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
982 &bind_virq);
983 if (ret == 0)
984 evtchn = bind_virq.port;
985 else {
986 if (ret == -EEXIST)
987 ret = find_virq(virq, cpu);
988 BUG_ON(ret < 0);
989 evtchn = ret;
990 }
e46cdb66 991
3d4cfa37 992 xen_irq_info_virq_init(cpu, irq, evtchn, virq);
e46cdb66
JF
993
994 bind_evtchn_to_cpu(evtchn, cpu);
5e152e6c
KRW
995 } else {
996 struct irq_info *info = info_for_irq(irq);
997 WARN_ON(info == NULL || info->type != IRQT_VIRQ);
e46cdb66
JF
998 }
999
7bee9768 1000out:
77365948 1001 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
1002
1003 return irq;
1004}
1005
1006static void unbind_from_irq(unsigned int irq)
1007{
1008 struct evtchn_close close;
1009 int evtchn = evtchn_from_irq(irq);
420eb554 1010 struct irq_info *info = irq_get_handler_data(irq);
e46cdb66 1011
94032c50
KRW
1012 if (WARN_ON(!info))
1013 return;
1014
77365948 1015 mutex_lock(&irq_mapping_update_lock);
e46cdb66 1016
420eb554
DDG
1017 if (info->refcnt > 0) {
1018 info->refcnt--;
1019 if (info->refcnt != 0)
1020 goto done;
1021 }
1022
d77bbd4d 1023 if (VALID_EVTCHN(evtchn)) {
e46cdb66
JF
1024 close.port = evtchn;
1025 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
1026 BUG();
1027
1028 switch (type_from_irq(irq)) {
1029 case IRQT_VIRQ:
1030 per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 1031 [virq_from_irq(irq)] = -1;
e46cdb66 1032 break;
d68d82af
AN
1033 case IRQT_IPI:
1034 per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 1035 [ipi_from_irq(irq)] = -1;
d68d82af 1036 break;
e46cdb66
JF
1037 default:
1038 break;
1039 }
1040
1041 /* Closed ports are implicitly re-bound to VCPU0. */
1042 bind_evtchn_to_cpu(evtchn, 0);
1043
1044 evtchn_to_irq[evtchn] = -1;
fed5ea87
IC
1045 }
1046
ca62ce8c 1047 BUG_ON(info_for_irq(irq)->type == IRQT_UNBOUND);
e46cdb66 1048
9158c358 1049 xen_free_irq(irq);
e46cdb66 1050
420eb554 1051 done:
77365948 1052 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
1053}
1054
1055int bind_evtchn_to_irqhandler(unsigned int evtchn,
7c239975 1056 irq_handler_t handler,
e46cdb66
JF
1057 unsigned long irqflags,
1058 const char *devname, void *dev_id)
1059{
361ae8cb 1060 int irq, retval;
e46cdb66
JF
1061
1062 irq = bind_evtchn_to_irq(evtchn);
7bee9768
IC
1063 if (irq < 0)
1064 return irq;
e46cdb66
JF
1065 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1066 if (retval != 0) {
1067 unbind_from_irq(irq);
1068 return retval;
1069 }
1070
1071 return irq;
1072}
1073EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
1074
2e820f58
IC
1075int bind_interdomain_evtchn_to_irqhandler(unsigned int remote_domain,
1076 unsigned int remote_port,
1077 irq_handler_t handler,
1078 unsigned long irqflags,
1079 const char *devname,
1080 void *dev_id)
1081{
1082 int irq, retval;
1083
1084 irq = bind_interdomain_evtchn_to_irq(remote_domain, remote_port);
1085 if (irq < 0)
1086 return irq;
1087
1088 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1089 if (retval != 0) {
1090 unbind_from_irq(irq);
1091 return retval;
1092 }
1093
1094 return irq;
1095}
1096EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irqhandler);
1097
e46cdb66 1098int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
7c239975 1099 irq_handler_t handler,
e46cdb66
JF
1100 unsigned long irqflags, const char *devname, void *dev_id)
1101{
361ae8cb 1102 int irq, retval;
e46cdb66
JF
1103
1104 irq = bind_virq_to_irq(virq, cpu);
7bee9768
IC
1105 if (irq < 0)
1106 return irq;
e46cdb66
JF
1107 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1108 if (retval != 0) {
1109 unbind_from_irq(irq);
1110 return retval;
1111 }
1112
1113 return irq;
1114}
1115EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
1116
f87e4cac
JF
1117int bind_ipi_to_irqhandler(enum ipi_vector ipi,
1118 unsigned int cpu,
1119 irq_handler_t handler,
1120 unsigned long irqflags,
1121 const char *devname,
1122 void *dev_id)
1123{
1124 int irq, retval;
1125
1126 irq = bind_ipi_to_irq(ipi, cpu);
1127 if (irq < 0)
1128 return irq;
1129
9bab0b7f 1130 irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME | IRQF_EARLY_RESUME;
f87e4cac
JF
1131 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1132 if (retval != 0) {
1133 unbind_from_irq(irq);
1134 return retval;
1135 }
1136
1137 return irq;
1138}
1139
e46cdb66
JF
1140void unbind_from_irqhandler(unsigned int irq, void *dev_id)
1141{
94032c50
KRW
1142 struct irq_info *info = irq_get_handler_data(irq);
1143
1144 if (WARN_ON(!info))
1145 return;
e46cdb66
JF
1146 free_irq(irq, dev_id);
1147 unbind_from_irq(irq);
1148}
1149EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
1150
420eb554
DDG
1151int evtchn_make_refcounted(unsigned int evtchn)
1152{
1153 int irq = evtchn_to_irq[evtchn];
1154 struct irq_info *info;
1155
1156 if (irq == -1)
1157 return -ENOENT;
1158
1159 info = irq_get_handler_data(irq);
1160
1161 if (!info)
1162 return -ENOENT;
1163
1164 WARN_ON(info->refcnt != -1);
1165
1166 info->refcnt = 1;
1167
1168 return 0;
1169}
1170EXPORT_SYMBOL_GPL(evtchn_make_refcounted);
1171
1172int evtchn_get(unsigned int evtchn)
1173{
1174 int irq;
1175 struct irq_info *info;
1176 int err = -ENOENT;
1177
c3b3f16d
DDG
1178 if (evtchn >= NR_EVENT_CHANNELS)
1179 return -EINVAL;
1180
420eb554
DDG
1181 mutex_lock(&irq_mapping_update_lock);
1182
1183 irq = evtchn_to_irq[evtchn];
1184 if (irq == -1)
1185 goto done;
1186
1187 info = irq_get_handler_data(irq);
1188
1189 if (!info)
1190 goto done;
1191
1192 err = -EINVAL;
1193 if (info->refcnt <= 0)
1194 goto done;
1195
1196 info->refcnt++;
1197 err = 0;
1198 done:
1199 mutex_unlock(&irq_mapping_update_lock);
1200
1201 return err;
1202}
1203EXPORT_SYMBOL_GPL(evtchn_get);
1204
1205void evtchn_put(unsigned int evtchn)
1206{
1207 int irq = evtchn_to_irq[evtchn];
1208 if (WARN_ON(irq == -1))
1209 return;
1210 unbind_from_irq(irq);
1211}
1212EXPORT_SYMBOL_GPL(evtchn_put);
1213
f87e4cac
JF
1214void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
1215{
6efa20e4
KRW
1216 int irq;
1217
072b2064 1218#ifdef CONFIG_X86
6efa20e4
KRW
1219 if (unlikely(vector == XEN_NMI_VECTOR)) {
1220 int rc = HYPERVISOR_vcpu_op(VCPUOP_send_nmi, cpu, NULL);
1221 if (rc < 0)
1222 printk(KERN_WARNING "Sending nmi to CPU%d failed (rc:%d)\n", cpu, rc);
1223 return;
1224 }
072b2064 1225#endif
6efa20e4 1226 irq = per_cpu(ipi_to_irq, cpu)[vector];
f87e4cac
JF
1227 BUG_ON(irq < 0);
1228 notify_remote_via_irq(irq);
1229}
1230
ee523ca1
JF
1231irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
1232{
1233 struct shared_info *sh = HYPERVISOR_shared_info;
1234 int cpu = smp_processor_id();
c81611c4 1235 xen_ulong_t *cpu_evtchn = per_cpu(cpu_evtchn_mask, cpu);
ee523ca1
JF
1236 int i;
1237 unsigned long flags;
1238 static DEFINE_SPINLOCK(debug_lock);
cb52e6d9 1239 struct vcpu_info *v;
ee523ca1
JF
1240
1241 spin_lock_irqsave(&debug_lock, flags);
1242
cb52e6d9 1243 printk("\nvcpu %d\n ", cpu);
ee523ca1
JF
1244
1245 for_each_online_cpu(i) {
cb52e6d9
IC
1246 int pending;
1247 v = per_cpu(xen_vcpu, i);
1248 pending = (get_irq_regs() && i == cpu)
1249 ? xen_irqs_disabled(get_irq_regs())
1250 : v->evtchn_upcall_mask;
c81611c4 1251 printk("%d: masked=%d pending=%d event_sel %0*"PRI_xen_ulong"\n ", i,
cb52e6d9
IC
1252 pending, v->evtchn_upcall_pending,
1253 (int)(sizeof(v->evtchn_pending_sel)*2),
1254 v->evtchn_pending_sel);
1255 }
1256 v = per_cpu(xen_vcpu, cpu);
1257
1258 printk("\npending:\n ");
1259 for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
c81611c4
IC
1260 printk("%0*"PRI_xen_ulong"%s",
1261 (int)sizeof(sh->evtchn_pending[0])*2,
cb52e6d9
IC
1262 sh->evtchn_pending[i],
1263 i % 8 == 0 ? "\n " : " ");
1264 printk("\nglobal mask:\n ");
1265 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
c81611c4 1266 printk("%0*"PRI_xen_ulong"%s",
cb52e6d9
IC
1267 (int)(sizeof(sh->evtchn_mask[0])*2),
1268 sh->evtchn_mask[i],
1269 i % 8 == 0 ? "\n " : " ");
1270
1271 printk("\nglobally unmasked:\n ");
1272 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
c81611c4
IC
1273 printk("%0*"PRI_xen_ulong"%s",
1274 (int)(sizeof(sh->evtchn_mask[0])*2),
cb52e6d9
IC
1275 sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
1276 i % 8 == 0 ? "\n " : " ");
1277
1278 printk("\nlocal cpu%d mask:\n ", cpu);
c81611c4
IC
1279 for (i = (NR_EVENT_CHANNELS/BITS_PER_EVTCHN_WORD)-1; i >= 0; i--)
1280 printk("%0*"PRI_xen_ulong"%s", (int)(sizeof(cpu_evtchn[0])*2),
cb52e6d9
IC
1281 cpu_evtchn[i],
1282 i % 8 == 0 ? "\n " : " ");
1283
1284 printk("\nlocally unmasked:\n ");
1285 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
c81611c4 1286 xen_ulong_t pending = sh->evtchn_pending[i]
cb52e6d9
IC
1287 & ~sh->evtchn_mask[i]
1288 & cpu_evtchn[i];
c81611c4
IC
1289 printk("%0*"PRI_xen_ulong"%s",
1290 (int)(sizeof(sh->evtchn_mask[0])*2),
cb52e6d9 1291 pending, i % 8 == 0 ? "\n " : " ");
ee523ca1 1292 }
ee523ca1
JF
1293
1294 printk("\npending list:\n");
cb52e6d9 1295 for (i = 0; i < NR_EVENT_CHANNELS; i++) {
c81611c4
IC
1296 if (sync_test_bit(i, BM(sh->evtchn_pending))) {
1297 int word_idx = i / BITS_PER_EVTCHN_WORD;
cb52e6d9 1298 printk(" %d: event %d -> irq %d%s%s%s\n",
ced40d0f 1299 cpu_from_evtchn(i), i,
cb52e6d9 1300 evtchn_to_irq[i],
c81611c4 1301 sync_test_bit(word_idx, BM(&v->evtchn_pending_sel))
cb52e6d9 1302 ? "" : " l2-clear",
c81611c4 1303 !sync_test_bit(i, BM(sh->evtchn_mask))
cb52e6d9 1304 ? "" : " globally-masked",
c81611c4 1305 sync_test_bit(i, BM(cpu_evtchn))
cb52e6d9 1306 ? "" : " locally-masked");
ee523ca1
JF
1307 }
1308 }
1309
1310 spin_unlock_irqrestore(&debug_lock, flags);
1311
1312 return IRQ_HANDLED;
1313}
1314
245b2e70 1315static DEFINE_PER_CPU(unsigned, xed_nesting_count);
ada6814c
KF
1316static DEFINE_PER_CPU(unsigned int, current_word_idx);
1317static DEFINE_PER_CPU(unsigned int, current_bit_idx);
245b2e70 1318
ab7f863e
SR
1319/*
1320 * Mask out the i least significant bits of w
1321 */
c81611c4 1322#define MASK_LSBS(w, i) (w & ((~((xen_ulong_t)0UL)) << i))
245b2e70 1323
e46cdb66
JF
1324/*
1325 * Search the CPUs pending events bitmasks. For each one found, map
1326 * the event number to an irq, and feed it into do_IRQ() for
1327 * handling.
1328 *
1329 * Xen uses a two-level bitmap to speed searching. The first level is
1330 * a bitset of words which contain pending event bits. The second
1331 * level is a bitset of pending events themselves.
1332 */
38e20b07 1333static void __xen_evtchn_do_upcall(void)
e46cdb66 1334{
24b51c2f 1335 int start_word_idx, start_bit_idx;
ab7f863e 1336 int word_idx, bit_idx;
bee980d9 1337 int i, irq;
e46cdb66
JF
1338 int cpu = get_cpu();
1339 struct shared_info *s = HYPERVISOR_shared_info;
780f36d8 1340 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
088c05a8 1341 unsigned count;
e46cdb66 1342
229664be 1343 do {
c81611c4 1344 xen_ulong_t pending_words;
bee980d9
KF
1345 xen_ulong_t pending_bits;
1346 struct irq_desc *desc;
e46cdb66 1347
229664be 1348 vcpu_info->evtchn_upcall_pending = 0;
e46cdb66 1349
b2e4ae69 1350 if (__this_cpu_inc_return(xed_nesting_count) - 1)
229664be 1351 goto out;
e46cdb66 1352
c81611c4
IC
1353 /*
1354 * Master flag must be cleared /before/ clearing
1355 * selector flag. xchg_xen_ulong must contain an
1356 * appropriate barrier.
1357 */
bee980d9
KF
1358 if ((irq = per_cpu(virq_to_irq, cpu)[VIRQ_TIMER]) != -1) {
1359 int evtchn = evtchn_from_irq(irq);
1360 word_idx = evtchn / BITS_PER_LONG;
1361 pending_bits = evtchn % BITS_PER_LONG;
1362 if (active_evtchns(cpu, s, word_idx) & (1ULL << pending_bits)) {
1363 desc = irq_to_desc(irq);
1364 if (desc)
1365 generic_handle_irq_desc(irq, desc);
1366 }
1367 }
1368
c81611c4 1369 pending_words = xchg_xen_ulong(&vcpu_info->evtchn_pending_sel, 0);
ab7f863e 1370
24b51c2f
KF
1371 start_word_idx = __this_cpu_read(current_word_idx);
1372 start_bit_idx = __this_cpu_read(current_bit_idx);
1373
1374 word_idx = start_word_idx;
ab7f863e 1375
24b51c2f 1376 for (i = 0; pending_words != 0; i++) {
c81611c4 1377 xen_ulong_t words;
229664be 1378
ab7f863e
SR
1379 words = MASK_LSBS(pending_words, word_idx);
1380
1381 /*
ada6814c 1382 * If we masked out all events, wrap to beginning.
ab7f863e
SR
1383 */
1384 if (words == 0) {
ada6814c
KF
1385 word_idx = 0;
1386 bit_idx = 0;
ab7f863e
SR
1387 continue;
1388 }
c81611c4 1389 word_idx = EVTCHN_FIRST_BIT(words);
229664be 1390
24b51c2f
KF
1391 pending_bits = active_evtchns(cpu, s, word_idx);
1392 bit_idx = 0; /* usually scan entire word from start */
3ef0296a
DV
1393 /*
1394 * We scan the starting word in two parts.
1395 *
1396 * 1st time: start in the middle, scanning the
1397 * upper bits.
1398 *
1399 * 2nd time: scan the whole word (not just the
1400 * parts skipped in the first pass) -- if an
1401 * event in the previously scanned bits is
1402 * pending again it would just be scanned on
1403 * the next loop anyway.
1404 */
24b51c2f 1405 if (word_idx == start_word_idx) {
24b51c2f 1406 if (i == 0)
24b51c2f 1407 bit_idx = start_bit_idx;
24b51c2f
KF
1408 }
1409
ab7f863e 1410 do {
c81611c4 1411 xen_ulong_t bits;
bee980d9 1412 int port;
229664be 1413
ab7f863e
SR
1414 bits = MASK_LSBS(pending_bits, bit_idx);
1415
1416 /* If we masked out all events, move on. */
ada6814c 1417 if (bits == 0)
ab7f863e 1418 break;
ab7f863e 1419
c81611c4 1420 bit_idx = EVTCHN_FIRST_BIT(bits);
ab7f863e
SR
1421
1422 /* Process port. */
c81611c4 1423 port = (word_idx * BITS_PER_EVTCHN_WORD) + bit_idx;
ab7f863e
SR
1424 irq = evtchn_to_irq[port];
1425
ca4dbc66
EB
1426 if (irq != -1) {
1427 desc = irq_to_desc(irq);
1428 if (desc)
1429 generic_handle_irq_desc(irq, desc);
1430 }
ab7f863e 1431
c81611c4 1432 bit_idx = (bit_idx + 1) % BITS_PER_EVTCHN_WORD;
ada6814c
KF
1433
1434 /* Next caller starts at last processed + 1 */
1435 __this_cpu_write(current_word_idx,
1436 bit_idx ? word_idx :
c81611c4 1437 (word_idx+1) % BITS_PER_EVTCHN_WORD);
ada6814c
KF
1438 __this_cpu_write(current_bit_idx, bit_idx);
1439 } while (bit_idx != 0);
ab7f863e 1440
24b51c2f
KF
1441 /* Scan start_l1i twice; all others once. */
1442 if ((word_idx != start_word_idx) || (i != 0))
ab7f863e 1443 pending_words &= ~(1UL << word_idx);
ada6814c 1444
c81611c4 1445 word_idx = (word_idx + 1) % BITS_PER_EVTCHN_WORD;
e46cdb66 1446 }
e46cdb66 1447
229664be
JF
1448 BUG_ON(!irqs_disabled());
1449
780f36d8
CL
1450 count = __this_cpu_read(xed_nesting_count);
1451 __this_cpu_write(xed_nesting_count, 0);
183d03cc 1452 } while (count != 1 || vcpu_info->evtchn_upcall_pending);
229664be
JF
1453
1454out:
38e20b07
SY
1455
1456 put_cpu();
1457}
1458
1459void xen_evtchn_do_upcall(struct pt_regs *regs)
1460{
1461 struct pt_regs *old_regs = set_irq_regs(regs);
1462
772aebce 1463 irq_enter();
0ec53ecf 1464#ifdef CONFIG_X86
38e20b07 1465 exit_idle();
0ec53ecf 1466#endif
38e20b07
SY
1467
1468 __xen_evtchn_do_upcall();
1469
3445a8fd
JF
1470 irq_exit();
1471 set_irq_regs(old_regs);
38e20b07 1472}
3445a8fd 1473
38e20b07
SY
1474void xen_hvm_evtchn_do_upcall(void)
1475{
1476 __xen_evtchn_do_upcall();
e46cdb66 1477}
183d03cc 1478EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
e46cdb66 1479
eb1e305f
JF
1480/* Rebind a new event channel to an existing irq. */
1481void rebind_evtchn_irq(int evtchn, int irq)
1482{
d77bbd4d
JF
1483 struct irq_info *info = info_for_irq(irq);
1484
94032c50
KRW
1485 if (WARN_ON(!info))
1486 return;
1487
eb1e305f
JF
1488 /* Make sure the irq is masked, since the new event channel
1489 will also be masked. */
1490 disable_irq(irq);
1491
77365948 1492 mutex_lock(&irq_mapping_update_lock);
eb1e305f
JF
1493
1494 /* After resume the irq<->evtchn mappings are all cleared out */
1495 BUG_ON(evtchn_to_irq[evtchn] != -1);
1496 /* Expect irq to have been bound before,
d77bbd4d
JF
1497 so there should be a proper type */
1498 BUG_ON(info->type == IRQT_UNBOUND);
eb1e305f 1499
9158c358 1500 xen_irq_info_evtchn_init(irq, evtchn);
eb1e305f 1501
77365948 1502 mutex_unlock(&irq_mapping_update_lock);
eb1e305f
JF
1503
1504 /* new event channels are always bound to cpu 0 */
0de26520 1505 irq_set_affinity(irq, cpumask_of(0));
eb1e305f
JF
1506
1507 /* Unmask the event channel. */
1508 enable_irq(irq);
1509}
1510
e46cdb66 1511/* Rebind an evtchn so that it gets delivered to a specific cpu */
d5dedd45 1512static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
e46cdb66 1513{
4704fe4f 1514 struct shared_info *s = HYPERVISOR_shared_info;
e46cdb66
JF
1515 struct evtchn_bind_vcpu bind_vcpu;
1516 int evtchn = evtchn_from_irq(irq);
4704fe4f 1517 int masked;
e46cdb66 1518
be49472f
IC
1519 if (!VALID_EVTCHN(evtchn))
1520 return -1;
1521
1522 /*
1523 * Events delivered via platform PCI interrupts are always
1524 * routed to vcpu 0 and hence cannot be rebound.
1525 */
1526 if (xen_hvm_domain() && !xen_have_vector_callback)
d5dedd45 1527 return -1;
e46cdb66
JF
1528
1529 /* Send future instances of this interrupt to other vcpu. */
1530 bind_vcpu.port = evtchn;
1531 bind_vcpu.vcpu = tcpu;
1532
4704fe4f
DV
1533 /*
1534 * Mask the event while changing the VCPU binding to prevent
1535 * it being delivered on an unexpected VCPU.
1536 */
1537 masked = sync_test_and_set_bit(evtchn, BM(s->evtchn_mask));
1538
e46cdb66
JF
1539 /*
1540 * If this fails, it usually just indicates that we're dealing with a
1541 * virq or IPI channel, which don't actually need to be rebound. Ignore
1542 * it, but don't do the xenlinux-level rebind in that case.
1543 */
1544 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
1545 bind_evtchn_to_cpu(evtchn, tcpu);
e46cdb66 1546
4704fe4f
DV
1547 if (!masked)
1548 unmask_evtchn(evtchn);
1549
d5dedd45
YL
1550 return 0;
1551}
e46cdb66 1552
c9e265e0
TG
1553static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest,
1554 bool force)
e46cdb66 1555{
0de26520 1556 unsigned tcpu = cpumask_first(dest);
d5dedd45 1557
c9e265e0 1558 return rebind_irq_to_cpu(data->irq, tcpu);
e46cdb66
JF
1559}
1560
642e0c88
IY
1561int resend_irq_on_evtchn(unsigned int irq)
1562{
1563 int masked, evtchn = evtchn_from_irq(irq);
1564 struct shared_info *s = HYPERVISOR_shared_info;
1565
1566 if (!VALID_EVTCHN(evtchn))
1567 return 1;
1568
c81611c4
IC
1569 masked = sync_test_and_set_bit(evtchn, BM(s->evtchn_mask));
1570 sync_set_bit(evtchn, BM(s->evtchn_pending));
642e0c88
IY
1571 if (!masked)
1572 unmask_evtchn(evtchn);
1573
1574 return 1;
1575}
1576
c9e265e0 1577static void enable_dynirq(struct irq_data *data)
e46cdb66 1578{
c9e265e0 1579 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1580
1581 if (VALID_EVTCHN(evtchn))
1582 unmask_evtchn(evtchn);
1583}
1584
c9e265e0 1585static void disable_dynirq(struct irq_data *data)
e46cdb66 1586{
c9e265e0 1587 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1588
1589 if (VALID_EVTCHN(evtchn))
1590 mask_evtchn(evtchn);
1591}
1592
c9e265e0 1593static void ack_dynirq(struct irq_data *data)
e46cdb66 1594{
c9e265e0 1595 int evtchn = evtchn_from_irq(data->irq);
e46cdb66 1596
7e186bdd 1597 irq_move_irq(data);
e46cdb66
JF
1598
1599 if (VALID_EVTCHN(evtchn))
7e186bdd
SS
1600 clear_evtchn(evtchn);
1601}
1602
1603static void mask_ack_dynirq(struct irq_data *data)
1604{
1605 disable_dynirq(data);
1606 ack_dynirq(data);
e46cdb66
JF
1607}
1608
c9e265e0 1609static int retrigger_dynirq(struct irq_data *data)
e46cdb66 1610{
c9e265e0 1611 int evtchn = evtchn_from_irq(data->irq);
ee8fa1c6 1612 struct shared_info *sh = HYPERVISOR_shared_info;
e46cdb66
JF
1613 int ret = 0;
1614
1615 if (VALID_EVTCHN(evtchn)) {
ee8fa1c6
JF
1616 int masked;
1617
c81611c4
IC
1618 masked = sync_test_and_set_bit(evtchn, BM(sh->evtchn_mask));
1619 sync_set_bit(evtchn, BM(sh->evtchn_pending));
ee8fa1c6
JF
1620 if (!masked)
1621 unmask_evtchn(evtchn);
e46cdb66
JF
1622 ret = 1;
1623 }
1624
1625 return ret;
1626}
1627
0a85226f 1628static void restore_pirqs(void)
9a069c33
SS
1629{
1630 int pirq, rc, irq, gsi;
1631 struct physdev_map_pirq map_irq;
69c358ce 1632 struct irq_info *info;
9a069c33 1633
69c358ce
IC
1634 list_for_each_entry(info, &xen_irq_list_head, list) {
1635 if (info->type != IRQT_PIRQ)
9a069c33
SS
1636 continue;
1637
69c358ce
IC
1638 pirq = info->u.pirq.pirq;
1639 gsi = info->u.pirq.gsi;
1640 irq = info->irq;
1641
9a069c33
SS
1642 /* save/restore of PT devices doesn't work, so at this point the
1643 * only devices present are GSI based emulated devices */
9a069c33
SS
1644 if (!gsi)
1645 continue;
1646
1647 map_irq.domid = DOMID_SELF;
1648 map_irq.type = MAP_PIRQ_TYPE_GSI;
1649 map_irq.index = gsi;
1650 map_irq.pirq = pirq;
1651
1652 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
1653 if (rc) {
283c0972
JP
1654 pr_warn("xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
1655 gsi, irq, pirq, rc);
9158c358 1656 xen_free_irq(irq);
9a069c33
SS
1657 continue;
1658 }
1659
1660 printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
1661
c9e265e0 1662 __startup_pirq(irq);
9a069c33
SS
1663 }
1664}
1665
0e91398f
JF
1666static void restore_cpu_virqs(unsigned int cpu)
1667{
1668 struct evtchn_bind_virq bind_virq;
1669 int virq, irq, evtchn;
1670
1671 for (virq = 0; virq < NR_VIRQS; virq++) {
1672 if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
1673 continue;
1674
ced40d0f 1675 BUG_ON(virq_from_irq(irq) != virq);
0e91398f
JF
1676
1677 /* Get a new binding from Xen. */
1678 bind_virq.virq = virq;
1679 bind_virq.vcpu = cpu;
1680 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
1681 &bind_virq) != 0)
1682 BUG();
1683 evtchn = bind_virq.port;
1684
1685 /* Record the new mapping. */
3d4cfa37 1686 xen_irq_info_virq_init(cpu, irq, evtchn, virq);
0e91398f 1687 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1688 }
1689}
1690
1691static void restore_cpu_ipis(unsigned int cpu)
1692{
1693 struct evtchn_bind_ipi bind_ipi;
1694 int ipi, irq, evtchn;
1695
1696 for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
1697 if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
1698 continue;
1699
ced40d0f 1700 BUG_ON(ipi_from_irq(irq) != ipi);
0e91398f
JF
1701
1702 /* Get a new binding from Xen. */
1703 bind_ipi.vcpu = cpu;
1704 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
1705 &bind_ipi) != 0)
1706 BUG();
1707 evtchn = bind_ipi.port;
1708
1709 /* Record the new mapping. */
3d4cfa37 1710 xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
0e91398f 1711 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1712 }
1713}
1714
2d9e1e2f
JF
1715/* Clear an irq's pending state, in preparation for polling on it */
1716void xen_clear_irq_pending(int irq)
1717{
1718 int evtchn = evtchn_from_irq(irq);
1719
1720 if (VALID_EVTCHN(evtchn))
1721 clear_evtchn(evtchn);
1722}
d9a8814f 1723EXPORT_SYMBOL(xen_clear_irq_pending);
168d2f46
JF
1724void xen_set_irq_pending(int irq)
1725{
1726 int evtchn = evtchn_from_irq(irq);
1727
1728 if (VALID_EVTCHN(evtchn))
1729 set_evtchn(evtchn);
1730}
1731
1732bool xen_test_irq_pending(int irq)
1733{
1734 int evtchn = evtchn_from_irq(irq);
1735 bool ret = false;
1736
1737 if (VALID_EVTCHN(evtchn))
1738 ret = test_evtchn(evtchn);
1739
1740 return ret;
1741}
1742
d9a8814f
KRW
1743/* Poll waiting for an irq to become pending with timeout. In the usual case,
1744 * the irq will be disabled so it won't deliver an interrupt. */
1745void xen_poll_irq_timeout(int irq, u64 timeout)
2d9e1e2f
JF
1746{
1747 evtchn_port_t evtchn = evtchn_from_irq(irq);
1748
1749 if (VALID_EVTCHN(evtchn)) {
1750 struct sched_poll poll;
1751
1752 poll.nr_ports = 1;
d9a8814f 1753 poll.timeout = timeout;
ff3c5362 1754 set_xen_guest_handle(poll.ports, &evtchn);
2d9e1e2f
JF
1755
1756 if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
1757 BUG();
1758 }
1759}
d9a8814f
KRW
1760EXPORT_SYMBOL(xen_poll_irq_timeout);
1761/* Poll waiting for an irq to become pending. In the usual case, the
1762 * irq will be disabled so it won't deliver an interrupt. */
1763void xen_poll_irq(int irq)
1764{
1765 xen_poll_irq_timeout(irq, 0 /* no timeout */);
1766}
2d9e1e2f 1767
c7c2c3a2
KRW
1768/* Check whether the IRQ line is shared with other guests. */
1769int xen_test_irq_shared(int irq)
1770{
1771 struct irq_info *info = info_for_irq(irq);
94032c50
KRW
1772 struct physdev_irq_status_query irq_status;
1773
1774 if (WARN_ON(!info))
1775 return -ENOENT;
1776
1777 irq_status.irq = info->u.pirq.pirq;
c7c2c3a2
KRW
1778
1779 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
1780 return 0;
1781 return !(irq_status.flags & XENIRQSTAT_shared);
1782}
1783EXPORT_SYMBOL_GPL(xen_test_irq_shared);
1784
0e91398f
JF
1785void xen_irq_resume(void)
1786{
6cb6537d
IC
1787 unsigned int cpu, evtchn;
1788 struct irq_info *info;
0e91398f
JF
1789
1790 init_evtchn_cpu_bindings();
1791
1792 /* New event-channel space is not 'live' yet. */
1793 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1794 mask_evtchn(evtchn);
1795
1796 /* No IRQ <-> event-channel mappings. */
6cb6537d
IC
1797 list_for_each_entry(info, &xen_irq_list_head, list)
1798 info->evtchn = 0; /* zap event-channel binding */
0e91398f
JF
1799
1800 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1801 evtchn_to_irq[evtchn] = -1;
1802
1803 for_each_possible_cpu(cpu) {
1804 restore_cpu_virqs(cpu);
1805 restore_cpu_ipis(cpu);
1806 }
6903591f 1807
0a85226f 1808 restore_pirqs();
0e91398f
JF
1809}
1810
e46cdb66 1811static struct irq_chip xen_dynamic_chip __read_mostly = {
c9e265e0 1812 .name = "xen-dyn",
54a353a0 1813
c9e265e0
TG
1814 .irq_disable = disable_dynirq,
1815 .irq_mask = disable_dynirq,
1816 .irq_unmask = enable_dynirq,
54a353a0 1817
7e186bdd
SS
1818 .irq_ack = ack_dynirq,
1819 .irq_mask_ack = mask_ack_dynirq,
1820
c9e265e0
TG
1821 .irq_set_affinity = set_affinity_irq,
1822 .irq_retrigger = retrigger_dynirq,
e46cdb66
JF
1823};
1824
d46a78b0 1825static struct irq_chip xen_pirq_chip __read_mostly = {
c9e265e0 1826 .name = "xen-pirq",
d46a78b0 1827
c9e265e0
TG
1828 .irq_startup = startup_pirq,
1829 .irq_shutdown = shutdown_pirq,
c9e265e0 1830 .irq_enable = enable_pirq,
c9e265e0 1831 .irq_disable = disable_pirq,
d46a78b0 1832
7e186bdd
SS
1833 .irq_mask = disable_dynirq,
1834 .irq_unmask = enable_dynirq,
1835
1836 .irq_ack = eoi_pirq,
1837 .irq_eoi = eoi_pirq,
1838 .irq_mask_ack = mask_ack_pirq,
d46a78b0 1839
c9e265e0 1840 .irq_set_affinity = set_affinity_irq,
d46a78b0 1841
c9e265e0 1842 .irq_retrigger = retrigger_dynirq,
d46a78b0
JF
1843};
1844
aaca4964 1845static struct irq_chip xen_percpu_chip __read_mostly = {
c9e265e0 1846 .name = "xen-percpu",
aaca4964 1847
c9e265e0
TG
1848 .irq_disable = disable_dynirq,
1849 .irq_mask = disable_dynirq,
1850 .irq_unmask = enable_dynirq,
aaca4964 1851
c9e265e0 1852 .irq_ack = ack_dynirq,
aaca4964
JF
1853};
1854
38e20b07
SY
1855int xen_set_callback_via(uint64_t via)
1856{
1857 struct xen_hvm_param a;
1858 a.domid = DOMID_SELF;
1859 a.index = HVM_PARAM_CALLBACK_IRQ;
1860 a.value = via;
1861 return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
1862}
1863EXPORT_SYMBOL_GPL(xen_set_callback_via);
1864
ca65f9fc 1865#ifdef CONFIG_XEN_PVHVM
38e20b07
SY
1866/* Vector callbacks are better than PCI interrupts to receive event
1867 * channel notifications because we can receive vector callbacks on any
1868 * vcpu and we don't need PCI support or APIC interactions. */
1869void xen_callback_vector(void)
1870{
1871 int rc;
1872 uint64_t callback_via;
1873 if (xen_have_vector_callback) {
bc2b0331 1874 callback_via = HVM_CALLBACK_VECTOR(HYPERVISOR_CALLBACK_VECTOR);
38e20b07
SY
1875 rc = xen_set_callback_via(callback_via);
1876 if (rc) {
283c0972 1877 pr_err("Request for Xen HVM callback vector failed\n");
38e20b07
SY
1878 xen_have_vector_callback = 0;
1879 return;
1880 }
283c0972 1881 pr_info("Xen HVM callback vector for event delivery is enabled\n");
38e20b07 1882 /* in the restore case the vector has already been allocated */
bc2b0331
S
1883 if (!test_bit(HYPERVISOR_CALLBACK_VECTOR, used_vectors))
1884 alloc_intr_gate(HYPERVISOR_CALLBACK_VECTOR,
1885 xen_hvm_callback_vector);
38e20b07
SY
1886 }
1887}
ca65f9fc
SS
1888#else
1889void xen_callback_vector(void) {}
1890#endif
38e20b07 1891
2e3d8860 1892void __init xen_init_IRQ(void)
e46cdb66 1893{
0ec53ecf 1894 int i;
c7a3589e 1895
b21ddbf5
JF
1896 evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
1897 GFP_KERNEL);
9d093e29 1898 BUG_ON(!evtchn_to_irq);
b21ddbf5
JF
1899 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1900 evtchn_to_irq[i] = -1;
e46cdb66
JF
1901
1902 init_evtchn_cpu_bindings();
1903
1904 /* No event channels are 'live' right now. */
1905 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1906 mask_evtchn(i);
1907
9846ff10
SS
1908 pirq_needs_eoi = pirq_needs_eoi_flag;
1909
0ec53ecf 1910#ifdef CONFIG_X86
38e20b07
SY
1911 if (xen_hvm_domain()) {
1912 xen_callback_vector();
1913 native_init_IRQ();
3942b740
SS
1914 /* pci_xen_hvm_init must be called after native_init_IRQ so that
1915 * __acpi_register_gsi can point at the right function */
1916 pci_xen_hvm_init();
38e20b07 1917 } else {
0ec53ecf 1918 int rc;
9846ff10
SS
1919 struct physdev_pirq_eoi_gmfn eoi_gmfn;
1920
38e20b07 1921 irq_ctx_init(smp_processor_id());
38aa66fc 1922 if (xen_initial_domain())
a0ee0567 1923 pci_xen_initial_domain();
9846ff10
SS
1924
1925 pirq_eoi_map = (void *)__get_free_page(GFP_KERNEL|__GFP_ZERO);
1926 eoi_gmfn.gmfn = virt_to_mfn(pirq_eoi_map);
1927 rc = HYPERVISOR_physdev_op(PHYSDEVOP_pirq_eoi_gmfn_v2, &eoi_gmfn);
1928 if (rc != 0) {
1929 free_page((unsigned long) pirq_eoi_map);
1930 pirq_eoi_map = NULL;
1931 } else
1932 pirq_needs_eoi = pirq_check_eoi_map;
38e20b07 1933 }
0ec53ecf 1934#endif
e46cdb66 1935}
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