regmap: Factor out debugfs register read
[deliverable/linux.git] / drivers / xen / events.c
CommitLineData
e46cdb66
JF
1/*
2 * Xen event channels
3 *
4 * Xen models interrupts with abstract event channels. Because each
5 * domain gets 1024 event channels, but NR_IRQ is not that large, we
6 * must dynamically map irqs<->event channels. The event channels
7 * interface with the rest of the kernel by defining a xen interrupt
25985edc 8 * chip. When an event is received, it is mapped to an irq and sent
e46cdb66
JF
9 * through the normal interrupt processing path.
10 *
11 * There are four kinds of events which can be mapped to an event
12 * channel:
13 *
14 * 1. Inter-domain notifications. This includes all the virtual
15 * device events, since they're driven by front-ends in another domain
16 * (typically dom0).
17 * 2. VIRQs, typically used for timers. These are per-cpu events.
18 * 3. IPIs.
d46a78b0 19 * 4. PIRQs - Hardware interrupts.
e46cdb66
JF
20 *
21 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
22 */
23
24#include <linux/linkage.h>
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/module.h>
28#include <linux/string.h>
28e08861 29#include <linux/bootmem.h>
5a0e3ad6 30#include <linux/slab.h>
b21ddbf5 31#include <linux/irqnr.h>
f731e3ef 32#include <linux/pci.h>
e46cdb66 33
0ec53ecf 34#ifdef CONFIG_X86
38e20b07 35#include <asm/desc.h>
e46cdb66
JF
36#include <asm/ptrace.h>
37#include <asm/irq.h>
792dc4f6 38#include <asm/idle.h>
0794bfc7 39#include <asm/io_apic.h>
9846ff10 40#include <asm/xen/page.h>
42a1de56 41#include <asm/xen/pci.h>
0ec53ecf
SS
42#endif
43#include <asm/sync_bitops.h>
e46cdb66 44#include <asm/xen/hypercall.h>
8d1b8753 45#include <asm/xen/hypervisor.h>
e46cdb66 46
38e20b07
SY
47#include <xen/xen.h>
48#include <xen/hvm.h>
e04d0d07 49#include <xen/xen-ops.h>
e46cdb66
JF
50#include <xen/events.h>
51#include <xen/interface/xen.h>
52#include <xen/interface/event_channel.h>
38e20b07
SY
53#include <xen/interface/hvm/hvm_op.h>
54#include <xen/interface/hvm/params.h>
0ec53ecf
SS
55#include <xen/interface/physdev.h>
56#include <xen/interface/sched.h>
57#include <asm/hw_irq.h>
e46cdb66 58
e46cdb66
JF
59/*
60 * This lock protects updates to the following mapping and reference-count
61 * arrays. The lock does not need to be acquired to read the mapping tables.
62 */
77365948 63static DEFINE_MUTEX(irq_mapping_update_lock);
e46cdb66 64
6cb6537d
IC
65static LIST_HEAD(xen_irq_list_head);
66
e46cdb66 67/* IRQ <-> VIRQ mapping. */
204fba4a 68static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
e46cdb66 69
f87e4cac 70/* IRQ <-> IPI mapping */
204fba4a 71static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
f87e4cac 72
ced40d0f
JF
73/* Interrupt types. */
74enum xen_irq_type {
d77bbd4d 75 IRQT_UNBOUND = 0,
f87e4cac
JF
76 IRQT_PIRQ,
77 IRQT_VIRQ,
78 IRQT_IPI,
79 IRQT_EVTCHN
80};
e46cdb66 81
ced40d0f
JF
82/*
83 * Packed IRQ information:
84 * type - enum xen_irq_type
85 * event channel - irq->event channel mapping
86 * cpu - cpu this event channel is bound to
87 * index - type-specific information:
42a1de56
SS
88 * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM
89 * guest, or GSI (real passthrough IRQ) of the device.
ced40d0f
JF
90 * VIRQ - virq number
91 * IPI - IPI vector
92 * EVTCHN -
93 */
088c05a8 94struct irq_info {
6cb6537d 95 struct list_head list;
420eb554 96 int refcnt;
ced40d0f 97 enum xen_irq_type type; /* type */
6cb6537d 98 unsigned irq;
ced40d0f
JF
99 unsigned short evtchn; /* event channel */
100 unsigned short cpu; /* cpu bound */
101
102 union {
103 unsigned short virq;
104 enum ipi_vector ipi;
105 struct {
7a043f11 106 unsigned short pirq;
ced40d0f 107 unsigned short gsi;
d46a78b0
JF
108 unsigned char vector;
109 unsigned char flags;
beafbdc1 110 uint16_t domid;
ced40d0f
JF
111 } pirq;
112 } u;
113};
d46a78b0 114#define PIRQ_NEEDS_EOI (1 << 0)
15ebbb82 115#define PIRQ_SHAREABLE (1 << 1)
ced40d0f 116
b21ddbf5 117static int *evtchn_to_irq;
9846ff10
SS
118static unsigned long *pirq_eoi_map;
119static bool (*pirq_needs_eoi)(unsigned irq);
3b32f574 120
cb60d114
IC
121static DEFINE_PER_CPU(unsigned long [NR_EVENT_CHANNELS/BITS_PER_LONG],
122 cpu_evtchn_mask);
e46cdb66 123
e46cdb66
JF
124/* Xen will never allocate port zero for any purpose. */
125#define VALID_EVTCHN(chn) ((chn) != 0)
126
e46cdb66 127static struct irq_chip xen_dynamic_chip;
aaca4964 128static struct irq_chip xen_percpu_chip;
d46a78b0 129static struct irq_chip xen_pirq_chip;
7e186bdd
SS
130static void enable_dynirq(struct irq_data *data);
131static void disable_dynirq(struct irq_data *data);
e46cdb66 132
9158c358
IC
133/* Get info for IRQ */
134static struct irq_info *info_for_irq(unsigned irq)
ced40d0f 135{
c442b806 136 return irq_get_handler_data(irq);
ced40d0f
JF
137}
138
9158c358
IC
139/* Constructors for packed IRQ information. */
140static void xen_irq_info_common_init(struct irq_info *info,
3d4cfa37 141 unsigned irq,
9158c358
IC
142 enum xen_irq_type type,
143 unsigned short evtchn,
144 unsigned short cpu)
ced40d0f 145{
9158c358
IC
146
147 BUG_ON(info->type != IRQT_UNBOUND && info->type != type);
148
149 info->type = type;
6cb6537d 150 info->irq = irq;
9158c358
IC
151 info->evtchn = evtchn;
152 info->cpu = cpu;
3d4cfa37
IC
153
154 evtchn_to_irq[evtchn] = irq;
ced40d0f
JF
155}
156
9158c358
IC
157static void xen_irq_info_evtchn_init(unsigned irq,
158 unsigned short evtchn)
ced40d0f 159{
9158c358
IC
160 struct irq_info *info = info_for_irq(irq);
161
3d4cfa37 162 xen_irq_info_common_init(info, irq, IRQT_EVTCHN, evtchn, 0);
ced40d0f
JF
163}
164
3d4cfa37
IC
165static void xen_irq_info_ipi_init(unsigned cpu,
166 unsigned irq,
9158c358
IC
167 unsigned short evtchn,
168 enum ipi_vector ipi)
e46cdb66 169{
9158c358
IC
170 struct irq_info *info = info_for_irq(irq);
171
3d4cfa37 172 xen_irq_info_common_init(info, irq, IRQT_IPI, evtchn, 0);
9158c358
IC
173
174 info->u.ipi = ipi;
3d4cfa37
IC
175
176 per_cpu(ipi_to_irq, cpu)[ipi] = irq;
ced40d0f
JF
177}
178
3d4cfa37
IC
179static void xen_irq_info_virq_init(unsigned cpu,
180 unsigned irq,
9158c358
IC
181 unsigned short evtchn,
182 unsigned short virq)
ced40d0f 183{
9158c358
IC
184 struct irq_info *info = info_for_irq(irq);
185
3d4cfa37 186 xen_irq_info_common_init(info, irq, IRQT_VIRQ, evtchn, 0);
9158c358
IC
187
188 info->u.virq = virq;
3d4cfa37
IC
189
190 per_cpu(virq_to_irq, cpu)[virq] = irq;
ced40d0f
JF
191}
192
9158c358
IC
193static void xen_irq_info_pirq_init(unsigned irq,
194 unsigned short evtchn,
195 unsigned short pirq,
196 unsigned short gsi,
197 unsigned short vector,
beafbdc1 198 uint16_t domid,
9158c358 199 unsigned char flags)
ced40d0f 200{
9158c358
IC
201 struct irq_info *info = info_for_irq(irq);
202
3d4cfa37 203 xen_irq_info_common_init(info, irq, IRQT_PIRQ, evtchn, 0);
9158c358
IC
204
205 info->u.pirq.pirq = pirq;
206 info->u.pirq.gsi = gsi;
207 info->u.pirq.vector = vector;
beafbdc1 208 info->u.pirq.domid = domid;
9158c358 209 info->u.pirq.flags = flags;
e46cdb66
JF
210}
211
212/*
213 * Accessors for packed IRQ information.
214 */
ced40d0f 215static unsigned int evtchn_from_irq(unsigned irq)
e46cdb66 216{
110e7c7e
JJ
217 if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
218 return 0;
219
ced40d0f 220 return info_for_irq(irq)->evtchn;
e46cdb66
JF
221}
222
d4c04536
IC
223unsigned irq_from_evtchn(unsigned int evtchn)
224{
225 return evtchn_to_irq[evtchn];
226}
227EXPORT_SYMBOL_GPL(irq_from_evtchn);
228
ced40d0f 229static enum ipi_vector ipi_from_irq(unsigned irq)
e46cdb66 230{
ced40d0f
JF
231 struct irq_info *info = info_for_irq(irq);
232
233 BUG_ON(info == NULL);
234 BUG_ON(info->type != IRQT_IPI);
235
236 return info->u.ipi;
237}
238
239static unsigned virq_from_irq(unsigned irq)
240{
241 struct irq_info *info = info_for_irq(irq);
242
243 BUG_ON(info == NULL);
244 BUG_ON(info->type != IRQT_VIRQ);
245
246 return info->u.virq;
247}
248
7a043f11
SS
249static unsigned pirq_from_irq(unsigned irq)
250{
251 struct irq_info *info = info_for_irq(irq);
252
253 BUG_ON(info == NULL);
254 BUG_ON(info->type != IRQT_PIRQ);
255
256 return info->u.pirq.pirq;
257}
258
ced40d0f
JF
259static enum xen_irq_type type_from_irq(unsigned irq)
260{
261 return info_for_irq(irq)->type;
262}
263
264static unsigned cpu_from_irq(unsigned irq)
265{
266 return info_for_irq(irq)->cpu;
267}
268
269static unsigned int cpu_from_evtchn(unsigned int evtchn)
270{
271 int irq = evtchn_to_irq[evtchn];
272 unsigned ret = 0;
273
274 if (irq != -1)
275 ret = cpu_from_irq(irq);
276
277 return ret;
e46cdb66
JF
278}
279
9846ff10 280static bool pirq_check_eoi_map(unsigned irq)
d46a78b0 281{
521394e4 282 return test_bit(pirq_from_irq(irq), pirq_eoi_map);
9846ff10 283}
d46a78b0 284
9846ff10
SS
285static bool pirq_needs_eoi_flag(unsigned irq)
286{
287 struct irq_info *info = info_for_irq(irq);
d46a78b0
JF
288 BUG_ON(info->type != IRQT_PIRQ);
289
290 return info->u.pirq.flags & PIRQ_NEEDS_EOI;
291}
292
e46cdb66
JF
293static inline unsigned long active_evtchns(unsigned int cpu,
294 struct shared_info *sh,
295 unsigned int idx)
296{
088c05a8 297 return sh->evtchn_pending[idx] &
cb60d114 298 per_cpu(cpu_evtchn_mask, cpu)[idx] &
088c05a8 299 ~sh->evtchn_mask[idx];
e46cdb66
JF
300}
301
302static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
303{
304 int irq = evtchn_to_irq[chn];
305
306 BUG_ON(irq == -1);
307#ifdef CONFIG_SMP
c9e265e0 308 cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu));
e46cdb66
JF
309#endif
310
cb60d114
IC
311 clear_bit(chn, per_cpu(cpu_evtchn_mask, cpu_from_irq(irq)));
312 set_bit(chn, per_cpu(cpu_evtchn_mask, cpu));
e46cdb66 313
ca62ce8c 314 info_for_irq(irq)->cpu = cpu;
e46cdb66
JF
315}
316
317static void init_evtchn_cpu_bindings(void)
318{
1c6969ec 319 int i;
e46cdb66 320#ifdef CONFIG_SMP
6cb6537d 321 struct irq_info *info;
10e58084 322
e46cdb66 323 /* By default all event channels notify CPU#0. */
6cb6537d
IC
324 list_for_each_entry(info, &xen_irq_list_head, list) {
325 struct irq_desc *desc = irq_to_desc(info->irq);
c9e265e0 326 cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
0b8f1efa 327 }
e46cdb66
JF
328#endif
329
1c6969ec 330 for_each_possible_cpu(i)
cb60d114
IC
331 memset(per_cpu(cpu_evtchn_mask, i),
332 (i == 0) ? ~0 : 0, sizeof(*per_cpu(cpu_evtchn_mask, i)));
e46cdb66
JF
333}
334
e46cdb66
JF
335static inline void clear_evtchn(int port)
336{
337 struct shared_info *s = HYPERVISOR_shared_info;
338 sync_clear_bit(port, &s->evtchn_pending[0]);
339}
340
341static inline void set_evtchn(int port)
342{
343 struct shared_info *s = HYPERVISOR_shared_info;
344 sync_set_bit(port, &s->evtchn_pending[0]);
345}
346
168d2f46
JF
347static inline int test_evtchn(int port)
348{
349 struct shared_info *s = HYPERVISOR_shared_info;
350 return sync_test_bit(port, &s->evtchn_pending[0]);
351}
352
e46cdb66
JF
353
354/**
355 * notify_remote_via_irq - send event to remote end of event channel via irq
356 * @irq: irq of event channel to send event to
357 *
358 * Unlike notify_remote_via_evtchn(), this is safe to use across
359 * save/restore. Notifications on a broken connection are silently
360 * dropped.
361 */
362void notify_remote_via_irq(int irq)
363{
364 int evtchn = evtchn_from_irq(irq);
365
366 if (VALID_EVTCHN(evtchn))
367 notify_remote_via_evtchn(evtchn);
368}
369EXPORT_SYMBOL_GPL(notify_remote_via_irq);
370
371static void mask_evtchn(int port)
372{
373 struct shared_info *s = HYPERVISOR_shared_info;
374 sync_set_bit(port, &s->evtchn_mask[0]);
375}
376
377static void unmask_evtchn(int port)
378{
379 struct shared_info *s = HYPERVISOR_shared_info;
380 unsigned int cpu = get_cpu();
b5e57923 381 int do_hypercall = 0, evtchn_pending = 0;
e46cdb66
JF
382
383 BUG_ON(!irqs_disabled());
384
b5e57923
SS
385 if (unlikely((cpu != cpu_from_evtchn(port))))
386 do_hypercall = 1;
387 else
388 evtchn_pending = sync_test_bit(port, &s->evtchn_pending[0]);
389
390 if (unlikely(evtchn_pending && xen_hvm_domain()))
391 do_hypercall = 1;
392
393 /* Slow path (hypercall) if this is a non-local port or if this is
394 * an hvm domain and an event is pending (hvm domains don't have
395 * their own implementation of irq_enable). */
396 if (do_hypercall) {
e46cdb66
JF
397 struct evtchn_unmask unmask = { .port = port };
398 (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
399 } else {
780f36d8 400 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
e46cdb66
JF
401
402 sync_clear_bit(port, &s->evtchn_mask[0]);
403
404 /*
405 * The following is basically the equivalent of
406 * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
407 * the interrupt edge' if the channel is masked.
408 */
b5e57923 409 if (evtchn_pending &&
e46cdb66
JF
410 !sync_test_and_set_bit(port / BITS_PER_LONG,
411 &vcpu_info->evtchn_pending_sel))
412 vcpu_info->evtchn_upcall_pending = 1;
413 }
414
415 put_cpu();
416}
417
6cb6537d
IC
418static void xen_irq_init(unsigned irq)
419{
420 struct irq_info *info;
b5328cd1 421#ifdef CONFIG_SMP
6cb6537d
IC
422 struct irq_desc *desc = irq_to_desc(irq);
423
424 /* By default all event channels notify CPU#0. */
425 cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
44626e4a 426#endif
6cb6537d 427
ca62ce8c
IC
428 info = kzalloc(sizeof(*info), GFP_KERNEL);
429 if (info == NULL)
430 panic("Unable to allocate metadata for IRQ%d\n", irq);
6cb6537d
IC
431
432 info->type = IRQT_UNBOUND;
420eb554 433 info->refcnt = -1;
6cb6537d 434
c442b806 435 irq_set_handler_data(irq, info);
ca62ce8c 436
6cb6537d
IC
437 list_add_tail(&info->list, &xen_irq_list_head);
438}
439
7bee9768 440static int __must_check xen_allocate_irq_dynamic(void)
0794bfc7 441{
89911501
IC
442 int first = 0;
443 int irq;
0794bfc7
KRW
444
445#ifdef CONFIG_X86_IO_APIC
89911501
IC
446 /*
447 * For an HVM guest or domain 0 which see "real" (emulated or
25985edc 448 * actual respectively) GSIs we allocate dynamic IRQs
89911501
IC
449 * e.g. those corresponding to event channels or MSIs
450 * etc. from the range above those "real" GSIs to avoid
451 * collisions.
452 */
453 if (xen_initial_domain() || xen_hvm_domain())
454 first = get_nr_irqs_gsi();
0794bfc7
KRW
455#endif
456
89911501 457 irq = irq_alloc_desc_from(first, -1);
3a69e916 458
e6599225
KRW
459 if (irq >= 0)
460 xen_irq_init(irq);
ced40d0f 461
e46cdb66 462 return irq;
d46a78b0
JF
463}
464
7bee9768 465static int __must_check xen_allocate_irq_gsi(unsigned gsi)
c9df1ce5
IC
466{
467 int irq;
468
89911501
IC
469 /*
470 * A PV guest has no concept of a GSI (since it has no ACPI
471 * nor access to/knowledge of the physical APICs). Therefore
472 * all IRQs are dynamically allocated from the entire IRQ
473 * space.
474 */
475 if (xen_pv_domain() && !xen_initial_domain())
c9df1ce5
IC
476 return xen_allocate_irq_dynamic();
477
478 /* Legacy IRQ descriptors are already allocated by the arch. */
479 if (gsi < NR_IRQS_LEGACY)
6cb6537d
IC
480 irq = gsi;
481 else
482 irq = irq_alloc_desc_at(gsi, -1);
c9df1ce5 483
6cb6537d 484 xen_irq_init(irq);
c9df1ce5
IC
485
486 return irq;
487}
488
489static void xen_free_irq(unsigned irq)
490{
c442b806 491 struct irq_info *info = irq_get_handler_data(irq);
6cb6537d
IC
492
493 list_del(&info->list);
9158c358 494
c442b806 495 irq_set_handler_data(irq, NULL);
ca62ce8c 496
420eb554
DDG
497 WARN_ON(info->refcnt > 0);
498
ca62ce8c
IC
499 kfree(info);
500
72146104
IC
501 /* Legacy IRQ descriptors are managed by the arch. */
502 if (irq < NR_IRQS_LEGACY)
503 return;
504
c9df1ce5
IC
505 irq_free_desc(irq);
506}
507
d46a78b0
JF
508static void pirq_query_unmask(int irq)
509{
510 struct physdev_irq_status_query irq_status;
511 struct irq_info *info = info_for_irq(irq);
512
513 BUG_ON(info->type != IRQT_PIRQ);
514
7a043f11 515 irq_status.irq = pirq_from_irq(irq);
d46a78b0
JF
516 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
517 irq_status.flags = 0;
518
519 info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
520 if (irq_status.flags & XENIRQSTAT_needs_eoi)
521 info->u.pirq.flags |= PIRQ_NEEDS_EOI;
522}
523
524static bool probing_irq(int irq)
525{
526 struct irq_desc *desc = irq_to_desc(irq);
527
528 return desc && desc->action == NULL;
529}
530
7e186bdd
SS
531static void eoi_pirq(struct irq_data *data)
532{
533 int evtchn = evtchn_from_irq(data->irq);
534 struct physdev_eoi eoi = { .irq = pirq_from_irq(data->irq) };
535 int rc = 0;
536
537 irq_move_irq(data);
538
539 if (VALID_EVTCHN(evtchn))
540 clear_evtchn(evtchn);
541
542 if (pirq_needs_eoi(data->irq)) {
543 rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
544 WARN_ON(rc);
545 }
546}
547
548static void mask_ack_pirq(struct irq_data *data)
549{
550 disable_dynirq(data);
551 eoi_pirq(data);
552}
553
c9e265e0 554static unsigned int __startup_pirq(unsigned int irq)
d46a78b0
JF
555{
556 struct evtchn_bind_pirq bind_pirq;
557 struct irq_info *info = info_for_irq(irq);
558 int evtchn = evtchn_from_irq(irq);
15ebbb82 559 int rc;
d46a78b0
JF
560
561 BUG_ON(info->type != IRQT_PIRQ);
562
563 if (VALID_EVTCHN(evtchn))
564 goto out;
565
7a043f11 566 bind_pirq.pirq = pirq_from_irq(irq);
d46a78b0 567 /* NB. We are happy to share unless we are probing. */
15ebbb82
KRW
568 bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
569 BIND_PIRQ__WILL_SHARE : 0;
570 rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
571 if (rc != 0) {
d46a78b0
JF
572 if (!probing_irq(irq))
573 printk(KERN_INFO "Failed to obtain physical IRQ %d\n",
574 irq);
575 return 0;
576 }
577 evtchn = bind_pirq.port;
578
579 pirq_query_unmask(irq);
580
581 evtchn_to_irq[evtchn] = irq;
582 bind_evtchn_to_cpu(evtchn, 0);
583 info->evtchn = evtchn;
584
585out:
586 unmask_evtchn(evtchn);
7e186bdd 587 eoi_pirq(irq_get_irq_data(irq));
d46a78b0
JF
588
589 return 0;
590}
591
c9e265e0
TG
592static unsigned int startup_pirq(struct irq_data *data)
593{
594 return __startup_pirq(data->irq);
595}
596
597static void shutdown_pirq(struct irq_data *data)
d46a78b0
JF
598{
599 struct evtchn_close close;
c9e265e0 600 unsigned int irq = data->irq;
d46a78b0
JF
601 struct irq_info *info = info_for_irq(irq);
602 int evtchn = evtchn_from_irq(irq);
603
604 BUG_ON(info->type != IRQT_PIRQ);
605
606 if (!VALID_EVTCHN(evtchn))
607 return;
608
609 mask_evtchn(evtchn);
610
611 close.port = evtchn;
612 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
613 BUG();
614
615 bind_evtchn_to_cpu(evtchn, 0);
616 evtchn_to_irq[evtchn] = -1;
617 info->evtchn = 0;
618}
619
c9e265e0 620static void enable_pirq(struct irq_data *data)
d46a78b0 621{
c9e265e0 622 startup_pirq(data);
d46a78b0
JF
623}
624
c9e265e0 625static void disable_pirq(struct irq_data *data)
d46a78b0 626{
7e186bdd 627 disable_dynirq(data);
d46a78b0
JF
628}
629
68c2c39a 630int xen_irq_from_gsi(unsigned gsi)
d46a78b0 631{
6cb6537d 632 struct irq_info *info;
d46a78b0 633
6cb6537d
IC
634 list_for_each_entry(info, &xen_irq_list_head, list) {
635 if (info->type != IRQT_PIRQ)
d46a78b0
JF
636 continue;
637
6cb6537d
IC
638 if (info->u.pirq.gsi == gsi)
639 return info->irq;
d46a78b0
JF
640 }
641
642 return -1;
643}
68c2c39a 644EXPORT_SYMBOL_GPL(xen_irq_from_gsi);
d46a78b0 645
653378ac
IC
646/*
647 * Do not make any assumptions regarding the relationship between the
648 * IRQ number returned here and the Xen pirq argument.
7a043f11
SS
649 *
650 * Note: We don't assign an event channel until the irq actually started
651 * up. Return an existing irq if we've already got one for the gsi.
e5ac0bda
SS
652 *
653 * Shareable implies level triggered, not shareable implies edge
654 * triggered here.
d46a78b0 655 */
f4d0635b
IC
656int xen_bind_pirq_gsi_to_irq(unsigned gsi,
657 unsigned pirq, int shareable, char *name)
d46a78b0 658{
a0e18116 659 int irq = -1;
d46a78b0
JF
660 struct physdev_irq irq_op;
661
77365948 662 mutex_lock(&irq_mapping_update_lock);
d46a78b0 663
68c2c39a 664 irq = xen_irq_from_gsi(gsi);
d46a78b0 665 if (irq != -1) {
7a043f11 666 printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n",
d46a78b0 667 irq, gsi);
420eb554 668 goto out;
d46a78b0
JF
669 }
670
c9df1ce5 671 irq = xen_allocate_irq_gsi(gsi);
7bee9768
IC
672 if (irq < 0)
673 goto out;
d46a78b0 674
d46a78b0 675 irq_op.irq = irq;
b5401a96
AN
676 irq_op.vector = 0;
677
678 /* Only the privileged domain can do this. For non-priv, the pcifront
679 * driver provides a PCI bus that does the call to do exactly
680 * this in the priv domain. */
681 if (xen_initial_domain() &&
682 HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
c9df1ce5 683 xen_free_irq(irq);
d46a78b0
JF
684 irq = -ENOSPC;
685 goto out;
686 }
687
beafbdc1 688 xen_irq_info_pirq_init(irq, 0, pirq, gsi, irq_op.vector, DOMID_SELF,
9158c358 689 shareable ? PIRQ_SHAREABLE : 0);
d46a78b0 690
7e186bdd
SS
691 pirq_query_unmask(irq);
692 /* We try to use the handler with the appropriate semantic for the
e5ac0bda
SS
693 * type of interrupt: if the interrupt is an edge triggered
694 * interrupt we use handle_edge_irq.
7e186bdd 695 *
e5ac0bda
SS
696 * On the other hand if the interrupt is level triggered we use
697 * handle_fasteoi_irq like the native code does for this kind of
7e186bdd 698 * interrupts.
e5ac0bda 699 *
7e186bdd
SS
700 * Depending on the Xen version, pirq_needs_eoi might return true
701 * not only for level triggered interrupts but for edge triggered
702 * interrupts too. In any case Xen always honors the eoi mechanism,
703 * not injecting any more pirqs of the same kind if the first one
704 * hasn't received an eoi yet. Therefore using the fasteoi handler
705 * is the right choice either way.
706 */
e5ac0bda 707 if (shareable)
7e186bdd
SS
708 irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
709 handle_fasteoi_irq, name);
710 else
711 irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
712 handle_edge_irq, name);
713
d46a78b0 714out:
77365948 715 mutex_unlock(&irq_mapping_update_lock);
d46a78b0
JF
716
717 return irq;
718}
719
f731e3ef 720#ifdef CONFIG_PCI_MSI
bf480d95 721int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc)
cbf6aa89 722{
5cad61a6 723 int rc;
cbf6aa89 724 struct physdev_get_free_pirq op_get_free_pirq;
cbf6aa89 725
bf480d95 726 op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI;
cbf6aa89 727 rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
cbf6aa89 728
5cad61a6
IC
729 WARN_ONCE(rc == -ENOSYS,
730 "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n");
731
732 return rc ? -1 : op_get_free_pirq.pirq;
cbf6aa89
IC
733}
734
bf480d95 735int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc,
beafbdc1
KRW
736 int pirq, int vector, const char *name,
737 domid_t domid)
809f9267 738{
bf480d95 739 int irq, ret;
4b41df7f 740
77365948 741 mutex_lock(&irq_mapping_update_lock);
809f9267 742
4b41df7f 743 irq = xen_allocate_irq_dynamic();
e6599225 744 if (irq < 0)
bb5d079a 745 goto out;
809f9267 746
7e186bdd
SS
747 irq_set_chip_and_handler_name(irq, &xen_pirq_chip, handle_edge_irq,
748 name);
809f9267 749
beafbdc1 750 xen_irq_info_pirq_init(irq, 0, pirq, 0, vector, domid, 0);
5f6fb454 751 ret = irq_set_msi_desc(irq, msidesc);
bf480d95
IC
752 if (ret < 0)
753 goto error_irq;
809f9267 754out:
77365948 755 mutex_unlock(&irq_mapping_update_lock);
4b41df7f 756 return irq;
bf480d95 757error_irq:
77365948 758 mutex_unlock(&irq_mapping_update_lock);
bf480d95 759 xen_free_irq(irq);
e6599225 760 return ret;
809f9267 761}
f731e3ef
QH
762#endif
763
b5401a96
AN
764int xen_destroy_irq(int irq)
765{
766 struct irq_desc *desc;
38aa66fc
JF
767 struct physdev_unmap_pirq unmap_irq;
768 struct irq_info *info = info_for_irq(irq);
b5401a96
AN
769 int rc = -ENOENT;
770
77365948 771 mutex_lock(&irq_mapping_update_lock);
b5401a96
AN
772
773 desc = irq_to_desc(irq);
774 if (!desc)
775 goto out;
776
38aa66fc 777 if (xen_initial_domain()) {
12334715 778 unmap_irq.pirq = info->u.pirq.pirq;
beafbdc1 779 unmap_irq.domid = info->u.pirq.domid;
38aa66fc 780 rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
1eff1ad0
KRW
781 /* If another domain quits without making the pci_disable_msix
782 * call, the Xen hypervisor takes care of freeing the PIRQs
783 * (free_domain_pirqs).
784 */
785 if ((rc == -ESRCH && info->u.pirq.domid != DOMID_SELF))
786 printk(KERN_INFO "domain %d does not have %d anymore\n",
787 info->u.pirq.domid, info->u.pirq.pirq);
788 else if (rc) {
38aa66fc
JF
789 printk(KERN_WARNING "unmap irq failed %d\n", rc);
790 goto out;
791 }
792 }
b5401a96 793
c9df1ce5 794 xen_free_irq(irq);
b5401a96
AN
795
796out:
77365948 797 mutex_unlock(&irq_mapping_update_lock);
b5401a96
AN
798 return rc;
799}
800
af42b8d1 801int xen_irq_from_pirq(unsigned pirq)
d46a78b0 802{
69c358ce 803 int irq;
d46a78b0 804
69c358ce 805 struct irq_info *info;
e46cdb66 806
77365948 807 mutex_lock(&irq_mapping_update_lock);
69c358ce
IC
808
809 list_for_each_entry(info, &xen_irq_list_head, list) {
9bb9efe4 810 if (info->type != IRQT_PIRQ)
69c358ce
IC
811 continue;
812 irq = info->irq;
813 if (info->u.pirq.pirq == pirq)
814 goto out;
815 }
816 irq = -1;
817out:
77365948 818 mutex_unlock(&irq_mapping_update_lock);
69c358ce
IC
819
820 return irq;
af42b8d1
SS
821}
822
e6197acc
KRW
823
824int xen_pirq_from_irq(unsigned irq)
825{
826 return pirq_from_irq(irq);
827}
828EXPORT_SYMBOL_GPL(xen_pirq_from_irq);
b536b4b9 829int bind_evtchn_to_irq(unsigned int evtchn)
e46cdb66
JF
830{
831 int irq;
832
77365948 833 mutex_lock(&irq_mapping_update_lock);
e46cdb66
JF
834
835 irq = evtchn_to_irq[evtchn];
836
837 if (irq == -1) {
c9df1ce5 838 irq = xen_allocate_irq_dynamic();
7bee9768
IC
839 if (irq == -1)
840 goto out;
e46cdb66 841
c442b806 842 irq_set_chip_and_handler_name(irq, &xen_dynamic_chip,
7e186bdd 843 handle_edge_irq, "event");
e46cdb66 844
9158c358 845 xen_irq_info_evtchn_init(irq, evtchn);
5e152e6c
KRW
846 } else {
847 struct irq_info *info = info_for_irq(irq);
848 WARN_ON(info == NULL || info->type != IRQT_EVTCHN);
e46cdb66 849 }
a8636c0b 850 irq_clear_status_flags(irq, IRQ_NOREQUEST|IRQ_NOAUTOEN);
e46cdb66 851
7bee9768 852out:
77365948 853 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
854
855 return irq;
856}
b536b4b9 857EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
e46cdb66 858
f87e4cac
JF
859static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
860{
861 struct evtchn_bind_ipi bind_ipi;
862 int evtchn, irq;
863
77365948 864 mutex_lock(&irq_mapping_update_lock);
f87e4cac
JF
865
866 irq = per_cpu(ipi_to_irq, cpu)[ipi];
90af9514 867
f87e4cac 868 if (irq == -1) {
c9df1ce5 869 irq = xen_allocate_irq_dynamic();
f87e4cac
JF
870 if (irq < 0)
871 goto out;
872
c442b806 873 irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
aaca4964 874 handle_percpu_irq, "ipi");
f87e4cac
JF
875
876 bind_ipi.vcpu = cpu;
877 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
878 &bind_ipi) != 0)
879 BUG();
880 evtchn = bind_ipi.port;
881
3d4cfa37 882 xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
f87e4cac
JF
883
884 bind_evtchn_to_cpu(evtchn, cpu);
5e152e6c
KRW
885 } else {
886 struct irq_info *info = info_for_irq(irq);
887 WARN_ON(info == NULL || info->type != IRQT_IPI);
f87e4cac
JF
888 }
889
f87e4cac 890 out:
77365948 891 mutex_unlock(&irq_mapping_update_lock);
f87e4cac
JF
892 return irq;
893}
894
2e820f58
IC
895static int bind_interdomain_evtchn_to_irq(unsigned int remote_domain,
896 unsigned int remote_port)
897{
898 struct evtchn_bind_interdomain bind_interdomain;
899 int err;
900
901 bind_interdomain.remote_dom = remote_domain;
902 bind_interdomain.remote_port = remote_port;
903
904 err = HYPERVISOR_event_channel_op(EVTCHNOP_bind_interdomain,
905 &bind_interdomain);
906
907 return err ? : bind_evtchn_to_irq(bind_interdomain.local_port);
908}
909
62cc5fc7
OH
910static int find_virq(unsigned int virq, unsigned int cpu)
911{
912 struct evtchn_status status;
913 int port, rc = -ENOENT;
914
915 memset(&status, 0, sizeof(status));
916 for (port = 0; port <= NR_EVENT_CHANNELS; port++) {
917 status.dom = DOMID_SELF;
918 status.port = port;
919 rc = HYPERVISOR_event_channel_op(EVTCHNOP_status, &status);
920 if (rc < 0)
921 continue;
922 if (status.status != EVTCHNSTAT_virq)
923 continue;
924 if (status.u.virq == virq && status.vcpu == cpu) {
925 rc = port;
926 break;
927 }
928 }
929 return rc;
930}
f87e4cac 931
4fe7d5a7 932int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
e46cdb66
JF
933{
934 struct evtchn_bind_virq bind_virq;
62cc5fc7 935 int evtchn, irq, ret;
e46cdb66 936
77365948 937 mutex_lock(&irq_mapping_update_lock);
e46cdb66
JF
938
939 irq = per_cpu(virq_to_irq, cpu)[virq];
940
941 if (irq == -1) {
c9df1ce5 942 irq = xen_allocate_irq_dynamic();
7bee9768
IC
943 if (irq == -1)
944 goto out;
a52521f1 945
c442b806 946 irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
a52521f1
JF
947 handle_percpu_irq, "virq");
948
e46cdb66
JF
949 bind_virq.virq = virq;
950 bind_virq.vcpu = cpu;
62cc5fc7
OH
951 ret = HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
952 &bind_virq);
953 if (ret == 0)
954 evtchn = bind_virq.port;
955 else {
956 if (ret == -EEXIST)
957 ret = find_virq(virq, cpu);
958 BUG_ON(ret < 0);
959 evtchn = ret;
960 }
e46cdb66 961
3d4cfa37 962 xen_irq_info_virq_init(cpu, irq, evtchn, virq);
e46cdb66
JF
963
964 bind_evtchn_to_cpu(evtchn, cpu);
5e152e6c
KRW
965 } else {
966 struct irq_info *info = info_for_irq(irq);
967 WARN_ON(info == NULL || info->type != IRQT_VIRQ);
e46cdb66
JF
968 }
969
7bee9768 970out:
77365948 971 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
972
973 return irq;
974}
975
976static void unbind_from_irq(unsigned int irq)
977{
978 struct evtchn_close close;
979 int evtchn = evtchn_from_irq(irq);
420eb554 980 struct irq_info *info = irq_get_handler_data(irq);
e46cdb66 981
77365948 982 mutex_lock(&irq_mapping_update_lock);
e46cdb66 983
420eb554
DDG
984 if (info->refcnt > 0) {
985 info->refcnt--;
986 if (info->refcnt != 0)
987 goto done;
988 }
989
d77bbd4d 990 if (VALID_EVTCHN(evtchn)) {
e46cdb66
JF
991 close.port = evtchn;
992 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
993 BUG();
994
995 switch (type_from_irq(irq)) {
996 case IRQT_VIRQ:
997 per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 998 [virq_from_irq(irq)] = -1;
e46cdb66 999 break;
d68d82af
AN
1000 case IRQT_IPI:
1001 per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 1002 [ipi_from_irq(irq)] = -1;
d68d82af 1003 break;
e46cdb66
JF
1004 default:
1005 break;
1006 }
1007
1008 /* Closed ports are implicitly re-bound to VCPU0. */
1009 bind_evtchn_to_cpu(evtchn, 0);
1010
1011 evtchn_to_irq[evtchn] = -1;
fed5ea87
IC
1012 }
1013
ca62ce8c 1014 BUG_ON(info_for_irq(irq)->type == IRQT_UNBOUND);
e46cdb66 1015
9158c358 1016 xen_free_irq(irq);
e46cdb66 1017
420eb554 1018 done:
77365948 1019 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
1020}
1021
1022int bind_evtchn_to_irqhandler(unsigned int evtchn,
7c239975 1023 irq_handler_t handler,
e46cdb66
JF
1024 unsigned long irqflags,
1025 const char *devname, void *dev_id)
1026{
361ae8cb 1027 int irq, retval;
e46cdb66
JF
1028
1029 irq = bind_evtchn_to_irq(evtchn);
7bee9768
IC
1030 if (irq < 0)
1031 return irq;
e46cdb66
JF
1032 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1033 if (retval != 0) {
1034 unbind_from_irq(irq);
1035 return retval;
1036 }
1037
1038 return irq;
1039}
1040EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
1041
2e820f58
IC
1042int bind_interdomain_evtchn_to_irqhandler(unsigned int remote_domain,
1043 unsigned int remote_port,
1044 irq_handler_t handler,
1045 unsigned long irqflags,
1046 const char *devname,
1047 void *dev_id)
1048{
1049 int irq, retval;
1050
1051 irq = bind_interdomain_evtchn_to_irq(remote_domain, remote_port);
1052 if (irq < 0)
1053 return irq;
1054
1055 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1056 if (retval != 0) {
1057 unbind_from_irq(irq);
1058 return retval;
1059 }
1060
1061 return irq;
1062}
1063EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irqhandler);
1064
e46cdb66 1065int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
7c239975 1066 irq_handler_t handler,
e46cdb66
JF
1067 unsigned long irqflags, const char *devname, void *dev_id)
1068{
361ae8cb 1069 int irq, retval;
e46cdb66
JF
1070
1071 irq = bind_virq_to_irq(virq, cpu);
7bee9768
IC
1072 if (irq < 0)
1073 return irq;
e46cdb66
JF
1074 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1075 if (retval != 0) {
1076 unbind_from_irq(irq);
1077 return retval;
1078 }
1079
1080 return irq;
1081}
1082EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
1083
f87e4cac
JF
1084int bind_ipi_to_irqhandler(enum ipi_vector ipi,
1085 unsigned int cpu,
1086 irq_handler_t handler,
1087 unsigned long irqflags,
1088 const char *devname,
1089 void *dev_id)
1090{
1091 int irq, retval;
1092
1093 irq = bind_ipi_to_irq(ipi, cpu);
1094 if (irq < 0)
1095 return irq;
1096
9bab0b7f 1097 irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME | IRQF_EARLY_RESUME;
f87e4cac
JF
1098 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1099 if (retval != 0) {
1100 unbind_from_irq(irq);
1101 return retval;
1102 }
1103
1104 return irq;
1105}
1106
e46cdb66
JF
1107void unbind_from_irqhandler(unsigned int irq, void *dev_id)
1108{
1109 free_irq(irq, dev_id);
1110 unbind_from_irq(irq);
1111}
1112EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
1113
420eb554
DDG
1114int evtchn_make_refcounted(unsigned int evtchn)
1115{
1116 int irq = evtchn_to_irq[evtchn];
1117 struct irq_info *info;
1118
1119 if (irq == -1)
1120 return -ENOENT;
1121
1122 info = irq_get_handler_data(irq);
1123
1124 if (!info)
1125 return -ENOENT;
1126
1127 WARN_ON(info->refcnt != -1);
1128
1129 info->refcnt = 1;
1130
1131 return 0;
1132}
1133EXPORT_SYMBOL_GPL(evtchn_make_refcounted);
1134
1135int evtchn_get(unsigned int evtchn)
1136{
1137 int irq;
1138 struct irq_info *info;
1139 int err = -ENOENT;
1140
c3b3f16d
DDG
1141 if (evtchn >= NR_EVENT_CHANNELS)
1142 return -EINVAL;
1143
420eb554
DDG
1144 mutex_lock(&irq_mapping_update_lock);
1145
1146 irq = evtchn_to_irq[evtchn];
1147 if (irq == -1)
1148 goto done;
1149
1150 info = irq_get_handler_data(irq);
1151
1152 if (!info)
1153 goto done;
1154
1155 err = -EINVAL;
1156 if (info->refcnt <= 0)
1157 goto done;
1158
1159 info->refcnt++;
1160 err = 0;
1161 done:
1162 mutex_unlock(&irq_mapping_update_lock);
1163
1164 return err;
1165}
1166EXPORT_SYMBOL_GPL(evtchn_get);
1167
1168void evtchn_put(unsigned int evtchn)
1169{
1170 int irq = evtchn_to_irq[evtchn];
1171 if (WARN_ON(irq == -1))
1172 return;
1173 unbind_from_irq(irq);
1174}
1175EXPORT_SYMBOL_GPL(evtchn_put);
1176
f87e4cac
JF
1177void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
1178{
1179 int irq = per_cpu(ipi_to_irq, cpu)[vector];
1180 BUG_ON(irq < 0);
1181 notify_remote_via_irq(irq);
1182}
1183
ee523ca1
JF
1184irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
1185{
1186 struct shared_info *sh = HYPERVISOR_shared_info;
1187 int cpu = smp_processor_id();
cb60d114 1188 unsigned long *cpu_evtchn = per_cpu(cpu_evtchn_mask, cpu);
ee523ca1
JF
1189 int i;
1190 unsigned long flags;
1191 static DEFINE_SPINLOCK(debug_lock);
cb52e6d9 1192 struct vcpu_info *v;
ee523ca1
JF
1193
1194 spin_lock_irqsave(&debug_lock, flags);
1195
cb52e6d9 1196 printk("\nvcpu %d\n ", cpu);
ee523ca1
JF
1197
1198 for_each_online_cpu(i) {
cb52e6d9
IC
1199 int pending;
1200 v = per_cpu(xen_vcpu, i);
1201 pending = (get_irq_regs() && i == cpu)
1202 ? xen_irqs_disabled(get_irq_regs())
1203 : v->evtchn_upcall_mask;
1204 printk("%d: masked=%d pending=%d event_sel %0*lx\n ", i,
1205 pending, v->evtchn_upcall_pending,
1206 (int)(sizeof(v->evtchn_pending_sel)*2),
1207 v->evtchn_pending_sel);
1208 }
1209 v = per_cpu(xen_vcpu, cpu);
1210
1211 printk("\npending:\n ");
1212 for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
1213 printk("%0*lx%s", (int)sizeof(sh->evtchn_pending[0])*2,
1214 sh->evtchn_pending[i],
1215 i % 8 == 0 ? "\n " : " ");
1216 printk("\nglobal mask:\n ");
1217 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
1218 printk("%0*lx%s",
1219 (int)(sizeof(sh->evtchn_mask[0])*2),
1220 sh->evtchn_mask[i],
1221 i % 8 == 0 ? "\n " : " ");
1222
1223 printk("\nglobally unmasked:\n ");
1224 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
1225 printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
1226 sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
1227 i % 8 == 0 ? "\n " : " ");
1228
1229 printk("\nlocal cpu%d mask:\n ", cpu);
1230 for (i = (NR_EVENT_CHANNELS/BITS_PER_LONG)-1; i >= 0; i--)
1231 printk("%0*lx%s", (int)(sizeof(cpu_evtchn[0])*2),
1232 cpu_evtchn[i],
1233 i % 8 == 0 ? "\n " : " ");
1234
1235 printk("\nlocally unmasked:\n ");
1236 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
1237 unsigned long pending = sh->evtchn_pending[i]
1238 & ~sh->evtchn_mask[i]
1239 & cpu_evtchn[i];
1240 printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
1241 pending, i % 8 == 0 ? "\n " : " ");
ee523ca1 1242 }
ee523ca1
JF
1243
1244 printk("\npending list:\n");
cb52e6d9 1245 for (i = 0; i < NR_EVENT_CHANNELS; i++) {
ee523ca1 1246 if (sync_test_bit(i, sh->evtchn_pending)) {
cb52e6d9
IC
1247 int word_idx = i / BITS_PER_LONG;
1248 printk(" %d: event %d -> irq %d%s%s%s\n",
ced40d0f 1249 cpu_from_evtchn(i), i,
cb52e6d9
IC
1250 evtchn_to_irq[i],
1251 sync_test_bit(word_idx, &v->evtchn_pending_sel)
1252 ? "" : " l2-clear",
1253 !sync_test_bit(i, sh->evtchn_mask)
1254 ? "" : " globally-masked",
1255 sync_test_bit(i, cpu_evtchn)
1256 ? "" : " locally-masked");
ee523ca1
JF
1257 }
1258 }
1259
1260 spin_unlock_irqrestore(&debug_lock, flags);
1261
1262 return IRQ_HANDLED;
1263}
1264
245b2e70 1265static DEFINE_PER_CPU(unsigned, xed_nesting_count);
ada6814c
KF
1266static DEFINE_PER_CPU(unsigned int, current_word_idx);
1267static DEFINE_PER_CPU(unsigned int, current_bit_idx);
245b2e70 1268
ab7f863e
SR
1269/*
1270 * Mask out the i least significant bits of w
1271 */
1272#define MASK_LSBS(w, i) (w & ((~0UL) << i))
245b2e70 1273
e46cdb66
JF
1274/*
1275 * Search the CPUs pending events bitmasks. For each one found, map
1276 * the event number to an irq, and feed it into do_IRQ() for
1277 * handling.
1278 *
1279 * Xen uses a two-level bitmap to speed searching. The first level is
1280 * a bitset of words which contain pending event bits. The second
1281 * level is a bitset of pending events themselves.
1282 */
38e20b07 1283static void __xen_evtchn_do_upcall(void)
e46cdb66 1284{
24b51c2f 1285 int start_word_idx, start_bit_idx;
ab7f863e 1286 int word_idx, bit_idx;
24b51c2f 1287 int i;
e46cdb66
JF
1288 int cpu = get_cpu();
1289 struct shared_info *s = HYPERVISOR_shared_info;
780f36d8 1290 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
088c05a8 1291 unsigned count;
e46cdb66 1292
229664be
JF
1293 do {
1294 unsigned long pending_words;
e46cdb66 1295
229664be 1296 vcpu_info->evtchn_upcall_pending = 0;
e46cdb66 1297
b2e4ae69 1298 if (__this_cpu_inc_return(xed_nesting_count) - 1)
229664be 1299 goto out;
e46cdb66 1300
e849c3e9
IY
1301#ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */
1302 /* Clear master flag /before/ clearing selector flag. */
6673cf63 1303 wmb();
e849c3e9 1304#endif
229664be 1305 pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0);
ab7f863e 1306
24b51c2f
KF
1307 start_word_idx = __this_cpu_read(current_word_idx);
1308 start_bit_idx = __this_cpu_read(current_bit_idx);
1309
1310 word_idx = start_word_idx;
ab7f863e 1311
24b51c2f 1312 for (i = 0; pending_words != 0; i++) {
229664be 1313 unsigned long pending_bits;
ab7f863e 1314 unsigned long words;
229664be 1315
ab7f863e
SR
1316 words = MASK_LSBS(pending_words, word_idx);
1317
1318 /*
ada6814c 1319 * If we masked out all events, wrap to beginning.
ab7f863e
SR
1320 */
1321 if (words == 0) {
ada6814c
KF
1322 word_idx = 0;
1323 bit_idx = 0;
ab7f863e
SR
1324 continue;
1325 }
1326 word_idx = __ffs(words);
229664be 1327
24b51c2f
KF
1328 pending_bits = active_evtchns(cpu, s, word_idx);
1329 bit_idx = 0; /* usually scan entire word from start */
1330 if (word_idx == start_word_idx) {
1331 /* We scan the starting word in two parts */
1332 if (i == 0)
1333 /* 1st time: start in the middle */
1334 bit_idx = start_bit_idx;
1335 else
1336 /* 2nd time: mask bits done already */
1337 bit_idx &= (1UL << start_bit_idx) - 1;
1338 }
1339
ab7f863e
SR
1340 do {
1341 unsigned long bits;
1342 int port, irq;
ca4dbc66 1343 struct irq_desc *desc;
229664be 1344
ab7f863e
SR
1345 bits = MASK_LSBS(pending_bits, bit_idx);
1346
1347 /* If we masked out all events, move on. */
ada6814c 1348 if (bits == 0)
ab7f863e 1349 break;
ab7f863e
SR
1350
1351 bit_idx = __ffs(bits);
1352
1353 /* Process port. */
1354 port = (word_idx * BITS_PER_LONG) + bit_idx;
1355 irq = evtchn_to_irq[port];
1356
ca4dbc66
EB
1357 if (irq != -1) {
1358 desc = irq_to_desc(irq);
1359 if (desc)
1360 generic_handle_irq_desc(irq, desc);
1361 }
ab7f863e 1362
ada6814c
KF
1363 bit_idx = (bit_idx + 1) % BITS_PER_LONG;
1364
1365 /* Next caller starts at last processed + 1 */
1366 __this_cpu_write(current_word_idx,
1367 bit_idx ? word_idx :
1368 (word_idx+1) % BITS_PER_LONG);
1369 __this_cpu_write(current_bit_idx, bit_idx);
1370 } while (bit_idx != 0);
ab7f863e 1371
24b51c2f
KF
1372 /* Scan start_l1i twice; all others once. */
1373 if ((word_idx != start_word_idx) || (i != 0))
ab7f863e 1374 pending_words &= ~(1UL << word_idx);
ada6814c
KF
1375
1376 word_idx = (word_idx + 1) % BITS_PER_LONG;
e46cdb66 1377 }
e46cdb66 1378
229664be
JF
1379 BUG_ON(!irqs_disabled());
1380
780f36d8
CL
1381 count = __this_cpu_read(xed_nesting_count);
1382 __this_cpu_write(xed_nesting_count, 0);
183d03cc 1383 } while (count != 1 || vcpu_info->evtchn_upcall_pending);
229664be
JF
1384
1385out:
38e20b07
SY
1386
1387 put_cpu();
1388}
1389
1390void xen_evtchn_do_upcall(struct pt_regs *regs)
1391{
1392 struct pt_regs *old_regs = set_irq_regs(regs);
1393
0ec53ecf 1394#ifdef CONFIG_X86
38e20b07 1395 exit_idle();
0ec53ecf 1396#endif
38e20b07
SY
1397 irq_enter();
1398
1399 __xen_evtchn_do_upcall();
1400
3445a8fd
JF
1401 irq_exit();
1402 set_irq_regs(old_regs);
38e20b07 1403}
3445a8fd 1404
38e20b07
SY
1405void xen_hvm_evtchn_do_upcall(void)
1406{
1407 __xen_evtchn_do_upcall();
e46cdb66 1408}
183d03cc 1409EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
e46cdb66 1410
eb1e305f
JF
1411/* Rebind a new event channel to an existing irq. */
1412void rebind_evtchn_irq(int evtchn, int irq)
1413{
d77bbd4d
JF
1414 struct irq_info *info = info_for_irq(irq);
1415
eb1e305f
JF
1416 /* Make sure the irq is masked, since the new event channel
1417 will also be masked. */
1418 disable_irq(irq);
1419
77365948 1420 mutex_lock(&irq_mapping_update_lock);
eb1e305f
JF
1421
1422 /* After resume the irq<->evtchn mappings are all cleared out */
1423 BUG_ON(evtchn_to_irq[evtchn] != -1);
1424 /* Expect irq to have been bound before,
d77bbd4d
JF
1425 so there should be a proper type */
1426 BUG_ON(info->type == IRQT_UNBOUND);
eb1e305f 1427
9158c358 1428 xen_irq_info_evtchn_init(irq, evtchn);
eb1e305f 1429
77365948 1430 mutex_unlock(&irq_mapping_update_lock);
eb1e305f
JF
1431
1432 /* new event channels are always bound to cpu 0 */
0de26520 1433 irq_set_affinity(irq, cpumask_of(0));
eb1e305f
JF
1434
1435 /* Unmask the event channel. */
1436 enable_irq(irq);
1437}
1438
e46cdb66 1439/* Rebind an evtchn so that it gets delivered to a specific cpu */
d5dedd45 1440static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
e46cdb66
JF
1441{
1442 struct evtchn_bind_vcpu bind_vcpu;
1443 int evtchn = evtchn_from_irq(irq);
1444
be49472f
IC
1445 if (!VALID_EVTCHN(evtchn))
1446 return -1;
1447
1448 /*
1449 * Events delivered via platform PCI interrupts are always
1450 * routed to vcpu 0 and hence cannot be rebound.
1451 */
1452 if (xen_hvm_domain() && !xen_have_vector_callback)
d5dedd45 1453 return -1;
e46cdb66
JF
1454
1455 /* Send future instances of this interrupt to other vcpu. */
1456 bind_vcpu.port = evtchn;
1457 bind_vcpu.vcpu = tcpu;
1458
1459 /*
1460 * If this fails, it usually just indicates that we're dealing with a
1461 * virq or IPI channel, which don't actually need to be rebound. Ignore
1462 * it, but don't do the xenlinux-level rebind in that case.
1463 */
1464 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
1465 bind_evtchn_to_cpu(evtchn, tcpu);
e46cdb66 1466
d5dedd45
YL
1467 return 0;
1468}
e46cdb66 1469
c9e265e0
TG
1470static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest,
1471 bool force)
e46cdb66 1472{
0de26520 1473 unsigned tcpu = cpumask_first(dest);
d5dedd45 1474
c9e265e0 1475 return rebind_irq_to_cpu(data->irq, tcpu);
e46cdb66
JF
1476}
1477
642e0c88
IY
1478int resend_irq_on_evtchn(unsigned int irq)
1479{
1480 int masked, evtchn = evtchn_from_irq(irq);
1481 struct shared_info *s = HYPERVISOR_shared_info;
1482
1483 if (!VALID_EVTCHN(evtchn))
1484 return 1;
1485
1486 masked = sync_test_and_set_bit(evtchn, s->evtchn_mask);
1487 sync_set_bit(evtchn, s->evtchn_pending);
1488 if (!masked)
1489 unmask_evtchn(evtchn);
1490
1491 return 1;
1492}
1493
c9e265e0 1494static void enable_dynirq(struct irq_data *data)
e46cdb66 1495{
c9e265e0 1496 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1497
1498 if (VALID_EVTCHN(evtchn))
1499 unmask_evtchn(evtchn);
1500}
1501
c9e265e0 1502static void disable_dynirq(struct irq_data *data)
e46cdb66 1503{
c9e265e0 1504 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1505
1506 if (VALID_EVTCHN(evtchn))
1507 mask_evtchn(evtchn);
1508}
1509
c9e265e0 1510static void ack_dynirq(struct irq_data *data)
e46cdb66 1511{
c9e265e0 1512 int evtchn = evtchn_from_irq(data->irq);
e46cdb66 1513
7e186bdd 1514 irq_move_irq(data);
e46cdb66
JF
1515
1516 if (VALID_EVTCHN(evtchn))
7e186bdd
SS
1517 clear_evtchn(evtchn);
1518}
1519
1520static void mask_ack_dynirq(struct irq_data *data)
1521{
1522 disable_dynirq(data);
1523 ack_dynirq(data);
e46cdb66
JF
1524}
1525
c9e265e0 1526static int retrigger_dynirq(struct irq_data *data)
e46cdb66 1527{
c9e265e0 1528 int evtchn = evtchn_from_irq(data->irq);
ee8fa1c6 1529 struct shared_info *sh = HYPERVISOR_shared_info;
e46cdb66
JF
1530 int ret = 0;
1531
1532 if (VALID_EVTCHN(evtchn)) {
ee8fa1c6
JF
1533 int masked;
1534
1535 masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask);
1536 sync_set_bit(evtchn, sh->evtchn_pending);
1537 if (!masked)
1538 unmask_evtchn(evtchn);
e46cdb66
JF
1539 ret = 1;
1540 }
1541
1542 return ret;
1543}
1544
0a85226f 1545static void restore_pirqs(void)
9a069c33
SS
1546{
1547 int pirq, rc, irq, gsi;
1548 struct physdev_map_pirq map_irq;
69c358ce 1549 struct irq_info *info;
9a069c33 1550
69c358ce
IC
1551 list_for_each_entry(info, &xen_irq_list_head, list) {
1552 if (info->type != IRQT_PIRQ)
9a069c33
SS
1553 continue;
1554
69c358ce
IC
1555 pirq = info->u.pirq.pirq;
1556 gsi = info->u.pirq.gsi;
1557 irq = info->irq;
1558
9a069c33
SS
1559 /* save/restore of PT devices doesn't work, so at this point the
1560 * only devices present are GSI based emulated devices */
9a069c33
SS
1561 if (!gsi)
1562 continue;
1563
1564 map_irq.domid = DOMID_SELF;
1565 map_irq.type = MAP_PIRQ_TYPE_GSI;
1566 map_irq.index = gsi;
1567 map_irq.pirq = pirq;
1568
1569 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
1570 if (rc) {
1571 printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
1572 gsi, irq, pirq, rc);
9158c358 1573 xen_free_irq(irq);
9a069c33
SS
1574 continue;
1575 }
1576
1577 printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
1578
c9e265e0 1579 __startup_pirq(irq);
9a069c33
SS
1580 }
1581}
1582
0e91398f
JF
1583static void restore_cpu_virqs(unsigned int cpu)
1584{
1585 struct evtchn_bind_virq bind_virq;
1586 int virq, irq, evtchn;
1587
1588 for (virq = 0; virq < NR_VIRQS; virq++) {
1589 if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
1590 continue;
1591
ced40d0f 1592 BUG_ON(virq_from_irq(irq) != virq);
0e91398f
JF
1593
1594 /* Get a new binding from Xen. */
1595 bind_virq.virq = virq;
1596 bind_virq.vcpu = cpu;
1597 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
1598 &bind_virq) != 0)
1599 BUG();
1600 evtchn = bind_virq.port;
1601
1602 /* Record the new mapping. */
3d4cfa37 1603 xen_irq_info_virq_init(cpu, irq, evtchn, virq);
0e91398f 1604 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1605 }
1606}
1607
1608static void restore_cpu_ipis(unsigned int cpu)
1609{
1610 struct evtchn_bind_ipi bind_ipi;
1611 int ipi, irq, evtchn;
1612
1613 for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
1614 if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
1615 continue;
1616
ced40d0f 1617 BUG_ON(ipi_from_irq(irq) != ipi);
0e91398f
JF
1618
1619 /* Get a new binding from Xen. */
1620 bind_ipi.vcpu = cpu;
1621 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
1622 &bind_ipi) != 0)
1623 BUG();
1624 evtchn = bind_ipi.port;
1625
1626 /* Record the new mapping. */
3d4cfa37 1627 xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
0e91398f 1628 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1629 }
1630}
1631
2d9e1e2f
JF
1632/* Clear an irq's pending state, in preparation for polling on it */
1633void xen_clear_irq_pending(int irq)
1634{
1635 int evtchn = evtchn_from_irq(irq);
1636
1637 if (VALID_EVTCHN(evtchn))
1638 clear_evtchn(evtchn);
1639}
d9a8814f 1640EXPORT_SYMBOL(xen_clear_irq_pending);
168d2f46
JF
1641void xen_set_irq_pending(int irq)
1642{
1643 int evtchn = evtchn_from_irq(irq);
1644
1645 if (VALID_EVTCHN(evtchn))
1646 set_evtchn(evtchn);
1647}
1648
1649bool xen_test_irq_pending(int irq)
1650{
1651 int evtchn = evtchn_from_irq(irq);
1652 bool ret = false;
1653
1654 if (VALID_EVTCHN(evtchn))
1655 ret = test_evtchn(evtchn);
1656
1657 return ret;
1658}
1659
d9a8814f
KRW
1660/* Poll waiting for an irq to become pending with timeout. In the usual case,
1661 * the irq will be disabled so it won't deliver an interrupt. */
1662void xen_poll_irq_timeout(int irq, u64 timeout)
2d9e1e2f
JF
1663{
1664 evtchn_port_t evtchn = evtchn_from_irq(irq);
1665
1666 if (VALID_EVTCHN(evtchn)) {
1667 struct sched_poll poll;
1668
1669 poll.nr_ports = 1;
d9a8814f 1670 poll.timeout = timeout;
ff3c5362 1671 set_xen_guest_handle(poll.ports, &evtchn);
2d9e1e2f
JF
1672
1673 if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
1674 BUG();
1675 }
1676}
d9a8814f
KRW
1677EXPORT_SYMBOL(xen_poll_irq_timeout);
1678/* Poll waiting for an irq to become pending. In the usual case, the
1679 * irq will be disabled so it won't deliver an interrupt. */
1680void xen_poll_irq(int irq)
1681{
1682 xen_poll_irq_timeout(irq, 0 /* no timeout */);
1683}
2d9e1e2f 1684
c7c2c3a2
KRW
1685/* Check whether the IRQ line is shared with other guests. */
1686int xen_test_irq_shared(int irq)
1687{
1688 struct irq_info *info = info_for_irq(irq);
1689 struct physdev_irq_status_query irq_status = { .irq = info->u.pirq.pirq };
1690
1691 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
1692 return 0;
1693 return !(irq_status.flags & XENIRQSTAT_shared);
1694}
1695EXPORT_SYMBOL_GPL(xen_test_irq_shared);
1696
0e91398f
JF
1697void xen_irq_resume(void)
1698{
6cb6537d
IC
1699 unsigned int cpu, evtchn;
1700 struct irq_info *info;
0e91398f
JF
1701
1702 init_evtchn_cpu_bindings();
1703
1704 /* New event-channel space is not 'live' yet. */
1705 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1706 mask_evtchn(evtchn);
1707
1708 /* No IRQ <-> event-channel mappings. */
6cb6537d
IC
1709 list_for_each_entry(info, &xen_irq_list_head, list)
1710 info->evtchn = 0; /* zap event-channel binding */
0e91398f
JF
1711
1712 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1713 evtchn_to_irq[evtchn] = -1;
1714
1715 for_each_possible_cpu(cpu) {
1716 restore_cpu_virqs(cpu);
1717 restore_cpu_ipis(cpu);
1718 }
6903591f 1719
0a85226f 1720 restore_pirqs();
0e91398f
JF
1721}
1722
e46cdb66 1723static struct irq_chip xen_dynamic_chip __read_mostly = {
c9e265e0 1724 .name = "xen-dyn",
54a353a0 1725
c9e265e0
TG
1726 .irq_disable = disable_dynirq,
1727 .irq_mask = disable_dynirq,
1728 .irq_unmask = enable_dynirq,
54a353a0 1729
7e186bdd
SS
1730 .irq_ack = ack_dynirq,
1731 .irq_mask_ack = mask_ack_dynirq,
1732
c9e265e0
TG
1733 .irq_set_affinity = set_affinity_irq,
1734 .irq_retrigger = retrigger_dynirq,
e46cdb66
JF
1735};
1736
d46a78b0 1737static struct irq_chip xen_pirq_chip __read_mostly = {
c9e265e0 1738 .name = "xen-pirq",
d46a78b0 1739
c9e265e0
TG
1740 .irq_startup = startup_pirq,
1741 .irq_shutdown = shutdown_pirq,
c9e265e0 1742 .irq_enable = enable_pirq,
c9e265e0 1743 .irq_disable = disable_pirq,
d46a78b0 1744
7e186bdd
SS
1745 .irq_mask = disable_dynirq,
1746 .irq_unmask = enable_dynirq,
1747
1748 .irq_ack = eoi_pirq,
1749 .irq_eoi = eoi_pirq,
1750 .irq_mask_ack = mask_ack_pirq,
d46a78b0 1751
c9e265e0 1752 .irq_set_affinity = set_affinity_irq,
d46a78b0 1753
c9e265e0 1754 .irq_retrigger = retrigger_dynirq,
d46a78b0
JF
1755};
1756
aaca4964 1757static struct irq_chip xen_percpu_chip __read_mostly = {
c9e265e0 1758 .name = "xen-percpu",
aaca4964 1759
c9e265e0
TG
1760 .irq_disable = disable_dynirq,
1761 .irq_mask = disable_dynirq,
1762 .irq_unmask = enable_dynirq,
aaca4964 1763
c9e265e0 1764 .irq_ack = ack_dynirq,
aaca4964
JF
1765};
1766
38e20b07
SY
1767int xen_set_callback_via(uint64_t via)
1768{
1769 struct xen_hvm_param a;
1770 a.domid = DOMID_SELF;
1771 a.index = HVM_PARAM_CALLBACK_IRQ;
1772 a.value = via;
1773 return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
1774}
1775EXPORT_SYMBOL_GPL(xen_set_callback_via);
1776
ca65f9fc 1777#ifdef CONFIG_XEN_PVHVM
38e20b07
SY
1778/* Vector callbacks are better than PCI interrupts to receive event
1779 * channel notifications because we can receive vector callbacks on any
1780 * vcpu and we don't need PCI support or APIC interactions. */
1781void xen_callback_vector(void)
1782{
1783 int rc;
1784 uint64_t callback_via;
1785 if (xen_have_vector_callback) {
1786 callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK);
1787 rc = xen_set_callback_via(callback_via);
1788 if (rc) {
1789 printk(KERN_ERR "Request for Xen HVM callback vector"
1790 " failed.\n");
1791 xen_have_vector_callback = 0;
1792 return;
1793 }
1794 printk(KERN_INFO "Xen HVM callback vector for event delivery is "
1795 "enabled\n");
1796 /* in the restore case the vector has already been allocated */
1797 if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors))
1798 alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector);
1799 }
1800}
ca65f9fc
SS
1801#else
1802void xen_callback_vector(void) {}
1803#endif
38e20b07 1804
2e3d8860 1805void __init xen_init_IRQ(void)
e46cdb66 1806{
0ec53ecf 1807 int i;
c7a3589e 1808
b21ddbf5
JF
1809 evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
1810 GFP_KERNEL);
9d093e29 1811 BUG_ON(!evtchn_to_irq);
b21ddbf5
JF
1812 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1813 evtchn_to_irq[i] = -1;
e46cdb66
JF
1814
1815 init_evtchn_cpu_bindings();
1816
1817 /* No event channels are 'live' right now. */
1818 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1819 mask_evtchn(i);
1820
9846ff10
SS
1821 pirq_needs_eoi = pirq_needs_eoi_flag;
1822
0ec53ecf 1823#ifdef CONFIG_X86
38e20b07
SY
1824 if (xen_hvm_domain()) {
1825 xen_callback_vector();
1826 native_init_IRQ();
3942b740
SS
1827 /* pci_xen_hvm_init must be called after native_init_IRQ so that
1828 * __acpi_register_gsi can point at the right function */
1829 pci_xen_hvm_init();
38e20b07 1830 } else {
0ec53ecf 1831 int rc;
9846ff10
SS
1832 struct physdev_pirq_eoi_gmfn eoi_gmfn;
1833
38e20b07 1834 irq_ctx_init(smp_processor_id());
38aa66fc 1835 if (xen_initial_domain())
a0ee0567 1836 pci_xen_initial_domain();
9846ff10
SS
1837
1838 pirq_eoi_map = (void *)__get_free_page(GFP_KERNEL|__GFP_ZERO);
1839 eoi_gmfn.gmfn = virt_to_mfn(pirq_eoi_map);
1840 rc = HYPERVISOR_physdev_op(PHYSDEVOP_pirq_eoi_gmfn_v2, &eoi_gmfn);
1841 if (rc != 0) {
1842 free_page((unsigned long) pirq_eoi_map);
1843 pirq_eoi_map = NULL;
1844 } else
1845 pirq_needs_eoi = pirq_check_eoi_map;
38e20b07 1846 }
0ec53ecf 1847#endif
e46cdb66 1848}
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