Merge tag 'mfd-3.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6
[deliverable/linux.git] / drivers / xen / events.c
CommitLineData
e46cdb66
JF
1/*
2 * Xen event channels
3 *
4 * Xen models interrupts with abstract event channels. Because each
5 * domain gets 1024 event channels, but NR_IRQ is not that large, we
6 * must dynamically map irqs<->event channels. The event channels
7 * interface with the rest of the kernel by defining a xen interrupt
25985edc 8 * chip. When an event is received, it is mapped to an irq and sent
e46cdb66
JF
9 * through the normal interrupt processing path.
10 *
11 * There are four kinds of events which can be mapped to an event
12 * channel:
13 *
14 * 1. Inter-domain notifications. This includes all the virtual
15 * device events, since they're driven by front-ends in another domain
16 * (typically dom0).
17 * 2. VIRQs, typically used for timers. These are per-cpu events.
18 * 3. IPIs.
d46a78b0 19 * 4. PIRQs - Hardware interrupts.
e46cdb66
JF
20 *
21 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
22 */
23
24#include <linux/linkage.h>
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/module.h>
28#include <linux/string.h>
28e08861 29#include <linux/bootmem.h>
5a0e3ad6 30#include <linux/slab.h>
b21ddbf5 31#include <linux/irqnr.h>
f731e3ef 32#include <linux/pci.h>
e46cdb66 33
38e20b07 34#include <asm/desc.h>
e46cdb66
JF
35#include <asm/ptrace.h>
36#include <asm/irq.h>
792dc4f6 37#include <asm/idle.h>
0794bfc7 38#include <asm/io_apic.h>
e46cdb66 39#include <asm/sync_bitops.h>
9846ff10 40#include <asm/xen/page.h>
42a1de56 41#include <asm/xen/pci.h>
e46cdb66 42#include <asm/xen/hypercall.h>
8d1b8753 43#include <asm/xen/hypervisor.h>
e46cdb66 44
38e20b07
SY
45#include <xen/xen.h>
46#include <xen/hvm.h>
e04d0d07 47#include <xen/xen-ops.h>
e46cdb66
JF
48#include <xen/events.h>
49#include <xen/interface/xen.h>
50#include <xen/interface/event_channel.h>
38e20b07
SY
51#include <xen/interface/hvm/hvm_op.h>
52#include <xen/interface/hvm/params.h>
e46cdb66 53
e46cdb66
JF
54/*
55 * This lock protects updates to the following mapping and reference-count
56 * arrays. The lock does not need to be acquired to read the mapping tables.
57 */
77365948 58static DEFINE_MUTEX(irq_mapping_update_lock);
e46cdb66 59
6cb6537d
IC
60static LIST_HEAD(xen_irq_list_head);
61
e46cdb66 62/* IRQ <-> VIRQ mapping. */
204fba4a 63static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
e46cdb66 64
f87e4cac 65/* IRQ <-> IPI mapping */
204fba4a 66static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
f87e4cac 67
ced40d0f
JF
68/* Interrupt types. */
69enum xen_irq_type {
d77bbd4d 70 IRQT_UNBOUND = 0,
f87e4cac
JF
71 IRQT_PIRQ,
72 IRQT_VIRQ,
73 IRQT_IPI,
74 IRQT_EVTCHN
75};
e46cdb66 76
ced40d0f
JF
77/*
78 * Packed IRQ information:
79 * type - enum xen_irq_type
80 * event channel - irq->event channel mapping
81 * cpu - cpu this event channel is bound to
82 * index - type-specific information:
42a1de56
SS
83 * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM
84 * guest, or GSI (real passthrough IRQ) of the device.
ced40d0f
JF
85 * VIRQ - virq number
86 * IPI - IPI vector
87 * EVTCHN -
88 */
088c05a8 89struct irq_info {
6cb6537d 90 struct list_head list;
420eb554 91 int refcnt;
ced40d0f 92 enum xen_irq_type type; /* type */
6cb6537d 93 unsigned irq;
ced40d0f
JF
94 unsigned short evtchn; /* event channel */
95 unsigned short cpu; /* cpu bound */
96
97 union {
98 unsigned short virq;
99 enum ipi_vector ipi;
100 struct {
7a043f11 101 unsigned short pirq;
ced40d0f 102 unsigned short gsi;
d46a78b0
JF
103 unsigned char vector;
104 unsigned char flags;
beafbdc1 105 uint16_t domid;
ced40d0f
JF
106 } pirq;
107 } u;
108};
d46a78b0 109#define PIRQ_NEEDS_EOI (1 << 0)
15ebbb82 110#define PIRQ_SHAREABLE (1 << 1)
ced40d0f 111
b21ddbf5 112static int *evtchn_to_irq;
9846ff10
SS
113static unsigned long *pirq_eoi_map;
114static bool (*pirq_needs_eoi)(unsigned irq);
3b32f574 115
cb60d114
IC
116static DEFINE_PER_CPU(unsigned long [NR_EVENT_CHANNELS/BITS_PER_LONG],
117 cpu_evtchn_mask);
e46cdb66 118
e46cdb66
JF
119/* Xen will never allocate port zero for any purpose. */
120#define VALID_EVTCHN(chn) ((chn) != 0)
121
e46cdb66 122static struct irq_chip xen_dynamic_chip;
aaca4964 123static struct irq_chip xen_percpu_chip;
d46a78b0 124static struct irq_chip xen_pirq_chip;
7e186bdd
SS
125static void enable_dynirq(struct irq_data *data);
126static void disable_dynirq(struct irq_data *data);
e46cdb66 127
9158c358
IC
128/* Get info for IRQ */
129static struct irq_info *info_for_irq(unsigned irq)
ced40d0f 130{
c442b806 131 return irq_get_handler_data(irq);
ced40d0f
JF
132}
133
9158c358
IC
134/* Constructors for packed IRQ information. */
135static void xen_irq_info_common_init(struct irq_info *info,
3d4cfa37 136 unsigned irq,
9158c358
IC
137 enum xen_irq_type type,
138 unsigned short evtchn,
139 unsigned short cpu)
ced40d0f 140{
9158c358
IC
141
142 BUG_ON(info->type != IRQT_UNBOUND && info->type != type);
143
144 info->type = type;
6cb6537d 145 info->irq = irq;
9158c358
IC
146 info->evtchn = evtchn;
147 info->cpu = cpu;
3d4cfa37
IC
148
149 evtchn_to_irq[evtchn] = irq;
ced40d0f
JF
150}
151
9158c358
IC
152static void xen_irq_info_evtchn_init(unsigned irq,
153 unsigned short evtchn)
ced40d0f 154{
9158c358
IC
155 struct irq_info *info = info_for_irq(irq);
156
3d4cfa37 157 xen_irq_info_common_init(info, irq, IRQT_EVTCHN, evtchn, 0);
ced40d0f
JF
158}
159
3d4cfa37
IC
160static void xen_irq_info_ipi_init(unsigned cpu,
161 unsigned irq,
9158c358
IC
162 unsigned short evtchn,
163 enum ipi_vector ipi)
e46cdb66 164{
9158c358
IC
165 struct irq_info *info = info_for_irq(irq);
166
3d4cfa37 167 xen_irq_info_common_init(info, irq, IRQT_IPI, evtchn, 0);
9158c358
IC
168
169 info->u.ipi = ipi;
3d4cfa37
IC
170
171 per_cpu(ipi_to_irq, cpu)[ipi] = irq;
ced40d0f
JF
172}
173
3d4cfa37
IC
174static void xen_irq_info_virq_init(unsigned cpu,
175 unsigned irq,
9158c358
IC
176 unsigned short evtchn,
177 unsigned short virq)
ced40d0f 178{
9158c358
IC
179 struct irq_info *info = info_for_irq(irq);
180
3d4cfa37 181 xen_irq_info_common_init(info, irq, IRQT_VIRQ, evtchn, 0);
9158c358
IC
182
183 info->u.virq = virq;
3d4cfa37
IC
184
185 per_cpu(virq_to_irq, cpu)[virq] = irq;
ced40d0f
JF
186}
187
9158c358
IC
188static void xen_irq_info_pirq_init(unsigned irq,
189 unsigned short evtchn,
190 unsigned short pirq,
191 unsigned short gsi,
192 unsigned short vector,
beafbdc1 193 uint16_t domid,
9158c358 194 unsigned char flags)
ced40d0f 195{
9158c358
IC
196 struct irq_info *info = info_for_irq(irq);
197
3d4cfa37 198 xen_irq_info_common_init(info, irq, IRQT_PIRQ, evtchn, 0);
9158c358
IC
199
200 info->u.pirq.pirq = pirq;
201 info->u.pirq.gsi = gsi;
202 info->u.pirq.vector = vector;
beafbdc1 203 info->u.pirq.domid = domid;
9158c358 204 info->u.pirq.flags = flags;
e46cdb66
JF
205}
206
207/*
208 * Accessors for packed IRQ information.
209 */
ced40d0f 210static unsigned int evtchn_from_irq(unsigned irq)
e46cdb66 211{
110e7c7e
JJ
212 if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
213 return 0;
214
ced40d0f 215 return info_for_irq(irq)->evtchn;
e46cdb66
JF
216}
217
d4c04536
IC
218unsigned irq_from_evtchn(unsigned int evtchn)
219{
220 return evtchn_to_irq[evtchn];
221}
222EXPORT_SYMBOL_GPL(irq_from_evtchn);
223
ced40d0f 224static enum ipi_vector ipi_from_irq(unsigned irq)
e46cdb66 225{
ced40d0f
JF
226 struct irq_info *info = info_for_irq(irq);
227
228 BUG_ON(info == NULL);
229 BUG_ON(info->type != IRQT_IPI);
230
231 return info->u.ipi;
232}
233
234static unsigned virq_from_irq(unsigned irq)
235{
236 struct irq_info *info = info_for_irq(irq);
237
238 BUG_ON(info == NULL);
239 BUG_ON(info->type != IRQT_VIRQ);
240
241 return info->u.virq;
242}
243
7a043f11
SS
244static unsigned pirq_from_irq(unsigned irq)
245{
246 struct irq_info *info = info_for_irq(irq);
247
248 BUG_ON(info == NULL);
249 BUG_ON(info->type != IRQT_PIRQ);
250
251 return info->u.pirq.pirq;
252}
253
ced40d0f
JF
254static enum xen_irq_type type_from_irq(unsigned irq)
255{
256 return info_for_irq(irq)->type;
257}
258
259static unsigned cpu_from_irq(unsigned irq)
260{
261 return info_for_irq(irq)->cpu;
262}
263
264static unsigned int cpu_from_evtchn(unsigned int evtchn)
265{
266 int irq = evtchn_to_irq[evtchn];
267 unsigned ret = 0;
268
269 if (irq != -1)
270 ret = cpu_from_irq(irq);
271
272 return ret;
e46cdb66
JF
273}
274
9846ff10 275static bool pirq_check_eoi_map(unsigned irq)
d46a78b0 276{
521394e4 277 return test_bit(pirq_from_irq(irq), pirq_eoi_map);
9846ff10 278}
d46a78b0 279
9846ff10
SS
280static bool pirq_needs_eoi_flag(unsigned irq)
281{
282 struct irq_info *info = info_for_irq(irq);
d46a78b0
JF
283 BUG_ON(info->type != IRQT_PIRQ);
284
285 return info->u.pirq.flags & PIRQ_NEEDS_EOI;
286}
287
e46cdb66
JF
288static inline unsigned long active_evtchns(unsigned int cpu,
289 struct shared_info *sh,
290 unsigned int idx)
291{
088c05a8 292 return sh->evtchn_pending[idx] &
cb60d114 293 per_cpu(cpu_evtchn_mask, cpu)[idx] &
088c05a8 294 ~sh->evtchn_mask[idx];
e46cdb66
JF
295}
296
297static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
298{
299 int irq = evtchn_to_irq[chn];
300
301 BUG_ON(irq == -1);
302#ifdef CONFIG_SMP
c9e265e0 303 cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu));
e46cdb66
JF
304#endif
305
cb60d114
IC
306 clear_bit(chn, per_cpu(cpu_evtchn_mask, cpu_from_irq(irq)));
307 set_bit(chn, per_cpu(cpu_evtchn_mask, cpu));
e46cdb66 308
ca62ce8c 309 info_for_irq(irq)->cpu = cpu;
e46cdb66
JF
310}
311
312static void init_evtchn_cpu_bindings(void)
313{
1c6969ec 314 int i;
e46cdb66 315#ifdef CONFIG_SMP
6cb6537d 316 struct irq_info *info;
10e58084 317
e46cdb66 318 /* By default all event channels notify CPU#0. */
6cb6537d
IC
319 list_for_each_entry(info, &xen_irq_list_head, list) {
320 struct irq_desc *desc = irq_to_desc(info->irq);
c9e265e0 321 cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
0b8f1efa 322 }
e46cdb66
JF
323#endif
324
1c6969ec 325 for_each_possible_cpu(i)
cb60d114
IC
326 memset(per_cpu(cpu_evtchn_mask, i),
327 (i == 0) ? ~0 : 0, sizeof(*per_cpu(cpu_evtchn_mask, i)));
e46cdb66
JF
328}
329
e46cdb66
JF
330static inline void clear_evtchn(int port)
331{
332 struct shared_info *s = HYPERVISOR_shared_info;
333 sync_clear_bit(port, &s->evtchn_pending[0]);
334}
335
336static inline void set_evtchn(int port)
337{
338 struct shared_info *s = HYPERVISOR_shared_info;
339 sync_set_bit(port, &s->evtchn_pending[0]);
340}
341
168d2f46
JF
342static inline int test_evtchn(int port)
343{
344 struct shared_info *s = HYPERVISOR_shared_info;
345 return sync_test_bit(port, &s->evtchn_pending[0]);
346}
347
e46cdb66
JF
348
349/**
350 * notify_remote_via_irq - send event to remote end of event channel via irq
351 * @irq: irq of event channel to send event to
352 *
353 * Unlike notify_remote_via_evtchn(), this is safe to use across
354 * save/restore. Notifications on a broken connection are silently
355 * dropped.
356 */
357void notify_remote_via_irq(int irq)
358{
359 int evtchn = evtchn_from_irq(irq);
360
361 if (VALID_EVTCHN(evtchn))
362 notify_remote_via_evtchn(evtchn);
363}
364EXPORT_SYMBOL_GPL(notify_remote_via_irq);
365
366static void mask_evtchn(int port)
367{
368 struct shared_info *s = HYPERVISOR_shared_info;
369 sync_set_bit(port, &s->evtchn_mask[0]);
370}
371
372static void unmask_evtchn(int port)
373{
374 struct shared_info *s = HYPERVISOR_shared_info;
375 unsigned int cpu = get_cpu();
376
377 BUG_ON(!irqs_disabled());
378
379 /* Slow path (hypercall) if this is a non-local port. */
380 if (unlikely(cpu != cpu_from_evtchn(port))) {
381 struct evtchn_unmask unmask = { .port = port };
382 (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
383 } else {
780f36d8 384 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
e46cdb66
JF
385
386 sync_clear_bit(port, &s->evtchn_mask[0]);
387
388 /*
389 * The following is basically the equivalent of
390 * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
391 * the interrupt edge' if the channel is masked.
392 */
393 if (sync_test_bit(port, &s->evtchn_pending[0]) &&
394 !sync_test_and_set_bit(port / BITS_PER_LONG,
395 &vcpu_info->evtchn_pending_sel))
396 vcpu_info->evtchn_upcall_pending = 1;
397 }
398
399 put_cpu();
400}
401
6cb6537d
IC
402static void xen_irq_init(unsigned irq)
403{
404 struct irq_info *info;
b5328cd1 405#ifdef CONFIG_SMP
6cb6537d
IC
406 struct irq_desc *desc = irq_to_desc(irq);
407
408 /* By default all event channels notify CPU#0. */
409 cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
44626e4a 410#endif
6cb6537d 411
ca62ce8c
IC
412 info = kzalloc(sizeof(*info), GFP_KERNEL);
413 if (info == NULL)
414 panic("Unable to allocate metadata for IRQ%d\n", irq);
6cb6537d
IC
415
416 info->type = IRQT_UNBOUND;
420eb554 417 info->refcnt = -1;
6cb6537d 418
c442b806 419 irq_set_handler_data(irq, info);
ca62ce8c 420
6cb6537d
IC
421 list_add_tail(&info->list, &xen_irq_list_head);
422}
423
7bee9768 424static int __must_check xen_allocate_irq_dynamic(void)
0794bfc7 425{
89911501
IC
426 int first = 0;
427 int irq;
0794bfc7
KRW
428
429#ifdef CONFIG_X86_IO_APIC
89911501
IC
430 /*
431 * For an HVM guest or domain 0 which see "real" (emulated or
25985edc 432 * actual respectively) GSIs we allocate dynamic IRQs
89911501
IC
433 * e.g. those corresponding to event channels or MSIs
434 * etc. from the range above those "real" GSIs to avoid
435 * collisions.
436 */
437 if (xen_initial_domain() || xen_hvm_domain())
438 first = get_nr_irqs_gsi();
0794bfc7
KRW
439#endif
440
89911501 441 irq = irq_alloc_desc_from(first, -1);
3a69e916 442
e6599225
KRW
443 if (irq >= 0)
444 xen_irq_init(irq);
ced40d0f 445
e46cdb66 446 return irq;
d46a78b0
JF
447}
448
7bee9768 449static int __must_check xen_allocate_irq_gsi(unsigned gsi)
c9df1ce5
IC
450{
451 int irq;
452
89911501
IC
453 /*
454 * A PV guest has no concept of a GSI (since it has no ACPI
455 * nor access to/knowledge of the physical APICs). Therefore
456 * all IRQs are dynamically allocated from the entire IRQ
457 * space.
458 */
459 if (xen_pv_domain() && !xen_initial_domain())
c9df1ce5
IC
460 return xen_allocate_irq_dynamic();
461
462 /* Legacy IRQ descriptors are already allocated by the arch. */
463 if (gsi < NR_IRQS_LEGACY)
6cb6537d
IC
464 irq = gsi;
465 else
466 irq = irq_alloc_desc_at(gsi, -1);
c9df1ce5 467
6cb6537d 468 xen_irq_init(irq);
c9df1ce5
IC
469
470 return irq;
471}
472
473static void xen_free_irq(unsigned irq)
474{
c442b806 475 struct irq_info *info = irq_get_handler_data(irq);
6cb6537d
IC
476
477 list_del(&info->list);
9158c358 478
c442b806 479 irq_set_handler_data(irq, NULL);
ca62ce8c 480
420eb554
DDG
481 WARN_ON(info->refcnt > 0);
482
ca62ce8c
IC
483 kfree(info);
484
72146104
IC
485 /* Legacy IRQ descriptors are managed by the arch. */
486 if (irq < NR_IRQS_LEGACY)
487 return;
488
c9df1ce5
IC
489 irq_free_desc(irq);
490}
491
d46a78b0
JF
492static void pirq_query_unmask(int irq)
493{
494 struct physdev_irq_status_query irq_status;
495 struct irq_info *info = info_for_irq(irq);
496
497 BUG_ON(info->type != IRQT_PIRQ);
498
7a043f11 499 irq_status.irq = pirq_from_irq(irq);
d46a78b0
JF
500 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
501 irq_status.flags = 0;
502
503 info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
504 if (irq_status.flags & XENIRQSTAT_needs_eoi)
505 info->u.pirq.flags |= PIRQ_NEEDS_EOI;
506}
507
508static bool probing_irq(int irq)
509{
510 struct irq_desc *desc = irq_to_desc(irq);
511
512 return desc && desc->action == NULL;
513}
514
7e186bdd
SS
515static void eoi_pirq(struct irq_data *data)
516{
517 int evtchn = evtchn_from_irq(data->irq);
518 struct physdev_eoi eoi = { .irq = pirq_from_irq(data->irq) };
519 int rc = 0;
520
521 irq_move_irq(data);
522
523 if (VALID_EVTCHN(evtchn))
524 clear_evtchn(evtchn);
525
526 if (pirq_needs_eoi(data->irq)) {
527 rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
528 WARN_ON(rc);
529 }
530}
531
532static void mask_ack_pirq(struct irq_data *data)
533{
534 disable_dynirq(data);
535 eoi_pirq(data);
536}
537
c9e265e0 538static unsigned int __startup_pirq(unsigned int irq)
d46a78b0
JF
539{
540 struct evtchn_bind_pirq bind_pirq;
541 struct irq_info *info = info_for_irq(irq);
542 int evtchn = evtchn_from_irq(irq);
15ebbb82 543 int rc;
d46a78b0
JF
544
545 BUG_ON(info->type != IRQT_PIRQ);
546
547 if (VALID_EVTCHN(evtchn))
548 goto out;
549
7a043f11 550 bind_pirq.pirq = pirq_from_irq(irq);
d46a78b0 551 /* NB. We are happy to share unless we are probing. */
15ebbb82
KRW
552 bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
553 BIND_PIRQ__WILL_SHARE : 0;
554 rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
555 if (rc != 0) {
d46a78b0
JF
556 if (!probing_irq(irq))
557 printk(KERN_INFO "Failed to obtain physical IRQ %d\n",
558 irq);
559 return 0;
560 }
561 evtchn = bind_pirq.port;
562
563 pirq_query_unmask(irq);
564
565 evtchn_to_irq[evtchn] = irq;
566 bind_evtchn_to_cpu(evtchn, 0);
567 info->evtchn = evtchn;
568
569out:
570 unmask_evtchn(evtchn);
7e186bdd 571 eoi_pirq(irq_get_irq_data(irq));
d46a78b0
JF
572
573 return 0;
574}
575
c9e265e0
TG
576static unsigned int startup_pirq(struct irq_data *data)
577{
578 return __startup_pirq(data->irq);
579}
580
581static void shutdown_pirq(struct irq_data *data)
d46a78b0
JF
582{
583 struct evtchn_close close;
c9e265e0 584 unsigned int irq = data->irq;
d46a78b0
JF
585 struct irq_info *info = info_for_irq(irq);
586 int evtchn = evtchn_from_irq(irq);
587
588 BUG_ON(info->type != IRQT_PIRQ);
589
590 if (!VALID_EVTCHN(evtchn))
591 return;
592
593 mask_evtchn(evtchn);
594
595 close.port = evtchn;
596 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
597 BUG();
598
599 bind_evtchn_to_cpu(evtchn, 0);
600 evtchn_to_irq[evtchn] = -1;
601 info->evtchn = 0;
602}
603
c9e265e0 604static void enable_pirq(struct irq_data *data)
d46a78b0 605{
c9e265e0 606 startup_pirq(data);
d46a78b0
JF
607}
608
c9e265e0 609static void disable_pirq(struct irq_data *data)
d46a78b0 610{
7e186bdd 611 disable_dynirq(data);
d46a78b0
JF
612}
613
68c2c39a 614int xen_irq_from_gsi(unsigned gsi)
d46a78b0 615{
6cb6537d 616 struct irq_info *info;
d46a78b0 617
6cb6537d
IC
618 list_for_each_entry(info, &xen_irq_list_head, list) {
619 if (info->type != IRQT_PIRQ)
d46a78b0
JF
620 continue;
621
6cb6537d
IC
622 if (info->u.pirq.gsi == gsi)
623 return info->irq;
d46a78b0
JF
624 }
625
626 return -1;
627}
68c2c39a 628EXPORT_SYMBOL_GPL(xen_irq_from_gsi);
d46a78b0 629
653378ac
IC
630/*
631 * Do not make any assumptions regarding the relationship between the
632 * IRQ number returned here and the Xen pirq argument.
7a043f11
SS
633 *
634 * Note: We don't assign an event channel until the irq actually started
635 * up. Return an existing irq if we've already got one for the gsi.
e5ac0bda
SS
636 *
637 * Shareable implies level triggered, not shareable implies edge
638 * triggered here.
d46a78b0 639 */
f4d0635b
IC
640int xen_bind_pirq_gsi_to_irq(unsigned gsi,
641 unsigned pirq, int shareable, char *name)
d46a78b0 642{
a0e18116 643 int irq = -1;
d46a78b0
JF
644 struct physdev_irq irq_op;
645
77365948 646 mutex_lock(&irq_mapping_update_lock);
d46a78b0 647
68c2c39a 648 irq = xen_irq_from_gsi(gsi);
d46a78b0 649 if (irq != -1) {
7a043f11 650 printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n",
d46a78b0 651 irq, gsi);
420eb554 652 goto out;
d46a78b0
JF
653 }
654
c9df1ce5 655 irq = xen_allocate_irq_gsi(gsi);
7bee9768
IC
656 if (irq < 0)
657 goto out;
d46a78b0 658
d46a78b0 659 irq_op.irq = irq;
b5401a96
AN
660 irq_op.vector = 0;
661
662 /* Only the privileged domain can do this. For non-priv, the pcifront
663 * driver provides a PCI bus that does the call to do exactly
664 * this in the priv domain. */
665 if (xen_initial_domain() &&
666 HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
c9df1ce5 667 xen_free_irq(irq);
d46a78b0
JF
668 irq = -ENOSPC;
669 goto out;
670 }
671
beafbdc1 672 xen_irq_info_pirq_init(irq, 0, pirq, gsi, irq_op.vector, DOMID_SELF,
9158c358 673 shareable ? PIRQ_SHAREABLE : 0);
d46a78b0 674
7e186bdd
SS
675 pirq_query_unmask(irq);
676 /* We try to use the handler with the appropriate semantic for the
e5ac0bda
SS
677 * type of interrupt: if the interrupt is an edge triggered
678 * interrupt we use handle_edge_irq.
7e186bdd 679 *
e5ac0bda
SS
680 * On the other hand if the interrupt is level triggered we use
681 * handle_fasteoi_irq like the native code does for this kind of
7e186bdd 682 * interrupts.
e5ac0bda 683 *
7e186bdd
SS
684 * Depending on the Xen version, pirq_needs_eoi might return true
685 * not only for level triggered interrupts but for edge triggered
686 * interrupts too. In any case Xen always honors the eoi mechanism,
687 * not injecting any more pirqs of the same kind if the first one
688 * hasn't received an eoi yet. Therefore using the fasteoi handler
689 * is the right choice either way.
690 */
e5ac0bda 691 if (shareable)
7e186bdd
SS
692 irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
693 handle_fasteoi_irq, name);
694 else
695 irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
696 handle_edge_irq, name);
697
d46a78b0 698out:
77365948 699 mutex_unlock(&irq_mapping_update_lock);
d46a78b0
JF
700
701 return irq;
702}
703
f731e3ef 704#ifdef CONFIG_PCI_MSI
bf480d95 705int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc)
cbf6aa89 706{
5cad61a6 707 int rc;
cbf6aa89 708 struct physdev_get_free_pirq op_get_free_pirq;
cbf6aa89 709
bf480d95 710 op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI;
cbf6aa89 711 rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
cbf6aa89 712
5cad61a6
IC
713 WARN_ONCE(rc == -ENOSYS,
714 "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n");
715
716 return rc ? -1 : op_get_free_pirq.pirq;
cbf6aa89
IC
717}
718
bf480d95 719int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc,
beafbdc1
KRW
720 int pirq, int vector, const char *name,
721 domid_t domid)
809f9267 722{
bf480d95 723 int irq, ret;
4b41df7f 724
77365948 725 mutex_lock(&irq_mapping_update_lock);
809f9267 726
4b41df7f 727 irq = xen_allocate_irq_dynamic();
e6599225 728 if (irq < 0)
bb5d079a 729 goto out;
809f9267 730
7e186bdd
SS
731 irq_set_chip_and_handler_name(irq, &xen_pirq_chip, handle_edge_irq,
732 name);
809f9267 733
beafbdc1 734 xen_irq_info_pirq_init(irq, 0, pirq, 0, vector, domid, 0);
5f6fb454 735 ret = irq_set_msi_desc(irq, msidesc);
bf480d95
IC
736 if (ret < 0)
737 goto error_irq;
809f9267 738out:
77365948 739 mutex_unlock(&irq_mapping_update_lock);
4b41df7f 740 return irq;
bf480d95 741error_irq:
77365948 742 mutex_unlock(&irq_mapping_update_lock);
bf480d95 743 xen_free_irq(irq);
e6599225 744 return ret;
809f9267 745}
f731e3ef
QH
746#endif
747
b5401a96
AN
748int xen_destroy_irq(int irq)
749{
750 struct irq_desc *desc;
38aa66fc
JF
751 struct physdev_unmap_pirq unmap_irq;
752 struct irq_info *info = info_for_irq(irq);
b5401a96
AN
753 int rc = -ENOENT;
754
77365948 755 mutex_lock(&irq_mapping_update_lock);
b5401a96
AN
756
757 desc = irq_to_desc(irq);
758 if (!desc)
759 goto out;
760
38aa66fc 761 if (xen_initial_domain()) {
12334715 762 unmap_irq.pirq = info->u.pirq.pirq;
beafbdc1 763 unmap_irq.domid = info->u.pirq.domid;
38aa66fc 764 rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
1eff1ad0
KRW
765 /* If another domain quits without making the pci_disable_msix
766 * call, the Xen hypervisor takes care of freeing the PIRQs
767 * (free_domain_pirqs).
768 */
769 if ((rc == -ESRCH && info->u.pirq.domid != DOMID_SELF))
770 printk(KERN_INFO "domain %d does not have %d anymore\n",
771 info->u.pirq.domid, info->u.pirq.pirq);
772 else if (rc) {
38aa66fc
JF
773 printk(KERN_WARNING "unmap irq failed %d\n", rc);
774 goto out;
775 }
776 }
b5401a96 777
c9df1ce5 778 xen_free_irq(irq);
b5401a96
AN
779
780out:
77365948 781 mutex_unlock(&irq_mapping_update_lock);
b5401a96
AN
782 return rc;
783}
784
af42b8d1 785int xen_irq_from_pirq(unsigned pirq)
d46a78b0 786{
69c358ce 787 int irq;
d46a78b0 788
69c358ce 789 struct irq_info *info;
e46cdb66 790
77365948 791 mutex_lock(&irq_mapping_update_lock);
69c358ce
IC
792
793 list_for_each_entry(info, &xen_irq_list_head, list) {
9bb9efe4 794 if (info->type != IRQT_PIRQ)
69c358ce
IC
795 continue;
796 irq = info->irq;
797 if (info->u.pirq.pirq == pirq)
798 goto out;
799 }
800 irq = -1;
801out:
77365948 802 mutex_unlock(&irq_mapping_update_lock);
69c358ce
IC
803
804 return irq;
af42b8d1
SS
805}
806
e6197acc
KRW
807
808int xen_pirq_from_irq(unsigned irq)
809{
810 return pirq_from_irq(irq);
811}
812EXPORT_SYMBOL_GPL(xen_pirq_from_irq);
b536b4b9 813int bind_evtchn_to_irq(unsigned int evtchn)
e46cdb66
JF
814{
815 int irq;
816
77365948 817 mutex_lock(&irq_mapping_update_lock);
e46cdb66
JF
818
819 irq = evtchn_to_irq[evtchn];
820
821 if (irq == -1) {
c9df1ce5 822 irq = xen_allocate_irq_dynamic();
7bee9768
IC
823 if (irq == -1)
824 goto out;
e46cdb66 825
c442b806 826 irq_set_chip_and_handler_name(irq, &xen_dynamic_chip,
7e186bdd 827 handle_edge_irq, "event");
e46cdb66 828
9158c358 829 xen_irq_info_evtchn_init(irq, evtchn);
e46cdb66
JF
830 }
831
7bee9768 832out:
77365948 833 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
834
835 return irq;
836}
b536b4b9 837EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
e46cdb66 838
f87e4cac
JF
839static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
840{
841 struct evtchn_bind_ipi bind_ipi;
842 int evtchn, irq;
843
77365948 844 mutex_lock(&irq_mapping_update_lock);
f87e4cac
JF
845
846 irq = per_cpu(ipi_to_irq, cpu)[ipi];
90af9514 847
f87e4cac 848 if (irq == -1) {
c9df1ce5 849 irq = xen_allocate_irq_dynamic();
f87e4cac
JF
850 if (irq < 0)
851 goto out;
852
c442b806 853 irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
aaca4964 854 handle_percpu_irq, "ipi");
f87e4cac
JF
855
856 bind_ipi.vcpu = cpu;
857 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
858 &bind_ipi) != 0)
859 BUG();
860 evtchn = bind_ipi.port;
861
3d4cfa37 862 xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
f87e4cac
JF
863
864 bind_evtchn_to_cpu(evtchn, cpu);
865 }
866
f87e4cac 867 out:
77365948 868 mutex_unlock(&irq_mapping_update_lock);
f87e4cac
JF
869 return irq;
870}
871
2e820f58
IC
872static int bind_interdomain_evtchn_to_irq(unsigned int remote_domain,
873 unsigned int remote_port)
874{
875 struct evtchn_bind_interdomain bind_interdomain;
876 int err;
877
878 bind_interdomain.remote_dom = remote_domain;
879 bind_interdomain.remote_port = remote_port;
880
881 err = HYPERVISOR_event_channel_op(EVTCHNOP_bind_interdomain,
882 &bind_interdomain);
883
884 return err ? : bind_evtchn_to_irq(bind_interdomain.local_port);
885}
886
62cc5fc7
OH
887static int find_virq(unsigned int virq, unsigned int cpu)
888{
889 struct evtchn_status status;
890 int port, rc = -ENOENT;
891
892 memset(&status, 0, sizeof(status));
893 for (port = 0; port <= NR_EVENT_CHANNELS; port++) {
894 status.dom = DOMID_SELF;
895 status.port = port;
896 rc = HYPERVISOR_event_channel_op(EVTCHNOP_status, &status);
897 if (rc < 0)
898 continue;
899 if (status.status != EVTCHNSTAT_virq)
900 continue;
901 if (status.u.virq == virq && status.vcpu == cpu) {
902 rc = port;
903 break;
904 }
905 }
906 return rc;
907}
f87e4cac 908
4fe7d5a7 909int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
e46cdb66
JF
910{
911 struct evtchn_bind_virq bind_virq;
62cc5fc7 912 int evtchn, irq, ret;
e46cdb66 913
77365948 914 mutex_lock(&irq_mapping_update_lock);
e46cdb66
JF
915
916 irq = per_cpu(virq_to_irq, cpu)[virq];
917
918 if (irq == -1) {
c9df1ce5 919 irq = xen_allocate_irq_dynamic();
7bee9768
IC
920 if (irq == -1)
921 goto out;
a52521f1 922
c442b806 923 irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
a52521f1
JF
924 handle_percpu_irq, "virq");
925
e46cdb66
JF
926 bind_virq.virq = virq;
927 bind_virq.vcpu = cpu;
62cc5fc7
OH
928 ret = HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
929 &bind_virq);
930 if (ret == 0)
931 evtchn = bind_virq.port;
932 else {
933 if (ret == -EEXIST)
934 ret = find_virq(virq, cpu);
935 BUG_ON(ret < 0);
936 evtchn = ret;
937 }
e46cdb66 938
3d4cfa37 939 xen_irq_info_virq_init(cpu, irq, evtchn, virq);
e46cdb66
JF
940
941 bind_evtchn_to_cpu(evtchn, cpu);
942 }
943
7bee9768 944out:
77365948 945 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
946
947 return irq;
948}
949
950static void unbind_from_irq(unsigned int irq)
951{
952 struct evtchn_close close;
953 int evtchn = evtchn_from_irq(irq);
420eb554 954 struct irq_info *info = irq_get_handler_data(irq);
e46cdb66 955
77365948 956 mutex_lock(&irq_mapping_update_lock);
e46cdb66 957
420eb554
DDG
958 if (info->refcnt > 0) {
959 info->refcnt--;
960 if (info->refcnt != 0)
961 goto done;
962 }
963
d77bbd4d 964 if (VALID_EVTCHN(evtchn)) {
e46cdb66
JF
965 close.port = evtchn;
966 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
967 BUG();
968
969 switch (type_from_irq(irq)) {
970 case IRQT_VIRQ:
971 per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 972 [virq_from_irq(irq)] = -1;
e46cdb66 973 break;
d68d82af
AN
974 case IRQT_IPI:
975 per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 976 [ipi_from_irq(irq)] = -1;
d68d82af 977 break;
e46cdb66
JF
978 default:
979 break;
980 }
981
982 /* Closed ports are implicitly re-bound to VCPU0. */
983 bind_evtchn_to_cpu(evtchn, 0);
984
985 evtchn_to_irq[evtchn] = -1;
fed5ea87
IC
986 }
987
ca62ce8c 988 BUG_ON(info_for_irq(irq)->type == IRQT_UNBOUND);
e46cdb66 989
9158c358 990 xen_free_irq(irq);
e46cdb66 991
420eb554 992 done:
77365948 993 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
994}
995
996int bind_evtchn_to_irqhandler(unsigned int evtchn,
7c239975 997 irq_handler_t handler,
e46cdb66
JF
998 unsigned long irqflags,
999 const char *devname, void *dev_id)
1000{
361ae8cb 1001 int irq, retval;
e46cdb66
JF
1002
1003 irq = bind_evtchn_to_irq(evtchn);
7bee9768
IC
1004 if (irq < 0)
1005 return irq;
e46cdb66
JF
1006 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1007 if (retval != 0) {
1008 unbind_from_irq(irq);
1009 return retval;
1010 }
1011
1012 return irq;
1013}
1014EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
1015
2e820f58
IC
1016int bind_interdomain_evtchn_to_irqhandler(unsigned int remote_domain,
1017 unsigned int remote_port,
1018 irq_handler_t handler,
1019 unsigned long irqflags,
1020 const char *devname,
1021 void *dev_id)
1022{
1023 int irq, retval;
1024
1025 irq = bind_interdomain_evtchn_to_irq(remote_domain, remote_port);
1026 if (irq < 0)
1027 return irq;
1028
1029 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1030 if (retval != 0) {
1031 unbind_from_irq(irq);
1032 return retval;
1033 }
1034
1035 return irq;
1036}
1037EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irqhandler);
1038
e46cdb66 1039int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
7c239975 1040 irq_handler_t handler,
e46cdb66
JF
1041 unsigned long irqflags, const char *devname, void *dev_id)
1042{
361ae8cb 1043 int irq, retval;
e46cdb66
JF
1044
1045 irq = bind_virq_to_irq(virq, cpu);
7bee9768
IC
1046 if (irq < 0)
1047 return irq;
e46cdb66
JF
1048 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1049 if (retval != 0) {
1050 unbind_from_irq(irq);
1051 return retval;
1052 }
1053
1054 return irq;
1055}
1056EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
1057
f87e4cac
JF
1058int bind_ipi_to_irqhandler(enum ipi_vector ipi,
1059 unsigned int cpu,
1060 irq_handler_t handler,
1061 unsigned long irqflags,
1062 const char *devname,
1063 void *dev_id)
1064{
1065 int irq, retval;
1066
1067 irq = bind_ipi_to_irq(ipi, cpu);
1068 if (irq < 0)
1069 return irq;
1070
9bab0b7f 1071 irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME | IRQF_EARLY_RESUME;
f87e4cac
JF
1072 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1073 if (retval != 0) {
1074 unbind_from_irq(irq);
1075 return retval;
1076 }
1077
1078 return irq;
1079}
1080
e46cdb66
JF
1081void unbind_from_irqhandler(unsigned int irq, void *dev_id)
1082{
1083 free_irq(irq, dev_id);
1084 unbind_from_irq(irq);
1085}
1086EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
1087
420eb554
DDG
1088int evtchn_make_refcounted(unsigned int evtchn)
1089{
1090 int irq = evtchn_to_irq[evtchn];
1091 struct irq_info *info;
1092
1093 if (irq == -1)
1094 return -ENOENT;
1095
1096 info = irq_get_handler_data(irq);
1097
1098 if (!info)
1099 return -ENOENT;
1100
1101 WARN_ON(info->refcnt != -1);
1102
1103 info->refcnt = 1;
1104
1105 return 0;
1106}
1107EXPORT_SYMBOL_GPL(evtchn_make_refcounted);
1108
1109int evtchn_get(unsigned int evtchn)
1110{
1111 int irq;
1112 struct irq_info *info;
1113 int err = -ENOENT;
1114
c3b3f16d
DDG
1115 if (evtchn >= NR_EVENT_CHANNELS)
1116 return -EINVAL;
1117
420eb554
DDG
1118 mutex_lock(&irq_mapping_update_lock);
1119
1120 irq = evtchn_to_irq[evtchn];
1121 if (irq == -1)
1122 goto done;
1123
1124 info = irq_get_handler_data(irq);
1125
1126 if (!info)
1127 goto done;
1128
1129 err = -EINVAL;
1130 if (info->refcnt <= 0)
1131 goto done;
1132
1133 info->refcnt++;
1134 err = 0;
1135 done:
1136 mutex_unlock(&irq_mapping_update_lock);
1137
1138 return err;
1139}
1140EXPORT_SYMBOL_GPL(evtchn_get);
1141
1142void evtchn_put(unsigned int evtchn)
1143{
1144 int irq = evtchn_to_irq[evtchn];
1145 if (WARN_ON(irq == -1))
1146 return;
1147 unbind_from_irq(irq);
1148}
1149EXPORT_SYMBOL_GPL(evtchn_put);
1150
f87e4cac
JF
1151void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
1152{
1153 int irq = per_cpu(ipi_to_irq, cpu)[vector];
1154 BUG_ON(irq < 0);
1155 notify_remote_via_irq(irq);
1156}
1157
ee523ca1
JF
1158irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
1159{
1160 struct shared_info *sh = HYPERVISOR_shared_info;
1161 int cpu = smp_processor_id();
cb60d114 1162 unsigned long *cpu_evtchn = per_cpu(cpu_evtchn_mask, cpu);
ee523ca1
JF
1163 int i;
1164 unsigned long flags;
1165 static DEFINE_SPINLOCK(debug_lock);
cb52e6d9 1166 struct vcpu_info *v;
ee523ca1
JF
1167
1168 spin_lock_irqsave(&debug_lock, flags);
1169
cb52e6d9 1170 printk("\nvcpu %d\n ", cpu);
ee523ca1
JF
1171
1172 for_each_online_cpu(i) {
cb52e6d9
IC
1173 int pending;
1174 v = per_cpu(xen_vcpu, i);
1175 pending = (get_irq_regs() && i == cpu)
1176 ? xen_irqs_disabled(get_irq_regs())
1177 : v->evtchn_upcall_mask;
1178 printk("%d: masked=%d pending=%d event_sel %0*lx\n ", i,
1179 pending, v->evtchn_upcall_pending,
1180 (int)(sizeof(v->evtchn_pending_sel)*2),
1181 v->evtchn_pending_sel);
1182 }
1183 v = per_cpu(xen_vcpu, cpu);
1184
1185 printk("\npending:\n ");
1186 for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
1187 printk("%0*lx%s", (int)sizeof(sh->evtchn_pending[0])*2,
1188 sh->evtchn_pending[i],
1189 i % 8 == 0 ? "\n " : " ");
1190 printk("\nglobal mask:\n ");
1191 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
1192 printk("%0*lx%s",
1193 (int)(sizeof(sh->evtchn_mask[0])*2),
1194 sh->evtchn_mask[i],
1195 i % 8 == 0 ? "\n " : " ");
1196
1197 printk("\nglobally unmasked:\n ");
1198 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
1199 printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
1200 sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
1201 i % 8 == 0 ? "\n " : " ");
1202
1203 printk("\nlocal cpu%d mask:\n ", cpu);
1204 for (i = (NR_EVENT_CHANNELS/BITS_PER_LONG)-1; i >= 0; i--)
1205 printk("%0*lx%s", (int)(sizeof(cpu_evtchn[0])*2),
1206 cpu_evtchn[i],
1207 i % 8 == 0 ? "\n " : " ");
1208
1209 printk("\nlocally unmasked:\n ");
1210 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
1211 unsigned long pending = sh->evtchn_pending[i]
1212 & ~sh->evtchn_mask[i]
1213 & cpu_evtchn[i];
1214 printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
1215 pending, i % 8 == 0 ? "\n " : " ");
ee523ca1 1216 }
ee523ca1
JF
1217
1218 printk("\npending list:\n");
cb52e6d9 1219 for (i = 0; i < NR_EVENT_CHANNELS; i++) {
ee523ca1 1220 if (sync_test_bit(i, sh->evtchn_pending)) {
cb52e6d9
IC
1221 int word_idx = i / BITS_PER_LONG;
1222 printk(" %d: event %d -> irq %d%s%s%s\n",
ced40d0f 1223 cpu_from_evtchn(i), i,
cb52e6d9
IC
1224 evtchn_to_irq[i],
1225 sync_test_bit(word_idx, &v->evtchn_pending_sel)
1226 ? "" : " l2-clear",
1227 !sync_test_bit(i, sh->evtchn_mask)
1228 ? "" : " globally-masked",
1229 sync_test_bit(i, cpu_evtchn)
1230 ? "" : " locally-masked");
ee523ca1
JF
1231 }
1232 }
1233
1234 spin_unlock_irqrestore(&debug_lock, flags);
1235
1236 return IRQ_HANDLED;
1237}
1238
245b2e70 1239static DEFINE_PER_CPU(unsigned, xed_nesting_count);
ada6814c
KF
1240static DEFINE_PER_CPU(unsigned int, current_word_idx);
1241static DEFINE_PER_CPU(unsigned int, current_bit_idx);
245b2e70 1242
ab7f863e
SR
1243/*
1244 * Mask out the i least significant bits of w
1245 */
1246#define MASK_LSBS(w, i) (w & ((~0UL) << i))
245b2e70 1247
e46cdb66
JF
1248/*
1249 * Search the CPUs pending events bitmasks. For each one found, map
1250 * the event number to an irq, and feed it into do_IRQ() for
1251 * handling.
1252 *
1253 * Xen uses a two-level bitmap to speed searching. The first level is
1254 * a bitset of words which contain pending event bits. The second
1255 * level is a bitset of pending events themselves.
1256 */
38e20b07 1257static void __xen_evtchn_do_upcall(void)
e46cdb66 1258{
24b51c2f 1259 int start_word_idx, start_bit_idx;
ab7f863e 1260 int word_idx, bit_idx;
24b51c2f 1261 int i;
e46cdb66
JF
1262 int cpu = get_cpu();
1263 struct shared_info *s = HYPERVISOR_shared_info;
780f36d8 1264 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
088c05a8 1265 unsigned count;
e46cdb66 1266
229664be
JF
1267 do {
1268 unsigned long pending_words;
e46cdb66 1269
229664be 1270 vcpu_info->evtchn_upcall_pending = 0;
e46cdb66 1271
b2e4ae69 1272 if (__this_cpu_inc_return(xed_nesting_count) - 1)
229664be 1273 goto out;
e46cdb66 1274
e849c3e9
IY
1275#ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */
1276 /* Clear master flag /before/ clearing selector flag. */
6673cf63 1277 wmb();
e849c3e9 1278#endif
229664be 1279 pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0);
ab7f863e 1280
24b51c2f
KF
1281 start_word_idx = __this_cpu_read(current_word_idx);
1282 start_bit_idx = __this_cpu_read(current_bit_idx);
1283
1284 word_idx = start_word_idx;
ab7f863e 1285
24b51c2f 1286 for (i = 0; pending_words != 0; i++) {
229664be 1287 unsigned long pending_bits;
ab7f863e 1288 unsigned long words;
229664be 1289
ab7f863e
SR
1290 words = MASK_LSBS(pending_words, word_idx);
1291
1292 /*
ada6814c 1293 * If we masked out all events, wrap to beginning.
ab7f863e
SR
1294 */
1295 if (words == 0) {
ada6814c
KF
1296 word_idx = 0;
1297 bit_idx = 0;
ab7f863e
SR
1298 continue;
1299 }
1300 word_idx = __ffs(words);
229664be 1301
24b51c2f
KF
1302 pending_bits = active_evtchns(cpu, s, word_idx);
1303 bit_idx = 0; /* usually scan entire word from start */
1304 if (word_idx == start_word_idx) {
1305 /* We scan the starting word in two parts */
1306 if (i == 0)
1307 /* 1st time: start in the middle */
1308 bit_idx = start_bit_idx;
1309 else
1310 /* 2nd time: mask bits done already */
1311 bit_idx &= (1UL << start_bit_idx) - 1;
1312 }
1313
ab7f863e
SR
1314 do {
1315 unsigned long bits;
1316 int port, irq;
ca4dbc66 1317 struct irq_desc *desc;
229664be 1318
ab7f863e
SR
1319 bits = MASK_LSBS(pending_bits, bit_idx);
1320
1321 /* If we masked out all events, move on. */
ada6814c 1322 if (bits == 0)
ab7f863e 1323 break;
ab7f863e
SR
1324
1325 bit_idx = __ffs(bits);
1326
1327 /* Process port. */
1328 port = (word_idx * BITS_PER_LONG) + bit_idx;
1329 irq = evtchn_to_irq[port];
1330
ca4dbc66
EB
1331 if (irq != -1) {
1332 desc = irq_to_desc(irq);
1333 if (desc)
1334 generic_handle_irq_desc(irq, desc);
1335 }
ab7f863e 1336
ada6814c
KF
1337 bit_idx = (bit_idx + 1) % BITS_PER_LONG;
1338
1339 /* Next caller starts at last processed + 1 */
1340 __this_cpu_write(current_word_idx,
1341 bit_idx ? word_idx :
1342 (word_idx+1) % BITS_PER_LONG);
1343 __this_cpu_write(current_bit_idx, bit_idx);
1344 } while (bit_idx != 0);
ab7f863e 1345
24b51c2f
KF
1346 /* Scan start_l1i twice; all others once. */
1347 if ((word_idx != start_word_idx) || (i != 0))
ab7f863e 1348 pending_words &= ~(1UL << word_idx);
ada6814c
KF
1349
1350 word_idx = (word_idx + 1) % BITS_PER_LONG;
e46cdb66 1351 }
e46cdb66 1352
229664be
JF
1353 BUG_ON(!irqs_disabled());
1354
780f36d8
CL
1355 count = __this_cpu_read(xed_nesting_count);
1356 __this_cpu_write(xed_nesting_count, 0);
183d03cc 1357 } while (count != 1 || vcpu_info->evtchn_upcall_pending);
229664be
JF
1358
1359out:
38e20b07
SY
1360
1361 put_cpu();
1362}
1363
1364void xen_evtchn_do_upcall(struct pt_regs *regs)
1365{
1366 struct pt_regs *old_regs = set_irq_regs(regs);
1367
1368 exit_idle();
1369 irq_enter();
1370
1371 __xen_evtchn_do_upcall();
1372
3445a8fd
JF
1373 irq_exit();
1374 set_irq_regs(old_regs);
38e20b07 1375}
3445a8fd 1376
38e20b07
SY
1377void xen_hvm_evtchn_do_upcall(void)
1378{
1379 __xen_evtchn_do_upcall();
e46cdb66 1380}
183d03cc 1381EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
e46cdb66 1382
eb1e305f
JF
1383/* Rebind a new event channel to an existing irq. */
1384void rebind_evtchn_irq(int evtchn, int irq)
1385{
d77bbd4d
JF
1386 struct irq_info *info = info_for_irq(irq);
1387
eb1e305f
JF
1388 /* Make sure the irq is masked, since the new event channel
1389 will also be masked. */
1390 disable_irq(irq);
1391
77365948 1392 mutex_lock(&irq_mapping_update_lock);
eb1e305f
JF
1393
1394 /* After resume the irq<->evtchn mappings are all cleared out */
1395 BUG_ON(evtchn_to_irq[evtchn] != -1);
1396 /* Expect irq to have been bound before,
d77bbd4d
JF
1397 so there should be a proper type */
1398 BUG_ON(info->type == IRQT_UNBOUND);
eb1e305f 1399
9158c358 1400 xen_irq_info_evtchn_init(irq, evtchn);
eb1e305f 1401
77365948 1402 mutex_unlock(&irq_mapping_update_lock);
eb1e305f
JF
1403
1404 /* new event channels are always bound to cpu 0 */
0de26520 1405 irq_set_affinity(irq, cpumask_of(0));
eb1e305f
JF
1406
1407 /* Unmask the event channel. */
1408 enable_irq(irq);
1409}
1410
e46cdb66 1411/* Rebind an evtchn so that it gets delivered to a specific cpu */
d5dedd45 1412static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
e46cdb66
JF
1413{
1414 struct evtchn_bind_vcpu bind_vcpu;
1415 int evtchn = evtchn_from_irq(irq);
1416
be49472f
IC
1417 if (!VALID_EVTCHN(evtchn))
1418 return -1;
1419
1420 /*
1421 * Events delivered via platform PCI interrupts are always
1422 * routed to vcpu 0 and hence cannot be rebound.
1423 */
1424 if (xen_hvm_domain() && !xen_have_vector_callback)
d5dedd45 1425 return -1;
e46cdb66
JF
1426
1427 /* Send future instances of this interrupt to other vcpu. */
1428 bind_vcpu.port = evtchn;
1429 bind_vcpu.vcpu = tcpu;
1430
1431 /*
1432 * If this fails, it usually just indicates that we're dealing with a
1433 * virq or IPI channel, which don't actually need to be rebound. Ignore
1434 * it, but don't do the xenlinux-level rebind in that case.
1435 */
1436 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
1437 bind_evtchn_to_cpu(evtchn, tcpu);
e46cdb66 1438
d5dedd45
YL
1439 return 0;
1440}
e46cdb66 1441
c9e265e0
TG
1442static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest,
1443 bool force)
e46cdb66 1444{
0de26520 1445 unsigned tcpu = cpumask_first(dest);
d5dedd45 1446
c9e265e0 1447 return rebind_irq_to_cpu(data->irq, tcpu);
e46cdb66
JF
1448}
1449
642e0c88
IY
1450int resend_irq_on_evtchn(unsigned int irq)
1451{
1452 int masked, evtchn = evtchn_from_irq(irq);
1453 struct shared_info *s = HYPERVISOR_shared_info;
1454
1455 if (!VALID_EVTCHN(evtchn))
1456 return 1;
1457
1458 masked = sync_test_and_set_bit(evtchn, s->evtchn_mask);
1459 sync_set_bit(evtchn, s->evtchn_pending);
1460 if (!masked)
1461 unmask_evtchn(evtchn);
1462
1463 return 1;
1464}
1465
c9e265e0 1466static void enable_dynirq(struct irq_data *data)
e46cdb66 1467{
c9e265e0 1468 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1469
1470 if (VALID_EVTCHN(evtchn))
1471 unmask_evtchn(evtchn);
1472}
1473
c9e265e0 1474static void disable_dynirq(struct irq_data *data)
e46cdb66 1475{
c9e265e0 1476 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1477
1478 if (VALID_EVTCHN(evtchn))
1479 mask_evtchn(evtchn);
1480}
1481
c9e265e0 1482static void ack_dynirq(struct irq_data *data)
e46cdb66 1483{
c9e265e0 1484 int evtchn = evtchn_from_irq(data->irq);
e46cdb66 1485
7e186bdd 1486 irq_move_irq(data);
e46cdb66
JF
1487
1488 if (VALID_EVTCHN(evtchn))
7e186bdd
SS
1489 clear_evtchn(evtchn);
1490}
1491
1492static void mask_ack_dynirq(struct irq_data *data)
1493{
1494 disable_dynirq(data);
1495 ack_dynirq(data);
e46cdb66
JF
1496}
1497
c9e265e0 1498static int retrigger_dynirq(struct irq_data *data)
e46cdb66 1499{
c9e265e0 1500 int evtchn = evtchn_from_irq(data->irq);
ee8fa1c6 1501 struct shared_info *sh = HYPERVISOR_shared_info;
e46cdb66
JF
1502 int ret = 0;
1503
1504 if (VALID_EVTCHN(evtchn)) {
ee8fa1c6
JF
1505 int masked;
1506
1507 masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask);
1508 sync_set_bit(evtchn, sh->evtchn_pending);
1509 if (!masked)
1510 unmask_evtchn(evtchn);
e46cdb66
JF
1511 ret = 1;
1512 }
1513
1514 return ret;
1515}
1516
0a85226f 1517static void restore_pirqs(void)
9a069c33
SS
1518{
1519 int pirq, rc, irq, gsi;
1520 struct physdev_map_pirq map_irq;
69c358ce 1521 struct irq_info *info;
9a069c33 1522
69c358ce
IC
1523 list_for_each_entry(info, &xen_irq_list_head, list) {
1524 if (info->type != IRQT_PIRQ)
9a069c33
SS
1525 continue;
1526
69c358ce
IC
1527 pirq = info->u.pirq.pirq;
1528 gsi = info->u.pirq.gsi;
1529 irq = info->irq;
1530
9a069c33
SS
1531 /* save/restore of PT devices doesn't work, so at this point the
1532 * only devices present are GSI based emulated devices */
9a069c33
SS
1533 if (!gsi)
1534 continue;
1535
1536 map_irq.domid = DOMID_SELF;
1537 map_irq.type = MAP_PIRQ_TYPE_GSI;
1538 map_irq.index = gsi;
1539 map_irq.pirq = pirq;
1540
1541 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
1542 if (rc) {
1543 printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
1544 gsi, irq, pirq, rc);
9158c358 1545 xen_free_irq(irq);
9a069c33
SS
1546 continue;
1547 }
1548
1549 printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
1550
c9e265e0 1551 __startup_pirq(irq);
9a069c33
SS
1552 }
1553}
1554
0e91398f
JF
1555static void restore_cpu_virqs(unsigned int cpu)
1556{
1557 struct evtchn_bind_virq bind_virq;
1558 int virq, irq, evtchn;
1559
1560 for (virq = 0; virq < NR_VIRQS; virq++) {
1561 if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
1562 continue;
1563
ced40d0f 1564 BUG_ON(virq_from_irq(irq) != virq);
0e91398f
JF
1565
1566 /* Get a new binding from Xen. */
1567 bind_virq.virq = virq;
1568 bind_virq.vcpu = cpu;
1569 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
1570 &bind_virq) != 0)
1571 BUG();
1572 evtchn = bind_virq.port;
1573
1574 /* Record the new mapping. */
3d4cfa37 1575 xen_irq_info_virq_init(cpu, irq, evtchn, virq);
0e91398f 1576 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1577 }
1578}
1579
1580static void restore_cpu_ipis(unsigned int cpu)
1581{
1582 struct evtchn_bind_ipi bind_ipi;
1583 int ipi, irq, evtchn;
1584
1585 for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
1586 if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
1587 continue;
1588
ced40d0f 1589 BUG_ON(ipi_from_irq(irq) != ipi);
0e91398f
JF
1590
1591 /* Get a new binding from Xen. */
1592 bind_ipi.vcpu = cpu;
1593 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
1594 &bind_ipi) != 0)
1595 BUG();
1596 evtchn = bind_ipi.port;
1597
1598 /* Record the new mapping. */
3d4cfa37 1599 xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
0e91398f 1600 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1601 }
1602}
1603
2d9e1e2f
JF
1604/* Clear an irq's pending state, in preparation for polling on it */
1605void xen_clear_irq_pending(int irq)
1606{
1607 int evtchn = evtchn_from_irq(irq);
1608
1609 if (VALID_EVTCHN(evtchn))
1610 clear_evtchn(evtchn);
1611}
d9a8814f 1612EXPORT_SYMBOL(xen_clear_irq_pending);
168d2f46
JF
1613void xen_set_irq_pending(int irq)
1614{
1615 int evtchn = evtchn_from_irq(irq);
1616
1617 if (VALID_EVTCHN(evtchn))
1618 set_evtchn(evtchn);
1619}
1620
1621bool xen_test_irq_pending(int irq)
1622{
1623 int evtchn = evtchn_from_irq(irq);
1624 bool ret = false;
1625
1626 if (VALID_EVTCHN(evtchn))
1627 ret = test_evtchn(evtchn);
1628
1629 return ret;
1630}
1631
d9a8814f
KRW
1632/* Poll waiting for an irq to become pending with timeout. In the usual case,
1633 * the irq will be disabled so it won't deliver an interrupt. */
1634void xen_poll_irq_timeout(int irq, u64 timeout)
2d9e1e2f
JF
1635{
1636 evtchn_port_t evtchn = evtchn_from_irq(irq);
1637
1638 if (VALID_EVTCHN(evtchn)) {
1639 struct sched_poll poll;
1640
1641 poll.nr_ports = 1;
d9a8814f 1642 poll.timeout = timeout;
ff3c5362 1643 set_xen_guest_handle(poll.ports, &evtchn);
2d9e1e2f
JF
1644
1645 if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
1646 BUG();
1647 }
1648}
d9a8814f
KRW
1649EXPORT_SYMBOL(xen_poll_irq_timeout);
1650/* Poll waiting for an irq to become pending. In the usual case, the
1651 * irq will be disabled so it won't deliver an interrupt. */
1652void xen_poll_irq(int irq)
1653{
1654 xen_poll_irq_timeout(irq, 0 /* no timeout */);
1655}
2d9e1e2f 1656
c7c2c3a2
KRW
1657/* Check whether the IRQ line is shared with other guests. */
1658int xen_test_irq_shared(int irq)
1659{
1660 struct irq_info *info = info_for_irq(irq);
1661 struct physdev_irq_status_query irq_status = { .irq = info->u.pirq.pirq };
1662
1663 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
1664 return 0;
1665 return !(irq_status.flags & XENIRQSTAT_shared);
1666}
1667EXPORT_SYMBOL_GPL(xen_test_irq_shared);
1668
0e91398f
JF
1669void xen_irq_resume(void)
1670{
6cb6537d
IC
1671 unsigned int cpu, evtchn;
1672 struct irq_info *info;
0e91398f
JF
1673
1674 init_evtchn_cpu_bindings();
1675
1676 /* New event-channel space is not 'live' yet. */
1677 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1678 mask_evtchn(evtchn);
1679
1680 /* No IRQ <-> event-channel mappings. */
6cb6537d
IC
1681 list_for_each_entry(info, &xen_irq_list_head, list)
1682 info->evtchn = 0; /* zap event-channel binding */
0e91398f
JF
1683
1684 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1685 evtchn_to_irq[evtchn] = -1;
1686
1687 for_each_possible_cpu(cpu) {
1688 restore_cpu_virqs(cpu);
1689 restore_cpu_ipis(cpu);
1690 }
6903591f 1691
0a85226f 1692 restore_pirqs();
0e91398f
JF
1693}
1694
e46cdb66 1695static struct irq_chip xen_dynamic_chip __read_mostly = {
c9e265e0 1696 .name = "xen-dyn",
54a353a0 1697
c9e265e0
TG
1698 .irq_disable = disable_dynirq,
1699 .irq_mask = disable_dynirq,
1700 .irq_unmask = enable_dynirq,
54a353a0 1701
7e186bdd
SS
1702 .irq_ack = ack_dynirq,
1703 .irq_mask_ack = mask_ack_dynirq,
1704
c9e265e0
TG
1705 .irq_set_affinity = set_affinity_irq,
1706 .irq_retrigger = retrigger_dynirq,
e46cdb66
JF
1707};
1708
d46a78b0 1709static struct irq_chip xen_pirq_chip __read_mostly = {
c9e265e0 1710 .name = "xen-pirq",
d46a78b0 1711
c9e265e0
TG
1712 .irq_startup = startup_pirq,
1713 .irq_shutdown = shutdown_pirq,
c9e265e0 1714 .irq_enable = enable_pirq,
c9e265e0 1715 .irq_disable = disable_pirq,
d46a78b0 1716
7e186bdd
SS
1717 .irq_mask = disable_dynirq,
1718 .irq_unmask = enable_dynirq,
1719
1720 .irq_ack = eoi_pirq,
1721 .irq_eoi = eoi_pirq,
1722 .irq_mask_ack = mask_ack_pirq,
d46a78b0 1723
c9e265e0 1724 .irq_set_affinity = set_affinity_irq,
d46a78b0 1725
c9e265e0 1726 .irq_retrigger = retrigger_dynirq,
d46a78b0
JF
1727};
1728
aaca4964 1729static struct irq_chip xen_percpu_chip __read_mostly = {
c9e265e0 1730 .name = "xen-percpu",
aaca4964 1731
c9e265e0
TG
1732 .irq_disable = disable_dynirq,
1733 .irq_mask = disable_dynirq,
1734 .irq_unmask = enable_dynirq,
aaca4964 1735
c9e265e0 1736 .irq_ack = ack_dynirq,
aaca4964
JF
1737};
1738
38e20b07
SY
1739int xen_set_callback_via(uint64_t via)
1740{
1741 struct xen_hvm_param a;
1742 a.domid = DOMID_SELF;
1743 a.index = HVM_PARAM_CALLBACK_IRQ;
1744 a.value = via;
1745 return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
1746}
1747EXPORT_SYMBOL_GPL(xen_set_callback_via);
1748
ca65f9fc 1749#ifdef CONFIG_XEN_PVHVM
38e20b07
SY
1750/* Vector callbacks are better than PCI interrupts to receive event
1751 * channel notifications because we can receive vector callbacks on any
1752 * vcpu and we don't need PCI support or APIC interactions. */
1753void xen_callback_vector(void)
1754{
1755 int rc;
1756 uint64_t callback_via;
1757 if (xen_have_vector_callback) {
1758 callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK);
1759 rc = xen_set_callback_via(callback_via);
1760 if (rc) {
1761 printk(KERN_ERR "Request for Xen HVM callback vector"
1762 " failed.\n");
1763 xen_have_vector_callback = 0;
1764 return;
1765 }
1766 printk(KERN_INFO "Xen HVM callback vector for event delivery is "
1767 "enabled\n");
1768 /* in the restore case the vector has already been allocated */
1769 if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors))
1770 alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector);
1771 }
1772}
ca65f9fc
SS
1773#else
1774void xen_callback_vector(void) {}
1775#endif
38e20b07 1776
e46cdb66
JF
1777void __init xen_init_IRQ(void)
1778{
9846ff10 1779 int i, rc;
c7a3589e 1780
b21ddbf5
JF
1781 evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
1782 GFP_KERNEL);
9d093e29 1783 BUG_ON(!evtchn_to_irq);
b21ddbf5
JF
1784 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1785 evtchn_to_irq[i] = -1;
e46cdb66
JF
1786
1787 init_evtchn_cpu_bindings();
1788
1789 /* No event channels are 'live' right now. */
1790 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1791 mask_evtchn(i);
1792
9846ff10
SS
1793 pirq_needs_eoi = pirq_needs_eoi_flag;
1794
38e20b07
SY
1795 if (xen_hvm_domain()) {
1796 xen_callback_vector();
1797 native_init_IRQ();
3942b740
SS
1798 /* pci_xen_hvm_init must be called after native_init_IRQ so that
1799 * __acpi_register_gsi can point at the right function */
1800 pci_xen_hvm_init();
38e20b07 1801 } else {
9846ff10
SS
1802 struct physdev_pirq_eoi_gmfn eoi_gmfn;
1803
38e20b07 1804 irq_ctx_init(smp_processor_id());
38aa66fc 1805 if (xen_initial_domain())
a0ee0567 1806 pci_xen_initial_domain();
9846ff10
SS
1807
1808 pirq_eoi_map = (void *)__get_free_page(GFP_KERNEL|__GFP_ZERO);
1809 eoi_gmfn.gmfn = virt_to_mfn(pirq_eoi_map);
1810 rc = HYPERVISOR_physdev_op(PHYSDEVOP_pirq_eoi_gmfn_v2, &eoi_gmfn);
1811 if (rc != 0) {
1812 free_page((unsigned long) pirq_eoi_map);
1813 pirq_eoi_map = NULL;
1814 } else
1815 pirq_needs_eoi = pirq_check_eoi_map;
38e20b07 1816 }
e46cdb66 1817}
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