Commit | Line | Data |
---|---|---|
e46cdb66 JF |
1 | /* |
2 | * Xen event channels | |
3 | * | |
4 | * Xen models interrupts with abstract event channels. Because each | |
5 | * domain gets 1024 event channels, but NR_IRQ is not that large, we | |
6 | * must dynamically map irqs<->event channels. The event channels | |
7 | * interface with the rest of the kernel by defining a xen interrupt | |
25985edc | 8 | * chip. When an event is received, it is mapped to an irq and sent |
e46cdb66 JF |
9 | * through the normal interrupt processing path. |
10 | * | |
11 | * There are four kinds of events which can be mapped to an event | |
12 | * channel: | |
13 | * | |
14 | * 1. Inter-domain notifications. This includes all the virtual | |
15 | * device events, since they're driven by front-ends in another domain | |
16 | * (typically dom0). | |
17 | * 2. VIRQs, typically used for timers. These are per-cpu events. | |
18 | * 3. IPIs. | |
d46a78b0 | 19 | * 4. PIRQs - Hardware interrupts. |
e46cdb66 JF |
20 | * |
21 | * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007 | |
22 | */ | |
23 | ||
24 | #include <linux/linkage.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/irq.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/string.h> | |
28e08861 | 29 | #include <linux/bootmem.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
b21ddbf5 | 31 | #include <linux/irqnr.h> |
f731e3ef | 32 | #include <linux/pci.h> |
e46cdb66 | 33 | |
38e20b07 | 34 | #include <asm/desc.h> |
e46cdb66 JF |
35 | #include <asm/ptrace.h> |
36 | #include <asm/irq.h> | |
792dc4f6 | 37 | #include <asm/idle.h> |
0794bfc7 | 38 | #include <asm/io_apic.h> |
e46cdb66 | 39 | #include <asm/sync_bitops.h> |
42a1de56 | 40 | #include <asm/xen/pci.h> |
e46cdb66 | 41 | #include <asm/xen/hypercall.h> |
8d1b8753 | 42 | #include <asm/xen/hypervisor.h> |
e46cdb66 | 43 | |
38e20b07 SY |
44 | #include <xen/xen.h> |
45 | #include <xen/hvm.h> | |
e04d0d07 | 46 | #include <xen/xen-ops.h> |
e46cdb66 JF |
47 | #include <xen/events.h> |
48 | #include <xen/interface/xen.h> | |
49 | #include <xen/interface/event_channel.h> | |
38e20b07 SY |
50 | #include <xen/interface/hvm/hvm_op.h> |
51 | #include <xen/interface/hvm/params.h> | |
e46cdb66 | 52 | |
e46cdb66 JF |
53 | /* |
54 | * This lock protects updates to the following mapping and reference-count | |
55 | * arrays. The lock does not need to be acquired to read the mapping tables. | |
56 | */ | |
77365948 | 57 | static DEFINE_MUTEX(irq_mapping_update_lock); |
e46cdb66 | 58 | |
6cb6537d IC |
59 | static LIST_HEAD(xen_irq_list_head); |
60 | ||
e46cdb66 | 61 | /* IRQ <-> VIRQ mapping. */ |
204fba4a | 62 | static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1}; |
e46cdb66 | 63 | |
f87e4cac | 64 | /* IRQ <-> IPI mapping */ |
204fba4a | 65 | static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1}; |
f87e4cac | 66 | |
ced40d0f JF |
67 | /* Interrupt types. */ |
68 | enum xen_irq_type { | |
d77bbd4d | 69 | IRQT_UNBOUND = 0, |
f87e4cac JF |
70 | IRQT_PIRQ, |
71 | IRQT_VIRQ, | |
72 | IRQT_IPI, | |
73 | IRQT_EVTCHN | |
74 | }; | |
e46cdb66 | 75 | |
ced40d0f JF |
76 | /* |
77 | * Packed IRQ information: | |
78 | * type - enum xen_irq_type | |
79 | * event channel - irq->event channel mapping | |
80 | * cpu - cpu this event channel is bound to | |
81 | * index - type-specific information: | |
42a1de56 SS |
82 | * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM |
83 | * guest, or GSI (real passthrough IRQ) of the device. | |
ced40d0f JF |
84 | * VIRQ - virq number |
85 | * IPI - IPI vector | |
86 | * EVTCHN - | |
87 | */ | |
88 | struct irq_info | |
89 | { | |
6cb6537d | 90 | struct list_head list; |
ced40d0f | 91 | enum xen_irq_type type; /* type */ |
6cb6537d | 92 | unsigned irq; |
ced40d0f JF |
93 | unsigned short evtchn; /* event channel */ |
94 | unsigned short cpu; /* cpu bound */ | |
95 | ||
96 | union { | |
97 | unsigned short virq; | |
98 | enum ipi_vector ipi; | |
99 | struct { | |
7a043f11 | 100 | unsigned short pirq; |
ced40d0f | 101 | unsigned short gsi; |
d46a78b0 JF |
102 | unsigned char vector; |
103 | unsigned char flags; | |
beafbdc1 | 104 | uint16_t domid; |
ced40d0f JF |
105 | } pirq; |
106 | } u; | |
107 | }; | |
d46a78b0 | 108 | #define PIRQ_NEEDS_EOI (1 << 0) |
15ebbb82 | 109 | #define PIRQ_SHAREABLE (1 << 1) |
ced40d0f | 110 | |
b21ddbf5 | 111 | static int *evtchn_to_irq; |
3b32f574 | 112 | |
cb60d114 IC |
113 | static DEFINE_PER_CPU(unsigned long [NR_EVENT_CHANNELS/BITS_PER_LONG], |
114 | cpu_evtchn_mask); | |
e46cdb66 | 115 | |
e46cdb66 JF |
116 | /* Xen will never allocate port zero for any purpose. */ |
117 | #define VALID_EVTCHN(chn) ((chn) != 0) | |
118 | ||
e46cdb66 | 119 | static struct irq_chip xen_dynamic_chip; |
aaca4964 | 120 | static struct irq_chip xen_percpu_chip; |
d46a78b0 | 121 | static struct irq_chip xen_pirq_chip; |
7e186bdd SS |
122 | static void enable_dynirq(struct irq_data *data); |
123 | static void disable_dynirq(struct irq_data *data); | |
e46cdb66 | 124 | |
9158c358 IC |
125 | /* Get info for IRQ */ |
126 | static struct irq_info *info_for_irq(unsigned irq) | |
ced40d0f | 127 | { |
c442b806 | 128 | return irq_get_handler_data(irq); |
ced40d0f JF |
129 | } |
130 | ||
9158c358 IC |
131 | /* Constructors for packed IRQ information. */ |
132 | static void xen_irq_info_common_init(struct irq_info *info, | |
3d4cfa37 | 133 | unsigned irq, |
9158c358 IC |
134 | enum xen_irq_type type, |
135 | unsigned short evtchn, | |
136 | unsigned short cpu) | |
ced40d0f | 137 | { |
9158c358 IC |
138 | |
139 | BUG_ON(info->type != IRQT_UNBOUND && info->type != type); | |
140 | ||
141 | info->type = type; | |
6cb6537d | 142 | info->irq = irq; |
9158c358 IC |
143 | info->evtchn = evtchn; |
144 | info->cpu = cpu; | |
3d4cfa37 IC |
145 | |
146 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f JF |
147 | } |
148 | ||
9158c358 IC |
149 | static void xen_irq_info_evtchn_init(unsigned irq, |
150 | unsigned short evtchn) | |
ced40d0f | 151 | { |
9158c358 IC |
152 | struct irq_info *info = info_for_irq(irq); |
153 | ||
3d4cfa37 | 154 | xen_irq_info_common_init(info, irq, IRQT_EVTCHN, evtchn, 0); |
ced40d0f JF |
155 | } |
156 | ||
3d4cfa37 IC |
157 | static void xen_irq_info_ipi_init(unsigned cpu, |
158 | unsigned irq, | |
9158c358 IC |
159 | unsigned short evtchn, |
160 | enum ipi_vector ipi) | |
e46cdb66 | 161 | { |
9158c358 IC |
162 | struct irq_info *info = info_for_irq(irq); |
163 | ||
3d4cfa37 | 164 | xen_irq_info_common_init(info, irq, IRQT_IPI, evtchn, 0); |
9158c358 IC |
165 | |
166 | info->u.ipi = ipi; | |
3d4cfa37 IC |
167 | |
168 | per_cpu(ipi_to_irq, cpu)[ipi] = irq; | |
ced40d0f JF |
169 | } |
170 | ||
3d4cfa37 IC |
171 | static void xen_irq_info_virq_init(unsigned cpu, |
172 | unsigned irq, | |
9158c358 IC |
173 | unsigned short evtchn, |
174 | unsigned short virq) | |
ced40d0f | 175 | { |
9158c358 IC |
176 | struct irq_info *info = info_for_irq(irq); |
177 | ||
3d4cfa37 | 178 | xen_irq_info_common_init(info, irq, IRQT_VIRQ, evtchn, 0); |
9158c358 IC |
179 | |
180 | info->u.virq = virq; | |
3d4cfa37 IC |
181 | |
182 | per_cpu(virq_to_irq, cpu)[virq] = irq; | |
ced40d0f JF |
183 | } |
184 | ||
9158c358 IC |
185 | static void xen_irq_info_pirq_init(unsigned irq, |
186 | unsigned short evtchn, | |
187 | unsigned short pirq, | |
188 | unsigned short gsi, | |
189 | unsigned short vector, | |
beafbdc1 | 190 | uint16_t domid, |
9158c358 | 191 | unsigned char flags) |
ced40d0f | 192 | { |
9158c358 IC |
193 | struct irq_info *info = info_for_irq(irq); |
194 | ||
3d4cfa37 | 195 | xen_irq_info_common_init(info, irq, IRQT_PIRQ, evtchn, 0); |
9158c358 IC |
196 | |
197 | info->u.pirq.pirq = pirq; | |
198 | info->u.pirq.gsi = gsi; | |
199 | info->u.pirq.vector = vector; | |
beafbdc1 | 200 | info->u.pirq.domid = domid; |
9158c358 | 201 | info->u.pirq.flags = flags; |
e46cdb66 JF |
202 | } |
203 | ||
204 | /* | |
205 | * Accessors for packed IRQ information. | |
206 | */ | |
ced40d0f | 207 | static unsigned int evtchn_from_irq(unsigned irq) |
e46cdb66 | 208 | { |
110e7c7e JJ |
209 | if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq))) |
210 | return 0; | |
211 | ||
ced40d0f | 212 | return info_for_irq(irq)->evtchn; |
e46cdb66 JF |
213 | } |
214 | ||
d4c04536 IC |
215 | unsigned irq_from_evtchn(unsigned int evtchn) |
216 | { | |
217 | return evtchn_to_irq[evtchn]; | |
218 | } | |
219 | EXPORT_SYMBOL_GPL(irq_from_evtchn); | |
220 | ||
ced40d0f | 221 | static enum ipi_vector ipi_from_irq(unsigned irq) |
e46cdb66 | 222 | { |
ced40d0f JF |
223 | struct irq_info *info = info_for_irq(irq); |
224 | ||
225 | BUG_ON(info == NULL); | |
226 | BUG_ON(info->type != IRQT_IPI); | |
227 | ||
228 | return info->u.ipi; | |
229 | } | |
230 | ||
231 | static unsigned virq_from_irq(unsigned irq) | |
232 | { | |
233 | struct irq_info *info = info_for_irq(irq); | |
234 | ||
235 | BUG_ON(info == NULL); | |
236 | BUG_ON(info->type != IRQT_VIRQ); | |
237 | ||
238 | return info->u.virq; | |
239 | } | |
240 | ||
7a043f11 SS |
241 | static unsigned pirq_from_irq(unsigned irq) |
242 | { | |
243 | struct irq_info *info = info_for_irq(irq); | |
244 | ||
245 | BUG_ON(info == NULL); | |
246 | BUG_ON(info->type != IRQT_PIRQ); | |
247 | ||
248 | return info->u.pirq.pirq; | |
249 | } | |
250 | ||
ced40d0f JF |
251 | static enum xen_irq_type type_from_irq(unsigned irq) |
252 | { | |
253 | return info_for_irq(irq)->type; | |
254 | } | |
255 | ||
256 | static unsigned cpu_from_irq(unsigned irq) | |
257 | { | |
258 | return info_for_irq(irq)->cpu; | |
259 | } | |
260 | ||
261 | static unsigned int cpu_from_evtchn(unsigned int evtchn) | |
262 | { | |
263 | int irq = evtchn_to_irq[evtchn]; | |
264 | unsigned ret = 0; | |
265 | ||
266 | if (irq != -1) | |
267 | ret = cpu_from_irq(irq); | |
268 | ||
269 | return ret; | |
e46cdb66 JF |
270 | } |
271 | ||
d46a78b0 JF |
272 | static bool pirq_needs_eoi(unsigned irq) |
273 | { | |
274 | struct irq_info *info = info_for_irq(irq); | |
275 | ||
276 | BUG_ON(info->type != IRQT_PIRQ); | |
277 | ||
278 | return info->u.pirq.flags & PIRQ_NEEDS_EOI; | |
279 | } | |
280 | ||
e46cdb66 JF |
281 | static inline unsigned long active_evtchns(unsigned int cpu, |
282 | struct shared_info *sh, | |
283 | unsigned int idx) | |
284 | { | |
285 | return (sh->evtchn_pending[idx] & | |
cb60d114 | 286 | per_cpu(cpu_evtchn_mask, cpu)[idx] & |
e46cdb66 JF |
287 | ~sh->evtchn_mask[idx]); |
288 | } | |
289 | ||
290 | static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu) | |
291 | { | |
292 | int irq = evtchn_to_irq[chn]; | |
293 | ||
294 | BUG_ON(irq == -1); | |
295 | #ifdef CONFIG_SMP | |
c9e265e0 | 296 | cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu)); |
e46cdb66 JF |
297 | #endif |
298 | ||
cb60d114 IC |
299 | clear_bit(chn, per_cpu(cpu_evtchn_mask, cpu_from_irq(irq))); |
300 | set_bit(chn, per_cpu(cpu_evtchn_mask, cpu)); | |
e46cdb66 | 301 | |
ca62ce8c | 302 | info_for_irq(irq)->cpu = cpu; |
e46cdb66 JF |
303 | } |
304 | ||
305 | static void init_evtchn_cpu_bindings(void) | |
306 | { | |
1c6969ec | 307 | int i; |
e46cdb66 | 308 | #ifdef CONFIG_SMP |
6cb6537d | 309 | struct irq_info *info; |
10e58084 | 310 | |
e46cdb66 | 311 | /* By default all event channels notify CPU#0. */ |
6cb6537d IC |
312 | list_for_each_entry(info, &xen_irq_list_head, list) { |
313 | struct irq_desc *desc = irq_to_desc(info->irq); | |
c9e265e0 | 314 | cpumask_copy(desc->irq_data.affinity, cpumask_of(0)); |
0b8f1efa | 315 | } |
e46cdb66 JF |
316 | #endif |
317 | ||
1c6969ec | 318 | for_each_possible_cpu(i) |
cb60d114 IC |
319 | memset(per_cpu(cpu_evtchn_mask, i), |
320 | (i == 0) ? ~0 : 0, sizeof(*per_cpu(cpu_evtchn_mask, i))); | |
e46cdb66 JF |
321 | } |
322 | ||
e46cdb66 JF |
323 | static inline void clear_evtchn(int port) |
324 | { | |
325 | struct shared_info *s = HYPERVISOR_shared_info; | |
326 | sync_clear_bit(port, &s->evtchn_pending[0]); | |
327 | } | |
328 | ||
329 | static inline void set_evtchn(int port) | |
330 | { | |
331 | struct shared_info *s = HYPERVISOR_shared_info; | |
332 | sync_set_bit(port, &s->evtchn_pending[0]); | |
333 | } | |
334 | ||
168d2f46 JF |
335 | static inline int test_evtchn(int port) |
336 | { | |
337 | struct shared_info *s = HYPERVISOR_shared_info; | |
338 | return sync_test_bit(port, &s->evtchn_pending[0]); | |
339 | } | |
340 | ||
e46cdb66 JF |
341 | |
342 | /** | |
343 | * notify_remote_via_irq - send event to remote end of event channel via irq | |
344 | * @irq: irq of event channel to send event to | |
345 | * | |
346 | * Unlike notify_remote_via_evtchn(), this is safe to use across | |
347 | * save/restore. Notifications on a broken connection are silently | |
348 | * dropped. | |
349 | */ | |
350 | void notify_remote_via_irq(int irq) | |
351 | { | |
352 | int evtchn = evtchn_from_irq(irq); | |
353 | ||
354 | if (VALID_EVTCHN(evtchn)) | |
355 | notify_remote_via_evtchn(evtchn); | |
356 | } | |
357 | EXPORT_SYMBOL_GPL(notify_remote_via_irq); | |
358 | ||
359 | static void mask_evtchn(int port) | |
360 | { | |
361 | struct shared_info *s = HYPERVISOR_shared_info; | |
362 | sync_set_bit(port, &s->evtchn_mask[0]); | |
363 | } | |
364 | ||
365 | static void unmask_evtchn(int port) | |
366 | { | |
367 | struct shared_info *s = HYPERVISOR_shared_info; | |
368 | unsigned int cpu = get_cpu(); | |
369 | ||
370 | BUG_ON(!irqs_disabled()); | |
371 | ||
372 | /* Slow path (hypercall) if this is a non-local port. */ | |
373 | if (unlikely(cpu != cpu_from_evtchn(port))) { | |
374 | struct evtchn_unmask unmask = { .port = port }; | |
375 | (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask); | |
376 | } else { | |
780f36d8 | 377 | struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu); |
e46cdb66 JF |
378 | |
379 | sync_clear_bit(port, &s->evtchn_mask[0]); | |
380 | ||
381 | /* | |
382 | * The following is basically the equivalent of | |
383 | * 'hw_resend_irq'. Just like a real IO-APIC we 'lose | |
384 | * the interrupt edge' if the channel is masked. | |
385 | */ | |
386 | if (sync_test_bit(port, &s->evtchn_pending[0]) && | |
387 | !sync_test_and_set_bit(port / BITS_PER_LONG, | |
388 | &vcpu_info->evtchn_pending_sel)) | |
389 | vcpu_info->evtchn_upcall_pending = 1; | |
390 | } | |
391 | ||
392 | put_cpu(); | |
393 | } | |
394 | ||
6cb6537d IC |
395 | static void xen_irq_init(unsigned irq) |
396 | { | |
397 | struct irq_info *info; | |
b5328cd1 | 398 | #ifdef CONFIG_SMP |
6cb6537d IC |
399 | struct irq_desc *desc = irq_to_desc(irq); |
400 | ||
401 | /* By default all event channels notify CPU#0. */ | |
402 | cpumask_copy(desc->irq_data.affinity, cpumask_of(0)); | |
44626e4a | 403 | #endif |
6cb6537d | 404 | |
ca62ce8c IC |
405 | info = kzalloc(sizeof(*info), GFP_KERNEL); |
406 | if (info == NULL) | |
407 | panic("Unable to allocate metadata for IRQ%d\n", irq); | |
6cb6537d IC |
408 | |
409 | info->type = IRQT_UNBOUND; | |
410 | ||
c442b806 | 411 | irq_set_handler_data(irq, info); |
ca62ce8c | 412 | |
6cb6537d IC |
413 | list_add_tail(&info->list, &xen_irq_list_head); |
414 | } | |
415 | ||
7bee9768 | 416 | static int __must_check xen_allocate_irq_dynamic(void) |
0794bfc7 | 417 | { |
89911501 IC |
418 | int first = 0; |
419 | int irq; | |
0794bfc7 KRW |
420 | |
421 | #ifdef CONFIG_X86_IO_APIC | |
89911501 IC |
422 | /* |
423 | * For an HVM guest or domain 0 which see "real" (emulated or | |
25985edc | 424 | * actual respectively) GSIs we allocate dynamic IRQs |
89911501 IC |
425 | * e.g. those corresponding to event channels or MSIs |
426 | * etc. from the range above those "real" GSIs to avoid | |
427 | * collisions. | |
428 | */ | |
429 | if (xen_initial_domain() || xen_hvm_domain()) | |
430 | first = get_nr_irqs_gsi(); | |
0794bfc7 KRW |
431 | #endif |
432 | ||
89911501 | 433 | irq = irq_alloc_desc_from(first, -1); |
3a69e916 | 434 | |
e6599225 KRW |
435 | if (irq >= 0) |
436 | xen_irq_init(irq); | |
ced40d0f | 437 | |
e46cdb66 | 438 | return irq; |
d46a78b0 JF |
439 | } |
440 | ||
7bee9768 | 441 | static int __must_check xen_allocate_irq_gsi(unsigned gsi) |
c9df1ce5 IC |
442 | { |
443 | int irq; | |
444 | ||
89911501 IC |
445 | /* |
446 | * A PV guest has no concept of a GSI (since it has no ACPI | |
447 | * nor access to/knowledge of the physical APICs). Therefore | |
448 | * all IRQs are dynamically allocated from the entire IRQ | |
449 | * space. | |
450 | */ | |
451 | if (xen_pv_domain() && !xen_initial_domain()) | |
c9df1ce5 IC |
452 | return xen_allocate_irq_dynamic(); |
453 | ||
454 | /* Legacy IRQ descriptors are already allocated by the arch. */ | |
455 | if (gsi < NR_IRQS_LEGACY) | |
6cb6537d IC |
456 | irq = gsi; |
457 | else | |
458 | irq = irq_alloc_desc_at(gsi, -1); | |
c9df1ce5 | 459 | |
6cb6537d | 460 | xen_irq_init(irq); |
c9df1ce5 IC |
461 | |
462 | return irq; | |
463 | } | |
464 | ||
465 | static void xen_free_irq(unsigned irq) | |
466 | { | |
c442b806 | 467 | struct irq_info *info = irq_get_handler_data(irq); |
6cb6537d IC |
468 | |
469 | list_del(&info->list); | |
9158c358 | 470 | |
c442b806 | 471 | irq_set_handler_data(irq, NULL); |
ca62ce8c IC |
472 | |
473 | kfree(info); | |
474 | ||
72146104 IC |
475 | /* Legacy IRQ descriptors are managed by the arch. */ |
476 | if (irq < NR_IRQS_LEGACY) | |
477 | return; | |
478 | ||
c9df1ce5 IC |
479 | irq_free_desc(irq); |
480 | } | |
481 | ||
d46a78b0 JF |
482 | static void pirq_query_unmask(int irq) |
483 | { | |
484 | struct physdev_irq_status_query irq_status; | |
485 | struct irq_info *info = info_for_irq(irq); | |
486 | ||
487 | BUG_ON(info->type != IRQT_PIRQ); | |
488 | ||
7a043f11 | 489 | irq_status.irq = pirq_from_irq(irq); |
d46a78b0 JF |
490 | if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status)) |
491 | irq_status.flags = 0; | |
492 | ||
493 | info->u.pirq.flags &= ~PIRQ_NEEDS_EOI; | |
494 | if (irq_status.flags & XENIRQSTAT_needs_eoi) | |
495 | info->u.pirq.flags |= PIRQ_NEEDS_EOI; | |
496 | } | |
497 | ||
498 | static bool probing_irq(int irq) | |
499 | { | |
500 | struct irq_desc *desc = irq_to_desc(irq); | |
501 | ||
502 | return desc && desc->action == NULL; | |
503 | } | |
504 | ||
7e186bdd SS |
505 | static void eoi_pirq(struct irq_data *data) |
506 | { | |
507 | int evtchn = evtchn_from_irq(data->irq); | |
508 | struct physdev_eoi eoi = { .irq = pirq_from_irq(data->irq) }; | |
509 | int rc = 0; | |
510 | ||
511 | irq_move_irq(data); | |
512 | ||
513 | if (VALID_EVTCHN(evtchn)) | |
514 | clear_evtchn(evtchn); | |
515 | ||
516 | if (pirq_needs_eoi(data->irq)) { | |
517 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi); | |
518 | WARN_ON(rc); | |
519 | } | |
520 | } | |
521 | ||
522 | static void mask_ack_pirq(struct irq_data *data) | |
523 | { | |
524 | disable_dynirq(data); | |
525 | eoi_pirq(data); | |
526 | } | |
527 | ||
c9e265e0 | 528 | static unsigned int __startup_pirq(unsigned int irq) |
d46a78b0 JF |
529 | { |
530 | struct evtchn_bind_pirq bind_pirq; | |
531 | struct irq_info *info = info_for_irq(irq); | |
532 | int evtchn = evtchn_from_irq(irq); | |
15ebbb82 | 533 | int rc; |
d46a78b0 JF |
534 | |
535 | BUG_ON(info->type != IRQT_PIRQ); | |
536 | ||
537 | if (VALID_EVTCHN(evtchn)) | |
538 | goto out; | |
539 | ||
7a043f11 | 540 | bind_pirq.pirq = pirq_from_irq(irq); |
d46a78b0 | 541 | /* NB. We are happy to share unless we are probing. */ |
15ebbb82 KRW |
542 | bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ? |
543 | BIND_PIRQ__WILL_SHARE : 0; | |
544 | rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq); | |
545 | if (rc != 0) { | |
d46a78b0 JF |
546 | if (!probing_irq(irq)) |
547 | printk(KERN_INFO "Failed to obtain physical IRQ %d\n", | |
548 | irq); | |
549 | return 0; | |
550 | } | |
551 | evtchn = bind_pirq.port; | |
552 | ||
553 | pirq_query_unmask(irq); | |
554 | ||
555 | evtchn_to_irq[evtchn] = irq; | |
556 | bind_evtchn_to_cpu(evtchn, 0); | |
557 | info->evtchn = evtchn; | |
558 | ||
559 | out: | |
560 | unmask_evtchn(evtchn); | |
7e186bdd | 561 | eoi_pirq(irq_get_irq_data(irq)); |
d46a78b0 JF |
562 | |
563 | return 0; | |
564 | } | |
565 | ||
c9e265e0 TG |
566 | static unsigned int startup_pirq(struct irq_data *data) |
567 | { | |
568 | return __startup_pirq(data->irq); | |
569 | } | |
570 | ||
571 | static void shutdown_pirq(struct irq_data *data) | |
d46a78b0 JF |
572 | { |
573 | struct evtchn_close close; | |
c9e265e0 | 574 | unsigned int irq = data->irq; |
d46a78b0 JF |
575 | struct irq_info *info = info_for_irq(irq); |
576 | int evtchn = evtchn_from_irq(irq); | |
577 | ||
578 | BUG_ON(info->type != IRQT_PIRQ); | |
579 | ||
580 | if (!VALID_EVTCHN(evtchn)) | |
581 | return; | |
582 | ||
583 | mask_evtchn(evtchn); | |
584 | ||
585 | close.port = evtchn; | |
586 | if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0) | |
587 | BUG(); | |
588 | ||
589 | bind_evtchn_to_cpu(evtchn, 0); | |
590 | evtchn_to_irq[evtchn] = -1; | |
591 | info->evtchn = 0; | |
592 | } | |
593 | ||
c9e265e0 | 594 | static void enable_pirq(struct irq_data *data) |
d46a78b0 | 595 | { |
c9e265e0 | 596 | startup_pirq(data); |
d46a78b0 JF |
597 | } |
598 | ||
c9e265e0 | 599 | static void disable_pirq(struct irq_data *data) |
d46a78b0 | 600 | { |
7e186bdd | 601 | disable_dynirq(data); |
d46a78b0 JF |
602 | } |
603 | ||
d46a78b0 JF |
604 | static int find_irq_by_gsi(unsigned gsi) |
605 | { | |
6cb6537d | 606 | struct irq_info *info; |
d46a78b0 | 607 | |
6cb6537d IC |
608 | list_for_each_entry(info, &xen_irq_list_head, list) { |
609 | if (info->type != IRQT_PIRQ) | |
d46a78b0 JF |
610 | continue; |
611 | ||
6cb6537d IC |
612 | if (info->u.pirq.gsi == gsi) |
613 | return info->irq; | |
d46a78b0 JF |
614 | } |
615 | ||
616 | return -1; | |
617 | } | |
618 | ||
653378ac IC |
619 | /* |
620 | * Do not make any assumptions regarding the relationship between the | |
621 | * IRQ number returned here and the Xen pirq argument. | |
7a043f11 SS |
622 | * |
623 | * Note: We don't assign an event channel until the irq actually started | |
624 | * up. Return an existing irq if we've already got one for the gsi. | |
e5ac0bda SS |
625 | * |
626 | * Shareable implies level triggered, not shareable implies edge | |
627 | * triggered here. | |
d46a78b0 | 628 | */ |
f4d0635b IC |
629 | int xen_bind_pirq_gsi_to_irq(unsigned gsi, |
630 | unsigned pirq, int shareable, char *name) | |
d46a78b0 | 631 | { |
a0e18116 | 632 | int irq = -1; |
d46a78b0 JF |
633 | struct physdev_irq irq_op; |
634 | ||
77365948 | 635 | mutex_lock(&irq_mapping_update_lock); |
d46a78b0 JF |
636 | |
637 | irq = find_irq_by_gsi(gsi); | |
638 | if (irq != -1) { | |
7a043f11 | 639 | printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n", |
d46a78b0 JF |
640 | irq, gsi); |
641 | goto out; /* XXX need refcount? */ | |
642 | } | |
643 | ||
c9df1ce5 | 644 | irq = xen_allocate_irq_gsi(gsi); |
7bee9768 IC |
645 | if (irq < 0) |
646 | goto out; | |
d46a78b0 | 647 | |
d46a78b0 | 648 | irq_op.irq = irq; |
b5401a96 AN |
649 | irq_op.vector = 0; |
650 | ||
651 | /* Only the privileged domain can do this. For non-priv, the pcifront | |
652 | * driver provides a PCI bus that does the call to do exactly | |
653 | * this in the priv domain. */ | |
654 | if (xen_initial_domain() && | |
655 | HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) { | |
c9df1ce5 | 656 | xen_free_irq(irq); |
d46a78b0 JF |
657 | irq = -ENOSPC; |
658 | goto out; | |
659 | } | |
660 | ||
beafbdc1 | 661 | xen_irq_info_pirq_init(irq, 0, pirq, gsi, irq_op.vector, DOMID_SELF, |
9158c358 | 662 | shareable ? PIRQ_SHAREABLE : 0); |
d46a78b0 | 663 | |
7e186bdd SS |
664 | pirq_query_unmask(irq); |
665 | /* We try to use the handler with the appropriate semantic for the | |
e5ac0bda SS |
666 | * type of interrupt: if the interrupt is an edge triggered |
667 | * interrupt we use handle_edge_irq. | |
7e186bdd | 668 | * |
e5ac0bda SS |
669 | * On the other hand if the interrupt is level triggered we use |
670 | * handle_fasteoi_irq like the native code does for this kind of | |
7e186bdd | 671 | * interrupts. |
e5ac0bda | 672 | * |
7e186bdd SS |
673 | * Depending on the Xen version, pirq_needs_eoi might return true |
674 | * not only for level triggered interrupts but for edge triggered | |
675 | * interrupts too. In any case Xen always honors the eoi mechanism, | |
676 | * not injecting any more pirqs of the same kind if the first one | |
677 | * hasn't received an eoi yet. Therefore using the fasteoi handler | |
678 | * is the right choice either way. | |
679 | */ | |
e5ac0bda | 680 | if (shareable) |
7e186bdd SS |
681 | irq_set_chip_and_handler_name(irq, &xen_pirq_chip, |
682 | handle_fasteoi_irq, name); | |
683 | else | |
684 | irq_set_chip_and_handler_name(irq, &xen_pirq_chip, | |
685 | handle_edge_irq, name); | |
686 | ||
d46a78b0 | 687 | out: |
77365948 | 688 | mutex_unlock(&irq_mapping_update_lock); |
d46a78b0 JF |
689 | |
690 | return irq; | |
691 | } | |
692 | ||
f731e3ef | 693 | #ifdef CONFIG_PCI_MSI |
bf480d95 | 694 | int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc) |
cbf6aa89 | 695 | { |
5cad61a6 | 696 | int rc; |
cbf6aa89 | 697 | struct physdev_get_free_pirq op_get_free_pirq; |
cbf6aa89 | 698 | |
bf480d95 | 699 | op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI; |
cbf6aa89 | 700 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq); |
cbf6aa89 | 701 | |
5cad61a6 IC |
702 | WARN_ONCE(rc == -ENOSYS, |
703 | "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n"); | |
704 | ||
705 | return rc ? -1 : op_get_free_pirq.pirq; | |
cbf6aa89 IC |
706 | } |
707 | ||
bf480d95 | 708 | int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc, |
beafbdc1 KRW |
709 | int pirq, int vector, const char *name, |
710 | domid_t domid) | |
809f9267 | 711 | { |
bf480d95 | 712 | int irq, ret; |
4b41df7f | 713 | |
77365948 | 714 | mutex_lock(&irq_mapping_update_lock); |
809f9267 | 715 | |
4b41df7f | 716 | irq = xen_allocate_irq_dynamic(); |
e6599225 | 717 | if (irq < 0) |
bb5d079a | 718 | goto out; |
809f9267 | 719 | |
7e186bdd SS |
720 | irq_set_chip_and_handler_name(irq, &xen_pirq_chip, handle_edge_irq, |
721 | name); | |
809f9267 | 722 | |
beafbdc1 | 723 | xen_irq_info_pirq_init(irq, 0, pirq, 0, vector, domid, 0); |
5f6fb454 | 724 | ret = irq_set_msi_desc(irq, msidesc); |
bf480d95 IC |
725 | if (ret < 0) |
726 | goto error_irq; | |
809f9267 | 727 | out: |
77365948 | 728 | mutex_unlock(&irq_mapping_update_lock); |
4b41df7f | 729 | return irq; |
bf480d95 | 730 | error_irq: |
77365948 | 731 | mutex_unlock(&irq_mapping_update_lock); |
bf480d95 | 732 | xen_free_irq(irq); |
e6599225 | 733 | return ret; |
809f9267 | 734 | } |
f731e3ef QH |
735 | #endif |
736 | ||
b5401a96 AN |
737 | int xen_destroy_irq(int irq) |
738 | { | |
739 | struct irq_desc *desc; | |
38aa66fc JF |
740 | struct physdev_unmap_pirq unmap_irq; |
741 | struct irq_info *info = info_for_irq(irq); | |
b5401a96 AN |
742 | int rc = -ENOENT; |
743 | ||
77365948 | 744 | mutex_lock(&irq_mapping_update_lock); |
b5401a96 AN |
745 | |
746 | desc = irq_to_desc(irq); | |
747 | if (!desc) | |
748 | goto out; | |
749 | ||
38aa66fc | 750 | if (xen_initial_domain()) { |
12334715 | 751 | unmap_irq.pirq = info->u.pirq.pirq; |
beafbdc1 | 752 | unmap_irq.domid = info->u.pirq.domid; |
38aa66fc | 753 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq); |
1eff1ad0 KRW |
754 | /* If another domain quits without making the pci_disable_msix |
755 | * call, the Xen hypervisor takes care of freeing the PIRQs | |
756 | * (free_domain_pirqs). | |
757 | */ | |
758 | if ((rc == -ESRCH && info->u.pirq.domid != DOMID_SELF)) | |
759 | printk(KERN_INFO "domain %d does not have %d anymore\n", | |
760 | info->u.pirq.domid, info->u.pirq.pirq); | |
761 | else if (rc) { | |
38aa66fc JF |
762 | printk(KERN_WARNING "unmap irq failed %d\n", rc); |
763 | goto out; | |
764 | } | |
765 | } | |
b5401a96 | 766 | |
c9df1ce5 | 767 | xen_free_irq(irq); |
b5401a96 AN |
768 | |
769 | out: | |
77365948 | 770 | mutex_unlock(&irq_mapping_update_lock); |
b5401a96 AN |
771 | return rc; |
772 | } | |
773 | ||
af42b8d1 | 774 | int xen_irq_from_pirq(unsigned pirq) |
d46a78b0 | 775 | { |
69c358ce | 776 | int irq; |
d46a78b0 | 777 | |
69c358ce | 778 | struct irq_info *info; |
e46cdb66 | 779 | |
77365948 | 780 | mutex_lock(&irq_mapping_update_lock); |
69c358ce IC |
781 | |
782 | list_for_each_entry(info, &xen_irq_list_head, list) { | |
9bb9efe4 | 783 | if (info->type != IRQT_PIRQ) |
69c358ce IC |
784 | continue; |
785 | irq = info->irq; | |
786 | if (info->u.pirq.pirq == pirq) | |
787 | goto out; | |
788 | } | |
789 | irq = -1; | |
790 | out: | |
77365948 | 791 | mutex_unlock(&irq_mapping_update_lock); |
69c358ce IC |
792 | |
793 | return irq; | |
af42b8d1 SS |
794 | } |
795 | ||
e6197acc KRW |
796 | |
797 | int xen_pirq_from_irq(unsigned irq) | |
798 | { | |
799 | return pirq_from_irq(irq); | |
800 | } | |
801 | EXPORT_SYMBOL_GPL(xen_pirq_from_irq); | |
b536b4b9 | 802 | int bind_evtchn_to_irq(unsigned int evtchn) |
e46cdb66 JF |
803 | { |
804 | int irq; | |
805 | ||
77365948 | 806 | mutex_lock(&irq_mapping_update_lock); |
e46cdb66 JF |
807 | |
808 | irq = evtchn_to_irq[evtchn]; | |
809 | ||
810 | if (irq == -1) { | |
c9df1ce5 | 811 | irq = xen_allocate_irq_dynamic(); |
7bee9768 IC |
812 | if (irq == -1) |
813 | goto out; | |
e46cdb66 | 814 | |
c442b806 | 815 | irq_set_chip_and_handler_name(irq, &xen_dynamic_chip, |
7e186bdd | 816 | handle_edge_irq, "event"); |
e46cdb66 | 817 | |
9158c358 | 818 | xen_irq_info_evtchn_init(irq, evtchn); |
e46cdb66 JF |
819 | } |
820 | ||
7bee9768 | 821 | out: |
77365948 | 822 | mutex_unlock(&irq_mapping_update_lock); |
e46cdb66 JF |
823 | |
824 | return irq; | |
825 | } | |
b536b4b9 | 826 | EXPORT_SYMBOL_GPL(bind_evtchn_to_irq); |
e46cdb66 | 827 | |
f87e4cac JF |
828 | static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu) |
829 | { | |
830 | struct evtchn_bind_ipi bind_ipi; | |
831 | int evtchn, irq; | |
832 | ||
77365948 | 833 | mutex_lock(&irq_mapping_update_lock); |
f87e4cac JF |
834 | |
835 | irq = per_cpu(ipi_to_irq, cpu)[ipi]; | |
90af9514 | 836 | |
f87e4cac | 837 | if (irq == -1) { |
c9df1ce5 | 838 | irq = xen_allocate_irq_dynamic(); |
f87e4cac JF |
839 | if (irq < 0) |
840 | goto out; | |
841 | ||
c442b806 | 842 | irq_set_chip_and_handler_name(irq, &xen_percpu_chip, |
aaca4964 | 843 | handle_percpu_irq, "ipi"); |
f87e4cac JF |
844 | |
845 | bind_ipi.vcpu = cpu; | |
846 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi, | |
847 | &bind_ipi) != 0) | |
848 | BUG(); | |
849 | evtchn = bind_ipi.port; | |
850 | ||
3d4cfa37 | 851 | xen_irq_info_ipi_init(cpu, irq, evtchn, ipi); |
f87e4cac JF |
852 | |
853 | bind_evtchn_to_cpu(evtchn, cpu); | |
854 | } | |
855 | ||
f87e4cac | 856 | out: |
77365948 | 857 | mutex_unlock(&irq_mapping_update_lock); |
f87e4cac JF |
858 | return irq; |
859 | } | |
860 | ||
2e820f58 IC |
861 | static int bind_interdomain_evtchn_to_irq(unsigned int remote_domain, |
862 | unsigned int remote_port) | |
863 | { | |
864 | struct evtchn_bind_interdomain bind_interdomain; | |
865 | int err; | |
866 | ||
867 | bind_interdomain.remote_dom = remote_domain; | |
868 | bind_interdomain.remote_port = remote_port; | |
869 | ||
870 | err = HYPERVISOR_event_channel_op(EVTCHNOP_bind_interdomain, | |
871 | &bind_interdomain); | |
872 | ||
873 | return err ? : bind_evtchn_to_irq(bind_interdomain.local_port); | |
874 | } | |
875 | ||
62cc5fc7 OH |
876 | static int find_virq(unsigned int virq, unsigned int cpu) |
877 | { | |
878 | struct evtchn_status status; | |
879 | int port, rc = -ENOENT; | |
880 | ||
881 | memset(&status, 0, sizeof(status)); | |
882 | for (port = 0; port <= NR_EVENT_CHANNELS; port++) { | |
883 | status.dom = DOMID_SELF; | |
884 | status.port = port; | |
885 | rc = HYPERVISOR_event_channel_op(EVTCHNOP_status, &status); | |
886 | if (rc < 0) | |
887 | continue; | |
888 | if (status.status != EVTCHNSTAT_virq) | |
889 | continue; | |
890 | if (status.u.virq == virq && status.vcpu == cpu) { | |
891 | rc = port; | |
892 | break; | |
893 | } | |
894 | } | |
895 | return rc; | |
896 | } | |
f87e4cac | 897 | |
4fe7d5a7 | 898 | int bind_virq_to_irq(unsigned int virq, unsigned int cpu) |
e46cdb66 JF |
899 | { |
900 | struct evtchn_bind_virq bind_virq; | |
62cc5fc7 | 901 | int evtchn, irq, ret; |
e46cdb66 | 902 | |
77365948 | 903 | mutex_lock(&irq_mapping_update_lock); |
e46cdb66 JF |
904 | |
905 | irq = per_cpu(virq_to_irq, cpu)[virq]; | |
906 | ||
907 | if (irq == -1) { | |
c9df1ce5 | 908 | irq = xen_allocate_irq_dynamic(); |
7bee9768 IC |
909 | if (irq == -1) |
910 | goto out; | |
a52521f1 | 911 | |
c442b806 | 912 | irq_set_chip_and_handler_name(irq, &xen_percpu_chip, |
a52521f1 JF |
913 | handle_percpu_irq, "virq"); |
914 | ||
e46cdb66 JF |
915 | bind_virq.virq = virq; |
916 | bind_virq.vcpu = cpu; | |
62cc5fc7 OH |
917 | ret = HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq, |
918 | &bind_virq); | |
919 | if (ret == 0) | |
920 | evtchn = bind_virq.port; | |
921 | else { | |
922 | if (ret == -EEXIST) | |
923 | ret = find_virq(virq, cpu); | |
924 | BUG_ON(ret < 0); | |
925 | evtchn = ret; | |
926 | } | |
e46cdb66 | 927 | |
3d4cfa37 | 928 | xen_irq_info_virq_init(cpu, irq, evtchn, virq); |
e46cdb66 JF |
929 | |
930 | bind_evtchn_to_cpu(evtchn, cpu); | |
931 | } | |
932 | ||
7bee9768 | 933 | out: |
77365948 | 934 | mutex_unlock(&irq_mapping_update_lock); |
e46cdb66 JF |
935 | |
936 | return irq; | |
937 | } | |
938 | ||
939 | static void unbind_from_irq(unsigned int irq) | |
940 | { | |
941 | struct evtchn_close close; | |
942 | int evtchn = evtchn_from_irq(irq); | |
943 | ||
77365948 | 944 | mutex_lock(&irq_mapping_update_lock); |
e46cdb66 | 945 | |
d77bbd4d | 946 | if (VALID_EVTCHN(evtchn)) { |
e46cdb66 JF |
947 | close.port = evtchn; |
948 | if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0) | |
949 | BUG(); | |
950 | ||
951 | switch (type_from_irq(irq)) { | |
952 | case IRQT_VIRQ: | |
953 | per_cpu(virq_to_irq, cpu_from_evtchn(evtchn)) | |
ced40d0f | 954 | [virq_from_irq(irq)] = -1; |
e46cdb66 | 955 | break; |
d68d82af AN |
956 | case IRQT_IPI: |
957 | per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn)) | |
ced40d0f | 958 | [ipi_from_irq(irq)] = -1; |
d68d82af | 959 | break; |
e46cdb66 JF |
960 | default: |
961 | break; | |
962 | } | |
963 | ||
964 | /* Closed ports are implicitly re-bound to VCPU0. */ | |
965 | bind_evtchn_to_cpu(evtchn, 0); | |
966 | ||
967 | evtchn_to_irq[evtchn] = -1; | |
fed5ea87 IC |
968 | } |
969 | ||
ca62ce8c | 970 | BUG_ON(info_for_irq(irq)->type == IRQT_UNBOUND); |
e46cdb66 | 971 | |
9158c358 | 972 | xen_free_irq(irq); |
e46cdb66 | 973 | |
77365948 | 974 | mutex_unlock(&irq_mapping_update_lock); |
e46cdb66 JF |
975 | } |
976 | ||
977 | int bind_evtchn_to_irqhandler(unsigned int evtchn, | |
7c239975 | 978 | irq_handler_t handler, |
e46cdb66 JF |
979 | unsigned long irqflags, |
980 | const char *devname, void *dev_id) | |
981 | { | |
361ae8cb | 982 | int irq, retval; |
e46cdb66 JF |
983 | |
984 | irq = bind_evtchn_to_irq(evtchn); | |
7bee9768 IC |
985 | if (irq < 0) |
986 | return irq; | |
e46cdb66 JF |
987 | retval = request_irq(irq, handler, irqflags, devname, dev_id); |
988 | if (retval != 0) { | |
989 | unbind_from_irq(irq); | |
990 | return retval; | |
991 | } | |
992 | ||
993 | return irq; | |
994 | } | |
995 | EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler); | |
996 | ||
2e820f58 IC |
997 | int bind_interdomain_evtchn_to_irqhandler(unsigned int remote_domain, |
998 | unsigned int remote_port, | |
999 | irq_handler_t handler, | |
1000 | unsigned long irqflags, | |
1001 | const char *devname, | |
1002 | void *dev_id) | |
1003 | { | |
1004 | int irq, retval; | |
1005 | ||
1006 | irq = bind_interdomain_evtchn_to_irq(remote_domain, remote_port); | |
1007 | if (irq < 0) | |
1008 | return irq; | |
1009 | ||
1010 | retval = request_irq(irq, handler, irqflags, devname, dev_id); | |
1011 | if (retval != 0) { | |
1012 | unbind_from_irq(irq); | |
1013 | return retval; | |
1014 | } | |
1015 | ||
1016 | return irq; | |
1017 | } | |
1018 | EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irqhandler); | |
1019 | ||
e46cdb66 | 1020 | int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu, |
7c239975 | 1021 | irq_handler_t handler, |
e46cdb66 JF |
1022 | unsigned long irqflags, const char *devname, void *dev_id) |
1023 | { | |
361ae8cb | 1024 | int irq, retval; |
e46cdb66 JF |
1025 | |
1026 | irq = bind_virq_to_irq(virq, cpu); | |
7bee9768 IC |
1027 | if (irq < 0) |
1028 | return irq; | |
e46cdb66 JF |
1029 | retval = request_irq(irq, handler, irqflags, devname, dev_id); |
1030 | if (retval != 0) { | |
1031 | unbind_from_irq(irq); | |
1032 | return retval; | |
1033 | } | |
1034 | ||
1035 | return irq; | |
1036 | } | |
1037 | EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler); | |
1038 | ||
f87e4cac JF |
1039 | int bind_ipi_to_irqhandler(enum ipi_vector ipi, |
1040 | unsigned int cpu, | |
1041 | irq_handler_t handler, | |
1042 | unsigned long irqflags, | |
1043 | const char *devname, | |
1044 | void *dev_id) | |
1045 | { | |
1046 | int irq, retval; | |
1047 | ||
1048 | irq = bind_ipi_to_irq(ipi, cpu); | |
1049 | if (irq < 0) | |
1050 | return irq; | |
1051 | ||
676dc3cf | 1052 | irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME; |
f87e4cac JF |
1053 | retval = request_irq(irq, handler, irqflags, devname, dev_id); |
1054 | if (retval != 0) { | |
1055 | unbind_from_irq(irq); | |
1056 | return retval; | |
1057 | } | |
1058 | ||
1059 | return irq; | |
1060 | } | |
1061 | ||
e46cdb66 JF |
1062 | void unbind_from_irqhandler(unsigned int irq, void *dev_id) |
1063 | { | |
1064 | free_irq(irq, dev_id); | |
1065 | unbind_from_irq(irq); | |
1066 | } | |
1067 | EXPORT_SYMBOL_GPL(unbind_from_irqhandler); | |
1068 | ||
f87e4cac JF |
1069 | void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector) |
1070 | { | |
1071 | int irq = per_cpu(ipi_to_irq, cpu)[vector]; | |
1072 | BUG_ON(irq < 0); | |
1073 | notify_remote_via_irq(irq); | |
1074 | } | |
1075 | ||
ee523ca1 JF |
1076 | irqreturn_t xen_debug_interrupt(int irq, void *dev_id) |
1077 | { | |
1078 | struct shared_info *sh = HYPERVISOR_shared_info; | |
1079 | int cpu = smp_processor_id(); | |
cb60d114 | 1080 | unsigned long *cpu_evtchn = per_cpu(cpu_evtchn_mask, cpu); |
ee523ca1 JF |
1081 | int i; |
1082 | unsigned long flags; | |
1083 | static DEFINE_SPINLOCK(debug_lock); | |
cb52e6d9 | 1084 | struct vcpu_info *v; |
ee523ca1 JF |
1085 | |
1086 | spin_lock_irqsave(&debug_lock, flags); | |
1087 | ||
cb52e6d9 | 1088 | printk("\nvcpu %d\n ", cpu); |
ee523ca1 JF |
1089 | |
1090 | for_each_online_cpu(i) { | |
cb52e6d9 IC |
1091 | int pending; |
1092 | v = per_cpu(xen_vcpu, i); | |
1093 | pending = (get_irq_regs() && i == cpu) | |
1094 | ? xen_irqs_disabled(get_irq_regs()) | |
1095 | : v->evtchn_upcall_mask; | |
1096 | printk("%d: masked=%d pending=%d event_sel %0*lx\n ", i, | |
1097 | pending, v->evtchn_upcall_pending, | |
1098 | (int)(sizeof(v->evtchn_pending_sel)*2), | |
1099 | v->evtchn_pending_sel); | |
1100 | } | |
1101 | v = per_cpu(xen_vcpu, cpu); | |
1102 | ||
1103 | printk("\npending:\n "); | |
1104 | for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--) | |
1105 | printk("%0*lx%s", (int)sizeof(sh->evtchn_pending[0])*2, | |
1106 | sh->evtchn_pending[i], | |
1107 | i % 8 == 0 ? "\n " : " "); | |
1108 | printk("\nglobal mask:\n "); | |
1109 | for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) | |
1110 | printk("%0*lx%s", | |
1111 | (int)(sizeof(sh->evtchn_mask[0])*2), | |
1112 | sh->evtchn_mask[i], | |
1113 | i % 8 == 0 ? "\n " : " "); | |
1114 | ||
1115 | printk("\nglobally unmasked:\n "); | |
1116 | for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) | |
1117 | printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2), | |
1118 | sh->evtchn_pending[i] & ~sh->evtchn_mask[i], | |
1119 | i % 8 == 0 ? "\n " : " "); | |
1120 | ||
1121 | printk("\nlocal cpu%d mask:\n ", cpu); | |
1122 | for (i = (NR_EVENT_CHANNELS/BITS_PER_LONG)-1; i >= 0; i--) | |
1123 | printk("%0*lx%s", (int)(sizeof(cpu_evtchn[0])*2), | |
1124 | cpu_evtchn[i], | |
1125 | i % 8 == 0 ? "\n " : " "); | |
1126 | ||
1127 | printk("\nlocally unmasked:\n "); | |
1128 | for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) { | |
1129 | unsigned long pending = sh->evtchn_pending[i] | |
1130 | & ~sh->evtchn_mask[i] | |
1131 | & cpu_evtchn[i]; | |
1132 | printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2), | |
1133 | pending, i % 8 == 0 ? "\n " : " "); | |
ee523ca1 | 1134 | } |
ee523ca1 JF |
1135 | |
1136 | printk("\npending list:\n"); | |
cb52e6d9 | 1137 | for (i = 0; i < NR_EVENT_CHANNELS; i++) { |
ee523ca1 | 1138 | if (sync_test_bit(i, sh->evtchn_pending)) { |
cb52e6d9 IC |
1139 | int word_idx = i / BITS_PER_LONG; |
1140 | printk(" %d: event %d -> irq %d%s%s%s\n", | |
ced40d0f | 1141 | cpu_from_evtchn(i), i, |
cb52e6d9 IC |
1142 | evtchn_to_irq[i], |
1143 | sync_test_bit(word_idx, &v->evtchn_pending_sel) | |
1144 | ? "" : " l2-clear", | |
1145 | !sync_test_bit(i, sh->evtchn_mask) | |
1146 | ? "" : " globally-masked", | |
1147 | sync_test_bit(i, cpu_evtchn) | |
1148 | ? "" : " locally-masked"); | |
ee523ca1 JF |
1149 | } |
1150 | } | |
1151 | ||
1152 | spin_unlock_irqrestore(&debug_lock, flags); | |
1153 | ||
1154 | return IRQ_HANDLED; | |
1155 | } | |
1156 | ||
245b2e70 | 1157 | static DEFINE_PER_CPU(unsigned, xed_nesting_count); |
ada6814c KF |
1158 | static DEFINE_PER_CPU(unsigned int, current_word_idx); |
1159 | static DEFINE_PER_CPU(unsigned int, current_bit_idx); | |
245b2e70 | 1160 | |
ab7f863e SR |
1161 | /* |
1162 | * Mask out the i least significant bits of w | |
1163 | */ | |
1164 | #define MASK_LSBS(w, i) (w & ((~0UL) << i)) | |
245b2e70 | 1165 | |
e46cdb66 JF |
1166 | /* |
1167 | * Search the CPUs pending events bitmasks. For each one found, map | |
1168 | * the event number to an irq, and feed it into do_IRQ() for | |
1169 | * handling. | |
1170 | * | |
1171 | * Xen uses a two-level bitmap to speed searching. The first level is | |
1172 | * a bitset of words which contain pending event bits. The second | |
1173 | * level is a bitset of pending events themselves. | |
1174 | */ | |
38e20b07 | 1175 | static void __xen_evtchn_do_upcall(void) |
e46cdb66 | 1176 | { |
24b51c2f | 1177 | int start_word_idx, start_bit_idx; |
ab7f863e | 1178 | int word_idx, bit_idx; |
24b51c2f | 1179 | int i; |
e46cdb66 JF |
1180 | int cpu = get_cpu(); |
1181 | struct shared_info *s = HYPERVISOR_shared_info; | |
780f36d8 | 1182 | struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu); |
229664be | 1183 | unsigned count; |
e46cdb66 | 1184 | |
229664be JF |
1185 | do { |
1186 | unsigned long pending_words; | |
e46cdb66 | 1187 | |
229664be | 1188 | vcpu_info->evtchn_upcall_pending = 0; |
e46cdb66 | 1189 | |
b2e4ae69 | 1190 | if (__this_cpu_inc_return(xed_nesting_count) - 1) |
229664be | 1191 | goto out; |
e46cdb66 | 1192 | |
e849c3e9 IY |
1193 | #ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */ |
1194 | /* Clear master flag /before/ clearing selector flag. */ | |
6673cf63 | 1195 | wmb(); |
e849c3e9 | 1196 | #endif |
229664be | 1197 | pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0); |
ab7f863e | 1198 | |
24b51c2f KF |
1199 | start_word_idx = __this_cpu_read(current_word_idx); |
1200 | start_bit_idx = __this_cpu_read(current_bit_idx); | |
1201 | ||
1202 | word_idx = start_word_idx; | |
ab7f863e | 1203 | |
24b51c2f | 1204 | for (i = 0; pending_words != 0; i++) { |
229664be | 1205 | unsigned long pending_bits; |
ab7f863e | 1206 | unsigned long words; |
229664be | 1207 | |
ab7f863e SR |
1208 | words = MASK_LSBS(pending_words, word_idx); |
1209 | ||
1210 | /* | |
ada6814c | 1211 | * If we masked out all events, wrap to beginning. |
ab7f863e SR |
1212 | */ |
1213 | if (words == 0) { | |
ada6814c KF |
1214 | word_idx = 0; |
1215 | bit_idx = 0; | |
ab7f863e SR |
1216 | continue; |
1217 | } | |
1218 | word_idx = __ffs(words); | |
229664be | 1219 | |
24b51c2f KF |
1220 | pending_bits = active_evtchns(cpu, s, word_idx); |
1221 | bit_idx = 0; /* usually scan entire word from start */ | |
1222 | if (word_idx == start_word_idx) { | |
1223 | /* We scan the starting word in two parts */ | |
1224 | if (i == 0) | |
1225 | /* 1st time: start in the middle */ | |
1226 | bit_idx = start_bit_idx; | |
1227 | else | |
1228 | /* 2nd time: mask bits done already */ | |
1229 | bit_idx &= (1UL << start_bit_idx) - 1; | |
1230 | } | |
1231 | ||
ab7f863e SR |
1232 | do { |
1233 | unsigned long bits; | |
1234 | int port, irq; | |
ca4dbc66 | 1235 | struct irq_desc *desc; |
229664be | 1236 | |
ab7f863e SR |
1237 | bits = MASK_LSBS(pending_bits, bit_idx); |
1238 | ||
1239 | /* If we masked out all events, move on. */ | |
ada6814c | 1240 | if (bits == 0) |
ab7f863e | 1241 | break; |
ab7f863e SR |
1242 | |
1243 | bit_idx = __ffs(bits); | |
1244 | ||
1245 | /* Process port. */ | |
1246 | port = (word_idx * BITS_PER_LONG) + bit_idx; | |
1247 | irq = evtchn_to_irq[port]; | |
1248 | ||
ca4dbc66 EB |
1249 | if (irq != -1) { |
1250 | desc = irq_to_desc(irq); | |
1251 | if (desc) | |
1252 | generic_handle_irq_desc(irq, desc); | |
1253 | } | |
ab7f863e | 1254 | |
ada6814c KF |
1255 | bit_idx = (bit_idx + 1) % BITS_PER_LONG; |
1256 | ||
1257 | /* Next caller starts at last processed + 1 */ | |
1258 | __this_cpu_write(current_word_idx, | |
1259 | bit_idx ? word_idx : | |
1260 | (word_idx+1) % BITS_PER_LONG); | |
1261 | __this_cpu_write(current_bit_idx, bit_idx); | |
1262 | } while (bit_idx != 0); | |
ab7f863e | 1263 | |
24b51c2f KF |
1264 | /* Scan start_l1i twice; all others once. */ |
1265 | if ((word_idx != start_word_idx) || (i != 0)) | |
ab7f863e | 1266 | pending_words &= ~(1UL << word_idx); |
ada6814c KF |
1267 | |
1268 | word_idx = (word_idx + 1) % BITS_PER_LONG; | |
e46cdb66 | 1269 | } |
e46cdb66 | 1270 | |
229664be JF |
1271 | BUG_ON(!irqs_disabled()); |
1272 | ||
780f36d8 CL |
1273 | count = __this_cpu_read(xed_nesting_count); |
1274 | __this_cpu_write(xed_nesting_count, 0); | |
183d03cc | 1275 | } while (count != 1 || vcpu_info->evtchn_upcall_pending); |
229664be JF |
1276 | |
1277 | out: | |
38e20b07 SY |
1278 | |
1279 | put_cpu(); | |
1280 | } | |
1281 | ||
1282 | void xen_evtchn_do_upcall(struct pt_regs *regs) | |
1283 | { | |
1284 | struct pt_regs *old_regs = set_irq_regs(regs); | |
1285 | ||
1286 | exit_idle(); | |
1287 | irq_enter(); | |
1288 | ||
1289 | __xen_evtchn_do_upcall(); | |
1290 | ||
3445a8fd JF |
1291 | irq_exit(); |
1292 | set_irq_regs(old_regs); | |
38e20b07 | 1293 | } |
3445a8fd | 1294 | |
38e20b07 SY |
1295 | void xen_hvm_evtchn_do_upcall(void) |
1296 | { | |
1297 | __xen_evtchn_do_upcall(); | |
e46cdb66 | 1298 | } |
183d03cc | 1299 | EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall); |
e46cdb66 | 1300 | |
eb1e305f JF |
1301 | /* Rebind a new event channel to an existing irq. */ |
1302 | void rebind_evtchn_irq(int evtchn, int irq) | |
1303 | { | |
d77bbd4d JF |
1304 | struct irq_info *info = info_for_irq(irq); |
1305 | ||
eb1e305f JF |
1306 | /* Make sure the irq is masked, since the new event channel |
1307 | will also be masked. */ | |
1308 | disable_irq(irq); | |
1309 | ||
77365948 | 1310 | mutex_lock(&irq_mapping_update_lock); |
eb1e305f JF |
1311 | |
1312 | /* After resume the irq<->evtchn mappings are all cleared out */ | |
1313 | BUG_ON(evtchn_to_irq[evtchn] != -1); | |
1314 | /* Expect irq to have been bound before, | |
d77bbd4d JF |
1315 | so there should be a proper type */ |
1316 | BUG_ON(info->type == IRQT_UNBOUND); | |
eb1e305f | 1317 | |
9158c358 | 1318 | xen_irq_info_evtchn_init(irq, evtchn); |
eb1e305f | 1319 | |
77365948 | 1320 | mutex_unlock(&irq_mapping_update_lock); |
eb1e305f JF |
1321 | |
1322 | /* new event channels are always bound to cpu 0 */ | |
0de26520 | 1323 | irq_set_affinity(irq, cpumask_of(0)); |
eb1e305f JF |
1324 | |
1325 | /* Unmask the event channel. */ | |
1326 | enable_irq(irq); | |
1327 | } | |
1328 | ||
e46cdb66 | 1329 | /* Rebind an evtchn so that it gets delivered to a specific cpu */ |
d5dedd45 | 1330 | static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu) |
e46cdb66 JF |
1331 | { |
1332 | struct evtchn_bind_vcpu bind_vcpu; | |
1333 | int evtchn = evtchn_from_irq(irq); | |
1334 | ||
be49472f IC |
1335 | if (!VALID_EVTCHN(evtchn)) |
1336 | return -1; | |
1337 | ||
1338 | /* | |
1339 | * Events delivered via platform PCI interrupts are always | |
1340 | * routed to vcpu 0 and hence cannot be rebound. | |
1341 | */ | |
1342 | if (xen_hvm_domain() && !xen_have_vector_callback) | |
d5dedd45 | 1343 | return -1; |
e46cdb66 JF |
1344 | |
1345 | /* Send future instances of this interrupt to other vcpu. */ | |
1346 | bind_vcpu.port = evtchn; | |
1347 | bind_vcpu.vcpu = tcpu; | |
1348 | ||
1349 | /* | |
1350 | * If this fails, it usually just indicates that we're dealing with a | |
1351 | * virq or IPI channel, which don't actually need to be rebound. Ignore | |
1352 | * it, but don't do the xenlinux-level rebind in that case. | |
1353 | */ | |
1354 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0) | |
1355 | bind_evtchn_to_cpu(evtchn, tcpu); | |
e46cdb66 | 1356 | |
d5dedd45 YL |
1357 | return 0; |
1358 | } | |
e46cdb66 | 1359 | |
c9e265e0 TG |
1360 | static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest, |
1361 | bool force) | |
e46cdb66 | 1362 | { |
0de26520 | 1363 | unsigned tcpu = cpumask_first(dest); |
d5dedd45 | 1364 | |
c9e265e0 | 1365 | return rebind_irq_to_cpu(data->irq, tcpu); |
e46cdb66 JF |
1366 | } |
1367 | ||
642e0c88 IY |
1368 | int resend_irq_on_evtchn(unsigned int irq) |
1369 | { | |
1370 | int masked, evtchn = evtchn_from_irq(irq); | |
1371 | struct shared_info *s = HYPERVISOR_shared_info; | |
1372 | ||
1373 | if (!VALID_EVTCHN(evtchn)) | |
1374 | return 1; | |
1375 | ||
1376 | masked = sync_test_and_set_bit(evtchn, s->evtchn_mask); | |
1377 | sync_set_bit(evtchn, s->evtchn_pending); | |
1378 | if (!masked) | |
1379 | unmask_evtchn(evtchn); | |
1380 | ||
1381 | return 1; | |
1382 | } | |
1383 | ||
c9e265e0 | 1384 | static void enable_dynirq(struct irq_data *data) |
e46cdb66 | 1385 | { |
c9e265e0 | 1386 | int evtchn = evtchn_from_irq(data->irq); |
e46cdb66 JF |
1387 | |
1388 | if (VALID_EVTCHN(evtchn)) | |
1389 | unmask_evtchn(evtchn); | |
1390 | } | |
1391 | ||
c9e265e0 | 1392 | static void disable_dynirq(struct irq_data *data) |
e46cdb66 | 1393 | { |
c9e265e0 | 1394 | int evtchn = evtchn_from_irq(data->irq); |
e46cdb66 JF |
1395 | |
1396 | if (VALID_EVTCHN(evtchn)) | |
1397 | mask_evtchn(evtchn); | |
1398 | } | |
1399 | ||
c9e265e0 | 1400 | static void ack_dynirq(struct irq_data *data) |
e46cdb66 | 1401 | { |
c9e265e0 | 1402 | int evtchn = evtchn_from_irq(data->irq); |
e46cdb66 | 1403 | |
7e186bdd | 1404 | irq_move_irq(data); |
e46cdb66 JF |
1405 | |
1406 | if (VALID_EVTCHN(evtchn)) | |
7e186bdd SS |
1407 | clear_evtchn(evtchn); |
1408 | } | |
1409 | ||
1410 | static void mask_ack_dynirq(struct irq_data *data) | |
1411 | { | |
1412 | disable_dynirq(data); | |
1413 | ack_dynirq(data); | |
e46cdb66 JF |
1414 | } |
1415 | ||
c9e265e0 | 1416 | static int retrigger_dynirq(struct irq_data *data) |
e46cdb66 | 1417 | { |
c9e265e0 | 1418 | int evtchn = evtchn_from_irq(data->irq); |
ee8fa1c6 | 1419 | struct shared_info *sh = HYPERVISOR_shared_info; |
e46cdb66 JF |
1420 | int ret = 0; |
1421 | ||
1422 | if (VALID_EVTCHN(evtchn)) { | |
ee8fa1c6 JF |
1423 | int masked; |
1424 | ||
1425 | masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask); | |
1426 | sync_set_bit(evtchn, sh->evtchn_pending); | |
1427 | if (!masked) | |
1428 | unmask_evtchn(evtchn); | |
e46cdb66 JF |
1429 | ret = 1; |
1430 | } | |
1431 | ||
1432 | return ret; | |
1433 | } | |
1434 | ||
0a85226f | 1435 | static void restore_pirqs(void) |
9a069c33 SS |
1436 | { |
1437 | int pirq, rc, irq, gsi; | |
1438 | struct physdev_map_pirq map_irq; | |
69c358ce | 1439 | struct irq_info *info; |
9a069c33 | 1440 | |
69c358ce IC |
1441 | list_for_each_entry(info, &xen_irq_list_head, list) { |
1442 | if (info->type != IRQT_PIRQ) | |
9a069c33 SS |
1443 | continue; |
1444 | ||
69c358ce IC |
1445 | pirq = info->u.pirq.pirq; |
1446 | gsi = info->u.pirq.gsi; | |
1447 | irq = info->irq; | |
1448 | ||
9a069c33 SS |
1449 | /* save/restore of PT devices doesn't work, so at this point the |
1450 | * only devices present are GSI based emulated devices */ | |
9a069c33 SS |
1451 | if (!gsi) |
1452 | continue; | |
1453 | ||
1454 | map_irq.domid = DOMID_SELF; | |
1455 | map_irq.type = MAP_PIRQ_TYPE_GSI; | |
1456 | map_irq.index = gsi; | |
1457 | map_irq.pirq = pirq; | |
1458 | ||
1459 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq); | |
1460 | if (rc) { | |
1461 | printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n", | |
1462 | gsi, irq, pirq, rc); | |
9158c358 | 1463 | xen_free_irq(irq); |
9a069c33 SS |
1464 | continue; |
1465 | } | |
1466 | ||
1467 | printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq); | |
1468 | ||
c9e265e0 | 1469 | __startup_pirq(irq); |
9a069c33 SS |
1470 | } |
1471 | } | |
1472 | ||
0e91398f JF |
1473 | static void restore_cpu_virqs(unsigned int cpu) |
1474 | { | |
1475 | struct evtchn_bind_virq bind_virq; | |
1476 | int virq, irq, evtchn; | |
1477 | ||
1478 | for (virq = 0; virq < NR_VIRQS; virq++) { | |
1479 | if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1) | |
1480 | continue; | |
1481 | ||
ced40d0f | 1482 | BUG_ON(virq_from_irq(irq) != virq); |
0e91398f JF |
1483 | |
1484 | /* Get a new binding from Xen. */ | |
1485 | bind_virq.virq = virq; | |
1486 | bind_virq.vcpu = cpu; | |
1487 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq, | |
1488 | &bind_virq) != 0) | |
1489 | BUG(); | |
1490 | evtchn = bind_virq.port; | |
1491 | ||
1492 | /* Record the new mapping. */ | |
3d4cfa37 | 1493 | xen_irq_info_virq_init(cpu, irq, evtchn, virq); |
0e91398f | 1494 | bind_evtchn_to_cpu(evtchn, cpu); |
0e91398f JF |
1495 | } |
1496 | } | |
1497 | ||
1498 | static void restore_cpu_ipis(unsigned int cpu) | |
1499 | { | |
1500 | struct evtchn_bind_ipi bind_ipi; | |
1501 | int ipi, irq, evtchn; | |
1502 | ||
1503 | for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) { | |
1504 | if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1) | |
1505 | continue; | |
1506 | ||
ced40d0f | 1507 | BUG_ON(ipi_from_irq(irq) != ipi); |
0e91398f JF |
1508 | |
1509 | /* Get a new binding from Xen. */ | |
1510 | bind_ipi.vcpu = cpu; | |
1511 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi, | |
1512 | &bind_ipi) != 0) | |
1513 | BUG(); | |
1514 | evtchn = bind_ipi.port; | |
1515 | ||
1516 | /* Record the new mapping. */ | |
3d4cfa37 | 1517 | xen_irq_info_ipi_init(cpu, irq, evtchn, ipi); |
0e91398f | 1518 | bind_evtchn_to_cpu(evtchn, cpu); |
0e91398f JF |
1519 | } |
1520 | } | |
1521 | ||
2d9e1e2f JF |
1522 | /* Clear an irq's pending state, in preparation for polling on it */ |
1523 | void xen_clear_irq_pending(int irq) | |
1524 | { | |
1525 | int evtchn = evtchn_from_irq(irq); | |
1526 | ||
1527 | if (VALID_EVTCHN(evtchn)) | |
1528 | clear_evtchn(evtchn); | |
1529 | } | |
d9a8814f | 1530 | EXPORT_SYMBOL(xen_clear_irq_pending); |
168d2f46 JF |
1531 | void xen_set_irq_pending(int irq) |
1532 | { | |
1533 | int evtchn = evtchn_from_irq(irq); | |
1534 | ||
1535 | if (VALID_EVTCHN(evtchn)) | |
1536 | set_evtchn(evtchn); | |
1537 | } | |
1538 | ||
1539 | bool xen_test_irq_pending(int irq) | |
1540 | { | |
1541 | int evtchn = evtchn_from_irq(irq); | |
1542 | bool ret = false; | |
1543 | ||
1544 | if (VALID_EVTCHN(evtchn)) | |
1545 | ret = test_evtchn(evtchn); | |
1546 | ||
1547 | return ret; | |
1548 | } | |
1549 | ||
d9a8814f KRW |
1550 | /* Poll waiting for an irq to become pending with timeout. In the usual case, |
1551 | * the irq will be disabled so it won't deliver an interrupt. */ | |
1552 | void xen_poll_irq_timeout(int irq, u64 timeout) | |
2d9e1e2f JF |
1553 | { |
1554 | evtchn_port_t evtchn = evtchn_from_irq(irq); | |
1555 | ||
1556 | if (VALID_EVTCHN(evtchn)) { | |
1557 | struct sched_poll poll; | |
1558 | ||
1559 | poll.nr_ports = 1; | |
d9a8814f | 1560 | poll.timeout = timeout; |
ff3c5362 | 1561 | set_xen_guest_handle(poll.ports, &evtchn); |
2d9e1e2f JF |
1562 | |
1563 | if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0) | |
1564 | BUG(); | |
1565 | } | |
1566 | } | |
d9a8814f KRW |
1567 | EXPORT_SYMBOL(xen_poll_irq_timeout); |
1568 | /* Poll waiting for an irq to become pending. In the usual case, the | |
1569 | * irq will be disabled so it won't deliver an interrupt. */ | |
1570 | void xen_poll_irq(int irq) | |
1571 | { | |
1572 | xen_poll_irq_timeout(irq, 0 /* no timeout */); | |
1573 | } | |
2d9e1e2f | 1574 | |
c7c2c3a2 KRW |
1575 | /* Check whether the IRQ line is shared with other guests. */ |
1576 | int xen_test_irq_shared(int irq) | |
1577 | { | |
1578 | struct irq_info *info = info_for_irq(irq); | |
1579 | struct physdev_irq_status_query irq_status = { .irq = info->u.pirq.pirq }; | |
1580 | ||
1581 | if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status)) | |
1582 | return 0; | |
1583 | return !(irq_status.flags & XENIRQSTAT_shared); | |
1584 | } | |
1585 | EXPORT_SYMBOL_GPL(xen_test_irq_shared); | |
1586 | ||
0e91398f JF |
1587 | void xen_irq_resume(void) |
1588 | { | |
6cb6537d IC |
1589 | unsigned int cpu, evtchn; |
1590 | struct irq_info *info; | |
0e91398f JF |
1591 | |
1592 | init_evtchn_cpu_bindings(); | |
1593 | ||
1594 | /* New event-channel space is not 'live' yet. */ | |
1595 | for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++) | |
1596 | mask_evtchn(evtchn); | |
1597 | ||
1598 | /* No IRQ <-> event-channel mappings. */ | |
6cb6537d IC |
1599 | list_for_each_entry(info, &xen_irq_list_head, list) |
1600 | info->evtchn = 0; /* zap event-channel binding */ | |
0e91398f JF |
1601 | |
1602 | for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++) | |
1603 | evtchn_to_irq[evtchn] = -1; | |
1604 | ||
1605 | for_each_possible_cpu(cpu) { | |
1606 | restore_cpu_virqs(cpu); | |
1607 | restore_cpu_ipis(cpu); | |
1608 | } | |
6903591f | 1609 | |
0a85226f | 1610 | restore_pirqs(); |
0e91398f JF |
1611 | } |
1612 | ||
e46cdb66 | 1613 | static struct irq_chip xen_dynamic_chip __read_mostly = { |
c9e265e0 | 1614 | .name = "xen-dyn", |
54a353a0 | 1615 | |
c9e265e0 TG |
1616 | .irq_disable = disable_dynirq, |
1617 | .irq_mask = disable_dynirq, | |
1618 | .irq_unmask = enable_dynirq, | |
54a353a0 | 1619 | |
7e186bdd SS |
1620 | .irq_ack = ack_dynirq, |
1621 | .irq_mask_ack = mask_ack_dynirq, | |
1622 | ||
c9e265e0 TG |
1623 | .irq_set_affinity = set_affinity_irq, |
1624 | .irq_retrigger = retrigger_dynirq, | |
e46cdb66 JF |
1625 | }; |
1626 | ||
d46a78b0 | 1627 | static struct irq_chip xen_pirq_chip __read_mostly = { |
c9e265e0 | 1628 | .name = "xen-pirq", |
d46a78b0 | 1629 | |
c9e265e0 TG |
1630 | .irq_startup = startup_pirq, |
1631 | .irq_shutdown = shutdown_pirq, | |
c9e265e0 | 1632 | .irq_enable = enable_pirq, |
c9e265e0 | 1633 | .irq_disable = disable_pirq, |
d46a78b0 | 1634 | |
7e186bdd SS |
1635 | .irq_mask = disable_dynirq, |
1636 | .irq_unmask = enable_dynirq, | |
1637 | ||
1638 | .irq_ack = eoi_pirq, | |
1639 | .irq_eoi = eoi_pirq, | |
1640 | .irq_mask_ack = mask_ack_pirq, | |
d46a78b0 | 1641 | |
c9e265e0 | 1642 | .irq_set_affinity = set_affinity_irq, |
d46a78b0 | 1643 | |
c9e265e0 | 1644 | .irq_retrigger = retrigger_dynirq, |
d46a78b0 JF |
1645 | }; |
1646 | ||
aaca4964 | 1647 | static struct irq_chip xen_percpu_chip __read_mostly = { |
c9e265e0 | 1648 | .name = "xen-percpu", |
aaca4964 | 1649 | |
c9e265e0 TG |
1650 | .irq_disable = disable_dynirq, |
1651 | .irq_mask = disable_dynirq, | |
1652 | .irq_unmask = enable_dynirq, | |
aaca4964 | 1653 | |
c9e265e0 | 1654 | .irq_ack = ack_dynirq, |
aaca4964 JF |
1655 | }; |
1656 | ||
38e20b07 SY |
1657 | int xen_set_callback_via(uint64_t via) |
1658 | { | |
1659 | struct xen_hvm_param a; | |
1660 | a.domid = DOMID_SELF; | |
1661 | a.index = HVM_PARAM_CALLBACK_IRQ; | |
1662 | a.value = via; | |
1663 | return HYPERVISOR_hvm_op(HVMOP_set_param, &a); | |
1664 | } | |
1665 | EXPORT_SYMBOL_GPL(xen_set_callback_via); | |
1666 | ||
ca65f9fc | 1667 | #ifdef CONFIG_XEN_PVHVM |
38e20b07 SY |
1668 | /* Vector callbacks are better than PCI interrupts to receive event |
1669 | * channel notifications because we can receive vector callbacks on any | |
1670 | * vcpu and we don't need PCI support or APIC interactions. */ | |
1671 | void xen_callback_vector(void) | |
1672 | { | |
1673 | int rc; | |
1674 | uint64_t callback_via; | |
1675 | if (xen_have_vector_callback) { | |
1676 | callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK); | |
1677 | rc = xen_set_callback_via(callback_via); | |
1678 | if (rc) { | |
1679 | printk(KERN_ERR "Request for Xen HVM callback vector" | |
1680 | " failed.\n"); | |
1681 | xen_have_vector_callback = 0; | |
1682 | return; | |
1683 | } | |
1684 | printk(KERN_INFO "Xen HVM callback vector for event delivery is " | |
1685 | "enabled\n"); | |
1686 | /* in the restore case the vector has already been allocated */ | |
1687 | if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors)) | |
1688 | alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector); | |
1689 | } | |
1690 | } | |
ca65f9fc SS |
1691 | #else |
1692 | void xen_callback_vector(void) {} | |
1693 | #endif | |
38e20b07 | 1694 | |
e46cdb66 JF |
1695 | void __init xen_init_IRQ(void) |
1696 | { | |
e5fc7345 | 1697 | int i; |
c7a3589e | 1698 | |
b21ddbf5 JF |
1699 | evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq), |
1700 | GFP_KERNEL); | |
9d093e29 | 1701 | BUG_ON(!evtchn_to_irq); |
b21ddbf5 JF |
1702 | for (i = 0; i < NR_EVENT_CHANNELS; i++) |
1703 | evtchn_to_irq[i] = -1; | |
e46cdb66 JF |
1704 | |
1705 | init_evtchn_cpu_bindings(); | |
1706 | ||
1707 | /* No event channels are 'live' right now. */ | |
1708 | for (i = 0; i < NR_EVENT_CHANNELS; i++) | |
1709 | mask_evtchn(i); | |
1710 | ||
38e20b07 SY |
1711 | if (xen_hvm_domain()) { |
1712 | xen_callback_vector(); | |
1713 | native_init_IRQ(); | |
3942b740 SS |
1714 | /* pci_xen_hvm_init must be called after native_init_IRQ so that |
1715 | * __acpi_register_gsi can point at the right function */ | |
1716 | pci_xen_hvm_init(); | |
38e20b07 SY |
1717 | } else { |
1718 | irq_ctx_init(smp_processor_id()); | |
38aa66fc | 1719 | if (xen_initial_domain()) |
a0ee0567 | 1720 | pci_xen_initial_domain(); |
38e20b07 | 1721 | } |
e46cdb66 | 1722 | } |