xen: events: rename restore_cpu_pirqs -> restore_pirqs
[deliverable/linux.git] / drivers / xen / events.c
CommitLineData
e46cdb66
JF
1/*
2 * Xen event channels
3 *
4 * Xen models interrupts with abstract event channels. Because each
5 * domain gets 1024 event channels, but NR_IRQ is not that large, we
6 * must dynamically map irqs<->event channels. The event channels
7 * interface with the rest of the kernel by defining a xen interrupt
8 * chip. When an event is recieved, it is mapped to an irq and sent
9 * through the normal interrupt processing path.
10 *
11 * There are four kinds of events which can be mapped to an event
12 * channel:
13 *
14 * 1. Inter-domain notifications. This includes all the virtual
15 * device events, since they're driven by front-ends in another domain
16 * (typically dom0).
17 * 2. VIRQs, typically used for timers. These are per-cpu events.
18 * 3. IPIs.
d46a78b0 19 * 4. PIRQs - Hardware interrupts.
e46cdb66
JF
20 *
21 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
22 */
23
24#include <linux/linkage.h>
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/module.h>
28#include <linux/string.h>
28e08861 29#include <linux/bootmem.h>
5a0e3ad6 30#include <linux/slab.h>
b21ddbf5 31#include <linux/irqnr.h>
f731e3ef 32#include <linux/pci.h>
e46cdb66 33
38e20b07 34#include <asm/desc.h>
e46cdb66
JF
35#include <asm/ptrace.h>
36#include <asm/irq.h>
792dc4f6 37#include <asm/idle.h>
0794bfc7 38#include <asm/io_apic.h>
e46cdb66 39#include <asm/sync_bitops.h>
42a1de56 40#include <asm/xen/pci.h>
e46cdb66 41#include <asm/xen/hypercall.h>
8d1b8753 42#include <asm/xen/hypervisor.h>
e46cdb66 43
38e20b07
SY
44#include <xen/xen.h>
45#include <xen/hvm.h>
e04d0d07 46#include <xen/xen-ops.h>
e46cdb66
JF
47#include <xen/events.h>
48#include <xen/interface/xen.h>
49#include <xen/interface/event_channel.h>
38e20b07
SY
50#include <xen/interface/hvm/hvm_op.h>
51#include <xen/interface/hvm/params.h>
e46cdb66 52
e46cdb66
JF
53/*
54 * This lock protects updates to the following mapping and reference-count
55 * arrays. The lock does not need to be acquired to read the mapping tables.
56 */
57static DEFINE_SPINLOCK(irq_mapping_update_lock);
58
59/* IRQ <-> VIRQ mapping. */
204fba4a 60static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
e46cdb66 61
f87e4cac 62/* IRQ <-> IPI mapping */
204fba4a 63static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
f87e4cac 64
ced40d0f
JF
65/* Interrupt types. */
66enum xen_irq_type {
d77bbd4d 67 IRQT_UNBOUND = 0,
f87e4cac
JF
68 IRQT_PIRQ,
69 IRQT_VIRQ,
70 IRQT_IPI,
71 IRQT_EVTCHN
72};
e46cdb66 73
ced40d0f
JF
74/*
75 * Packed IRQ information:
76 * type - enum xen_irq_type
77 * event channel - irq->event channel mapping
78 * cpu - cpu this event channel is bound to
79 * index - type-specific information:
42a1de56
SS
80 * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM
81 * guest, or GSI (real passthrough IRQ) of the device.
ced40d0f
JF
82 * VIRQ - virq number
83 * IPI - IPI vector
84 * EVTCHN -
85 */
86struct irq_info
87{
88 enum xen_irq_type type; /* type */
89 unsigned short evtchn; /* event channel */
90 unsigned short cpu; /* cpu bound */
91
92 union {
93 unsigned short virq;
94 enum ipi_vector ipi;
95 struct {
7a043f11 96 unsigned short pirq;
ced40d0f 97 unsigned short gsi;
d46a78b0
JF
98 unsigned char vector;
99 unsigned char flags;
ced40d0f
JF
100 } pirq;
101 } u;
102};
d46a78b0 103#define PIRQ_NEEDS_EOI (1 << 0)
15ebbb82 104#define PIRQ_SHAREABLE (1 << 1)
ced40d0f 105
b21ddbf5 106static struct irq_info *irq_info;
7a043f11 107static int *pirq_to_irq;
e46cdb66 108
b21ddbf5 109static int *evtchn_to_irq;
c7a3589e
MT
110struct cpu_evtchn_s {
111 unsigned long bits[NR_EVENT_CHANNELS/BITS_PER_LONG];
112};
3b32f574
JF
113
114static __initdata struct cpu_evtchn_s init_evtchn_mask = {
115 .bits[0 ... (NR_EVENT_CHANNELS/BITS_PER_LONG)-1] = ~0ul,
116};
117static struct cpu_evtchn_s *cpu_evtchn_mask_p = &init_evtchn_mask;
118
c7a3589e
MT
119static inline unsigned long *cpu_evtchn_mask(int cpu)
120{
121 return cpu_evtchn_mask_p[cpu].bits;
122}
e46cdb66 123
e46cdb66
JF
124/* Xen will never allocate port zero for any purpose. */
125#define VALID_EVTCHN(chn) ((chn) != 0)
126
e46cdb66 127static struct irq_chip xen_dynamic_chip;
aaca4964 128static struct irq_chip xen_percpu_chip;
d46a78b0 129static struct irq_chip xen_pirq_chip;
e46cdb66
JF
130
131/* Constructor for packed IRQ information. */
ced40d0f
JF
132static struct irq_info mk_unbound_info(void)
133{
134 return (struct irq_info) { .type = IRQT_UNBOUND };
135}
136
137static struct irq_info mk_evtchn_info(unsigned short evtchn)
138{
90af9514
IC
139 return (struct irq_info) { .type = IRQT_EVTCHN, .evtchn = evtchn,
140 .cpu = 0 };
ced40d0f
JF
141}
142
143static struct irq_info mk_ipi_info(unsigned short evtchn, enum ipi_vector ipi)
e46cdb66 144{
ced40d0f 145 return (struct irq_info) { .type = IRQT_IPI, .evtchn = evtchn,
90af9514 146 .cpu = 0, .u.ipi = ipi };
ced40d0f
JF
147}
148
149static struct irq_info mk_virq_info(unsigned short evtchn, unsigned short virq)
150{
151 return (struct irq_info) { .type = IRQT_VIRQ, .evtchn = evtchn,
90af9514 152 .cpu = 0, .u.virq = virq };
ced40d0f
JF
153}
154
7a043f11 155static struct irq_info mk_pirq_info(unsigned short evtchn, unsigned short pirq,
ced40d0f
JF
156 unsigned short gsi, unsigned short vector)
157{
158 return (struct irq_info) { .type = IRQT_PIRQ, .evtchn = evtchn,
7a043f11
SS
159 .cpu = 0,
160 .u.pirq = { .pirq = pirq, .gsi = gsi, .vector = vector } };
e46cdb66
JF
161}
162
163/*
164 * Accessors for packed IRQ information.
165 */
ced40d0f 166static struct irq_info *info_for_irq(unsigned irq)
e46cdb66 167{
ced40d0f 168 return &irq_info[irq];
e46cdb66
JF
169}
170
ced40d0f 171static unsigned int evtchn_from_irq(unsigned irq)
e46cdb66 172{
110e7c7e
JJ
173 if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
174 return 0;
175
ced40d0f 176 return info_for_irq(irq)->evtchn;
e46cdb66
JF
177}
178
d4c04536
IC
179unsigned irq_from_evtchn(unsigned int evtchn)
180{
181 return evtchn_to_irq[evtchn];
182}
183EXPORT_SYMBOL_GPL(irq_from_evtchn);
184
ced40d0f 185static enum ipi_vector ipi_from_irq(unsigned irq)
e46cdb66 186{
ced40d0f
JF
187 struct irq_info *info = info_for_irq(irq);
188
189 BUG_ON(info == NULL);
190 BUG_ON(info->type != IRQT_IPI);
191
192 return info->u.ipi;
193}
194
195static unsigned virq_from_irq(unsigned irq)
196{
197 struct irq_info *info = info_for_irq(irq);
198
199 BUG_ON(info == NULL);
200 BUG_ON(info->type != IRQT_VIRQ);
201
202 return info->u.virq;
203}
204
7a043f11
SS
205static unsigned pirq_from_irq(unsigned irq)
206{
207 struct irq_info *info = info_for_irq(irq);
208
209 BUG_ON(info == NULL);
210 BUG_ON(info->type != IRQT_PIRQ);
211
212 return info->u.pirq.pirq;
213}
214
ced40d0f
JF
215static unsigned gsi_from_irq(unsigned irq)
216{
217 struct irq_info *info = info_for_irq(irq);
218
219 BUG_ON(info == NULL);
220 BUG_ON(info->type != IRQT_PIRQ);
221
222 return info->u.pirq.gsi;
223}
224
ced40d0f
JF
225static enum xen_irq_type type_from_irq(unsigned irq)
226{
227 return info_for_irq(irq)->type;
228}
229
230static unsigned cpu_from_irq(unsigned irq)
231{
232 return info_for_irq(irq)->cpu;
233}
234
235static unsigned int cpu_from_evtchn(unsigned int evtchn)
236{
237 int irq = evtchn_to_irq[evtchn];
238 unsigned ret = 0;
239
240 if (irq != -1)
241 ret = cpu_from_irq(irq);
242
243 return ret;
e46cdb66
JF
244}
245
d46a78b0
JF
246static bool pirq_needs_eoi(unsigned irq)
247{
248 struct irq_info *info = info_for_irq(irq);
249
250 BUG_ON(info->type != IRQT_PIRQ);
251
252 return info->u.pirq.flags & PIRQ_NEEDS_EOI;
253}
254
e46cdb66
JF
255static inline unsigned long active_evtchns(unsigned int cpu,
256 struct shared_info *sh,
257 unsigned int idx)
258{
259 return (sh->evtchn_pending[idx] &
c7a3589e 260 cpu_evtchn_mask(cpu)[idx] &
e46cdb66
JF
261 ~sh->evtchn_mask[idx]);
262}
263
264static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
265{
266 int irq = evtchn_to_irq[chn];
267
268 BUG_ON(irq == -1);
269#ifdef CONFIG_SMP
c9e265e0 270 cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu));
e46cdb66
JF
271#endif
272
e0419564
JF
273 clear_bit(chn, cpu_evtchn_mask(cpu_from_irq(irq)));
274 set_bit(chn, cpu_evtchn_mask(cpu));
e46cdb66 275
ced40d0f 276 irq_info[irq].cpu = cpu;
e46cdb66
JF
277}
278
279static void init_evtchn_cpu_bindings(void)
280{
1c6969ec 281 int i;
e46cdb66 282#ifdef CONFIG_SMP
10e58084 283 struct irq_desc *desc;
10e58084 284
e46cdb66 285 /* By default all event channels notify CPU#0. */
0b8f1efa 286 for_each_irq_desc(i, desc) {
c9e265e0 287 cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
0b8f1efa 288 }
e46cdb66
JF
289#endif
290
1c6969ec
JB
291 for_each_possible_cpu(i)
292 memset(cpu_evtchn_mask(i),
293 (i == 0) ? ~0 : 0, sizeof(struct cpu_evtchn_s));
294
e46cdb66
JF
295}
296
e46cdb66
JF
297static inline void clear_evtchn(int port)
298{
299 struct shared_info *s = HYPERVISOR_shared_info;
300 sync_clear_bit(port, &s->evtchn_pending[0]);
301}
302
303static inline void set_evtchn(int port)
304{
305 struct shared_info *s = HYPERVISOR_shared_info;
306 sync_set_bit(port, &s->evtchn_pending[0]);
307}
308
168d2f46
JF
309static inline int test_evtchn(int port)
310{
311 struct shared_info *s = HYPERVISOR_shared_info;
312 return sync_test_bit(port, &s->evtchn_pending[0]);
313}
314
e46cdb66
JF
315
316/**
317 * notify_remote_via_irq - send event to remote end of event channel via irq
318 * @irq: irq of event channel to send event to
319 *
320 * Unlike notify_remote_via_evtchn(), this is safe to use across
321 * save/restore. Notifications on a broken connection are silently
322 * dropped.
323 */
324void notify_remote_via_irq(int irq)
325{
326 int evtchn = evtchn_from_irq(irq);
327
328 if (VALID_EVTCHN(evtchn))
329 notify_remote_via_evtchn(evtchn);
330}
331EXPORT_SYMBOL_GPL(notify_remote_via_irq);
332
333static void mask_evtchn(int port)
334{
335 struct shared_info *s = HYPERVISOR_shared_info;
336 sync_set_bit(port, &s->evtchn_mask[0]);
337}
338
339static void unmask_evtchn(int port)
340{
341 struct shared_info *s = HYPERVISOR_shared_info;
342 unsigned int cpu = get_cpu();
343
344 BUG_ON(!irqs_disabled());
345
346 /* Slow path (hypercall) if this is a non-local port. */
347 if (unlikely(cpu != cpu_from_evtchn(port))) {
348 struct evtchn_unmask unmask = { .port = port };
349 (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
350 } else {
780f36d8 351 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
e46cdb66
JF
352
353 sync_clear_bit(port, &s->evtchn_mask[0]);
354
355 /*
356 * The following is basically the equivalent of
357 * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
358 * the interrupt edge' if the channel is masked.
359 */
360 if (sync_test_bit(port, &s->evtchn_pending[0]) &&
361 !sync_test_and_set_bit(port / BITS_PER_LONG,
362 &vcpu_info->evtchn_pending_sel))
363 vcpu_info->evtchn_upcall_pending = 1;
364 }
365
366 put_cpu();
367}
368
89911501 369static int xen_allocate_irq_dynamic(void)
0794bfc7 370{
89911501
IC
371 int first = 0;
372 int irq;
0794bfc7
KRW
373
374#ifdef CONFIG_X86_IO_APIC
89911501
IC
375 /*
376 * For an HVM guest or domain 0 which see "real" (emulated or
377 * actual repectively) GSIs we allocate dynamic IRQs
378 * e.g. those corresponding to event channels or MSIs
379 * etc. from the range above those "real" GSIs to avoid
380 * collisions.
381 */
382 if (xen_initial_domain() || xen_hvm_domain())
383 first = get_nr_irqs_gsi();
0794bfc7
KRW
384#endif
385
89911501
IC
386retry:
387 irq = irq_alloc_desc_from(first, -1);
3a69e916 388
89911501
IC
389 if (irq == -ENOMEM && first > NR_IRQS_LEGACY) {
390 printk(KERN_ERR "Out of dynamic IRQ space and eating into GSI space. You should increase nr_irqs\n");
391 first = max(NR_IRQS_LEGACY, first - NR_IRQS_LEGACY);
392 goto retry;
99ad198c 393 }
e46cdb66 394
89911501
IC
395 if (irq < 0)
396 panic("No available IRQ to bind to: increase nr_irqs!\n");
ced40d0f 397
e46cdb66 398 return irq;
d46a78b0
JF
399}
400
c9df1ce5
IC
401static int xen_allocate_irq_gsi(unsigned gsi)
402{
403 int irq;
404
89911501
IC
405 /*
406 * A PV guest has no concept of a GSI (since it has no ACPI
407 * nor access to/knowledge of the physical APICs). Therefore
408 * all IRQs are dynamically allocated from the entire IRQ
409 * space.
410 */
411 if (xen_pv_domain() && !xen_initial_domain())
c9df1ce5
IC
412 return xen_allocate_irq_dynamic();
413
414 /* Legacy IRQ descriptors are already allocated by the arch. */
415 if (gsi < NR_IRQS_LEGACY)
416 return gsi;
417
418 irq = irq_alloc_desc_at(gsi, -1);
419 if (irq < 0)
420 panic("Unable to allocate to IRQ%d (%d)\n", gsi, irq);
421
422 return irq;
423}
424
425static void xen_free_irq(unsigned irq)
426{
72146104
IC
427 /* Legacy IRQ descriptors are managed by the arch. */
428 if (irq < NR_IRQS_LEGACY)
429 return;
430
c9df1ce5
IC
431 irq_free_desc(irq);
432}
433
d46a78b0
JF
434static void pirq_unmask_notify(int irq)
435{
7a043f11 436 struct physdev_eoi eoi = { .irq = pirq_from_irq(irq) };
d46a78b0
JF
437
438 if (unlikely(pirq_needs_eoi(irq))) {
439 int rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
440 WARN_ON(rc);
441 }
442}
443
444static void pirq_query_unmask(int irq)
445{
446 struct physdev_irq_status_query irq_status;
447 struct irq_info *info = info_for_irq(irq);
448
449 BUG_ON(info->type != IRQT_PIRQ);
450
7a043f11 451 irq_status.irq = pirq_from_irq(irq);
d46a78b0
JF
452 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
453 irq_status.flags = 0;
454
455 info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
456 if (irq_status.flags & XENIRQSTAT_needs_eoi)
457 info->u.pirq.flags |= PIRQ_NEEDS_EOI;
458}
459
460static bool probing_irq(int irq)
461{
462 struct irq_desc *desc = irq_to_desc(irq);
463
464 return desc && desc->action == NULL;
465}
466
c9e265e0 467static unsigned int __startup_pirq(unsigned int irq)
d46a78b0
JF
468{
469 struct evtchn_bind_pirq bind_pirq;
470 struct irq_info *info = info_for_irq(irq);
471 int evtchn = evtchn_from_irq(irq);
15ebbb82 472 int rc;
d46a78b0
JF
473
474 BUG_ON(info->type != IRQT_PIRQ);
475
476 if (VALID_EVTCHN(evtchn))
477 goto out;
478
7a043f11 479 bind_pirq.pirq = pirq_from_irq(irq);
d46a78b0 480 /* NB. We are happy to share unless we are probing. */
15ebbb82
KRW
481 bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
482 BIND_PIRQ__WILL_SHARE : 0;
483 rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
484 if (rc != 0) {
d46a78b0
JF
485 if (!probing_irq(irq))
486 printk(KERN_INFO "Failed to obtain physical IRQ %d\n",
487 irq);
488 return 0;
489 }
490 evtchn = bind_pirq.port;
491
492 pirq_query_unmask(irq);
493
494 evtchn_to_irq[evtchn] = irq;
495 bind_evtchn_to_cpu(evtchn, 0);
496 info->evtchn = evtchn;
497
498out:
499 unmask_evtchn(evtchn);
500 pirq_unmask_notify(irq);
501
502 return 0;
503}
504
c9e265e0
TG
505static unsigned int startup_pirq(struct irq_data *data)
506{
507 return __startup_pirq(data->irq);
508}
509
510static void shutdown_pirq(struct irq_data *data)
d46a78b0
JF
511{
512 struct evtchn_close close;
c9e265e0 513 unsigned int irq = data->irq;
d46a78b0
JF
514 struct irq_info *info = info_for_irq(irq);
515 int evtchn = evtchn_from_irq(irq);
516
517 BUG_ON(info->type != IRQT_PIRQ);
518
519 if (!VALID_EVTCHN(evtchn))
520 return;
521
522 mask_evtchn(evtchn);
523
524 close.port = evtchn;
525 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
526 BUG();
527
528 bind_evtchn_to_cpu(evtchn, 0);
529 evtchn_to_irq[evtchn] = -1;
530 info->evtchn = 0;
531}
532
c9e265e0 533static void enable_pirq(struct irq_data *data)
d46a78b0 534{
c9e265e0 535 startup_pirq(data);
d46a78b0
JF
536}
537
c9e265e0 538static void disable_pirq(struct irq_data *data)
d46a78b0
JF
539{
540}
541
c9e265e0 542static void ack_pirq(struct irq_data *data)
d46a78b0 543{
c9e265e0 544 int evtchn = evtchn_from_irq(data->irq);
d46a78b0 545
aa673c1c 546 move_native_irq(data->irq);
d46a78b0
JF
547
548 if (VALID_EVTCHN(evtchn)) {
549 mask_evtchn(evtchn);
550 clear_evtchn(evtchn);
551 }
552}
553
d46a78b0
JF
554static int find_irq_by_gsi(unsigned gsi)
555{
556 int irq;
557
b21ddbf5 558 for (irq = 0; irq < nr_irqs; irq++) {
d46a78b0
JF
559 struct irq_info *info = info_for_irq(irq);
560
561 if (info == NULL || info->type != IRQT_PIRQ)
562 continue;
563
564 if (gsi_from_irq(irq) == gsi)
565 return irq;
566 }
567
568 return -1;
569}
570
7a043f11
SS
571int xen_allocate_pirq(unsigned gsi, int shareable, char *name)
572{
573 return xen_map_pirq_gsi(gsi, gsi, shareable, name);
574}
575
653378ac
IC
576/*
577 * Do not make any assumptions regarding the relationship between the
578 * IRQ number returned here and the Xen pirq argument.
7a043f11
SS
579 *
580 * Note: We don't assign an event channel until the irq actually started
581 * up. Return an existing irq if we've already got one for the gsi.
d46a78b0 582 */
7a043f11 583int xen_map_pirq_gsi(unsigned pirq, unsigned gsi, int shareable, char *name)
d46a78b0 584{
a0e18116 585 int irq = -1;
d46a78b0
JF
586 struct physdev_irq irq_op;
587
588 spin_lock(&irq_mapping_update_lock);
589
e5fc7345 590 if ((pirq > nr_irqs) || (gsi > nr_irqs)) {
01557baf 591 printk(KERN_WARNING "xen_map_pirq_gsi: %s %s is incorrect!\n",
e5fc7345
SS
592 pirq > nr_irqs ? "pirq" :"",
593 gsi > nr_irqs ? "gsi" : "");
01557baf
SS
594 goto out;
595 }
596
d46a78b0
JF
597 irq = find_irq_by_gsi(gsi);
598 if (irq != -1) {
7a043f11 599 printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n",
d46a78b0
JF
600 irq, gsi);
601 goto out; /* XXX need refcount? */
602 }
603
c9df1ce5 604 irq = xen_allocate_irq_gsi(gsi);
d46a78b0
JF
605
606 set_irq_chip_and_handler_name(irq, &xen_pirq_chip,
1a60d05f 607 handle_level_irq, name);
d46a78b0
JF
608
609 irq_op.irq = irq;
b5401a96
AN
610 irq_op.vector = 0;
611
612 /* Only the privileged domain can do this. For non-priv, the pcifront
613 * driver provides a PCI bus that does the call to do exactly
614 * this in the priv domain. */
615 if (xen_initial_domain() &&
616 HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
c9df1ce5 617 xen_free_irq(irq);
d46a78b0
JF
618 irq = -ENOSPC;
619 goto out;
620 }
621
7a043f11 622 irq_info[irq] = mk_pirq_info(0, pirq, gsi, irq_op.vector);
15ebbb82 623 irq_info[irq].u.pirq.flags |= shareable ? PIRQ_SHAREABLE : 0;
7a043f11 624 pirq_to_irq[pirq] = irq;
d46a78b0
JF
625
626out:
627 spin_unlock(&irq_mapping_update_lock);
628
629 return irq;
630}
631
f731e3ef 632#ifdef CONFIG_PCI_MSI
bf480d95 633int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc)
cbf6aa89 634{
5cad61a6 635 int rc;
cbf6aa89 636 struct physdev_get_free_pirq op_get_free_pirq;
cbf6aa89 637
bf480d95 638 op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI;
cbf6aa89 639 rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
cbf6aa89 640
5cad61a6
IC
641 WARN_ONCE(rc == -ENOSYS,
642 "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n");
643
644 return rc ? -1 : op_get_free_pirq.pirq;
cbf6aa89
IC
645}
646
bf480d95 647int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc,
ca1d8fe9 648 int pirq, int vector, const char *name)
809f9267 649{
bf480d95 650 int irq, ret;
4b41df7f 651
809f9267
SS
652 spin_lock(&irq_mapping_update_lock);
653
4b41df7f
IC
654 irq = xen_allocate_irq_dynamic();
655 if (irq == -1)
bb5d079a 656 goto out;
809f9267 657
4b41df7f 658 set_irq_chip_and_handler_name(irq, &xen_pirq_chip,
809f9267
SS
659 handle_level_irq, name);
660
ca1d8fe9 661 irq_info[irq] = mk_pirq_info(0, pirq, 0, vector);
bf480d95
IC
662 pirq_to_irq[pirq] = irq;
663 ret = set_irq_msi(irq, msidesc);
664 if (ret < 0)
665 goto error_irq;
809f9267
SS
666out:
667 spin_unlock(&irq_mapping_update_lock);
4b41df7f 668 return irq;
bf480d95
IC
669error_irq:
670 spin_unlock(&irq_mapping_update_lock);
671 xen_free_irq(irq);
672 return -1;
809f9267 673}
f731e3ef
QH
674#endif
675
b5401a96
AN
676int xen_destroy_irq(int irq)
677{
678 struct irq_desc *desc;
38aa66fc
JF
679 struct physdev_unmap_pirq unmap_irq;
680 struct irq_info *info = info_for_irq(irq);
b5401a96
AN
681 int rc = -ENOENT;
682
683 spin_lock(&irq_mapping_update_lock);
684
685 desc = irq_to_desc(irq);
686 if (!desc)
687 goto out;
688
38aa66fc 689 if (xen_initial_domain()) {
12334715 690 unmap_irq.pirq = info->u.pirq.pirq;
38aa66fc
JF
691 unmap_irq.domid = DOMID_SELF;
692 rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
693 if (rc) {
694 printk(KERN_WARNING "unmap irq failed %d\n", rc);
695 goto out;
696 }
697 }
1aa0b51a
KRW
698 pirq_to_irq[info->u.pirq.pirq] = -1;
699
b5401a96
AN
700 irq_info[irq] = mk_unbound_info();
701
c9df1ce5 702 xen_free_irq(irq);
b5401a96
AN
703
704out:
705 spin_unlock(&irq_mapping_update_lock);
706 return rc;
707}
708
af42b8d1
SS
709int xen_irq_from_pirq(unsigned pirq)
710{
711 return pirq_to_irq[pirq];
712}
713
b536b4b9 714int bind_evtchn_to_irq(unsigned int evtchn)
e46cdb66
JF
715{
716 int irq;
717
718 spin_lock(&irq_mapping_update_lock);
719
720 irq = evtchn_to_irq[evtchn];
721
722 if (irq == -1) {
c9df1ce5 723 irq = xen_allocate_irq_dynamic();
e46cdb66 724
e46cdb66 725 set_irq_chip_and_handler_name(irq, &xen_dynamic_chip,
3588fe2e 726 handle_fasteoi_irq, "event");
e46cdb66
JF
727
728 evtchn_to_irq[evtchn] = irq;
ced40d0f 729 irq_info[irq] = mk_evtchn_info(evtchn);
e46cdb66
JF
730 }
731
e46cdb66
JF
732 spin_unlock(&irq_mapping_update_lock);
733
734 return irq;
735}
b536b4b9 736EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
e46cdb66 737
f87e4cac
JF
738static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
739{
740 struct evtchn_bind_ipi bind_ipi;
741 int evtchn, irq;
742
743 spin_lock(&irq_mapping_update_lock);
744
745 irq = per_cpu(ipi_to_irq, cpu)[ipi];
90af9514 746
f87e4cac 747 if (irq == -1) {
c9df1ce5 748 irq = xen_allocate_irq_dynamic();
f87e4cac
JF
749 if (irq < 0)
750 goto out;
751
aaca4964
JF
752 set_irq_chip_and_handler_name(irq, &xen_percpu_chip,
753 handle_percpu_irq, "ipi");
f87e4cac
JF
754
755 bind_ipi.vcpu = cpu;
756 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
757 &bind_ipi) != 0)
758 BUG();
759 evtchn = bind_ipi.port;
760
761 evtchn_to_irq[evtchn] = irq;
ced40d0f 762 irq_info[irq] = mk_ipi_info(evtchn, ipi);
f87e4cac
JF
763 per_cpu(ipi_to_irq, cpu)[ipi] = irq;
764
765 bind_evtchn_to_cpu(evtchn, cpu);
766 }
767
f87e4cac
JF
768 out:
769 spin_unlock(&irq_mapping_update_lock);
770 return irq;
771}
772
773
4fe7d5a7 774int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
e46cdb66
JF
775{
776 struct evtchn_bind_virq bind_virq;
777 int evtchn, irq;
778
779 spin_lock(&irq_mapping_update_lock);
780
781 irq = per_cpu(virq_to_irq, cpu)[virq];
782
783 if (irq == -1) {
c9df1ce5 784 irq = xen_allocate_irq_dynamic();
a52521f1
JF
785
786 set_irq_chip_and_handler_name(irq, &xen_percpu_chip,
787 handle_percpu_irq, "virq");
788
e46cdb66
JF
789 bind_virq.virq = virq;
790 bind_virq.vcpu = cpu;
791 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
792 &bind_virq) != 0)
793 BUG();
794 evtchn = bind_virq.port;
795
e46cdb66 796 evtchn_to_irq[evtchn] = irq;
ced40d0f 797 irq_info[irq] = mk_virq_info(evtchn, virq);
e46cdb66
JF
798
799 per_cpu(virq_to_irq, cpu)[virq] = irq;
800
801 bind_evtchn_to_cpu(evtchn, cpu);
802 }
803
e46cdb66
JF
804 spin_unlock(&irq_mapping_update_lock);
805
806 return irq;
807}
808
809static void unbind_from_irq(unsigned int irq)
810{
811 struct evtchn_close close;
812 int evtchn = evtchn_from_irq(irq);
813
814 spin_lock(&irq_mapping_update_lock);
815
d77bbd4d 816 if (VALID_EVTCHN(evtchn)) {
e46cdb66
JF
817 close.port = evtchn;
818 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
819 BUG();
820
821 switch (type_from_irq(irq)) {
822 case IRQT_VIRQ:
823 per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 824 [virq_from_irq(irq)] = -1;
e46cdb66 825 break;
d68d82af
AN
826 case IRQT_IPI:
827 per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 828 [ipi_from_irq(irq)] = -1;
d68d82af 829 break;
e46cdb66
JF
830 default:
831 break;
832 }
833
834 /* Closed ports are implicitly re-bound to VCPU0. */
835 bind_evtchn_to_cpu(evtchn, 0);
836
837 evtchn_to_irq[evtchn] = -1;
fed5ea87
IC
838 }
839
840 if (irq_info[irq].type != IRQT_UNBOUND) {
ced40d0f 841 irq_info[irq] = mk_unbound_info();
e46cdb66 842
c9df1ce5 843 xen_free_irq(irq);
e46cdb66
JF
844 }
845
846 spin_unlock(&irq_mapping_update_lock);
847}
848
849int bind_evtchn_to_irqhandler(unsigned int evtchn,
7c239975 850 irq_handler_t handler,
e46cdb66
JF
851 unsigned long irqflags,
852 const char *devname, void *dev_id)
853{
854 unsigned int irq;
855 int retval;
856
857 irq = bind_evtchn_to_irq(evtchn);
858 retval = request_irq(irq, handler, irqflags, devname, dev_id);
859 if (retval != 0) {
860 unbind_from_irq(irq);
861 return retval;
862 }
863
864 return irq;
865}
866EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
867
868int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
7c239975 869 irq_handler_t handler,
e46cdb66
JF
870 unsigned long irqflags, const char *devname, void *dev_id)
871{
872 unsigned int irq;
873 int retval;
874
875 irq = bind_virq_to_irq(virq, cpu);
876 retval = request_irq(irq, handler, irqflags, devname, dev_id);
877 if (retval != 0) {
878 unbind_from_irq(irq);
879 return retval;
880 }
881
882 return irq;
883}
884EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
885
f87e4cac
JF
886int bind_ipi_to_irqhandler(enum ipi_vector ipi,
887 unsigned int cpu,
888 irq_handler_t handler,
889 unsigned long irqflags,
890 const char *devname,
891 void *dev_id)
892{
893 int irq, retval;
894
895 irq = bind_ipi_to_irq(ipi, cpu);
896 if (irq < 0)
897 return irq;
898
676dc3cf 899 irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME;
f87e4cac
JF
900 retval = request_irq(irq, handler, irqflags, devname, dev_id);
901 if (retval != 0) {
902 unbind_from_irq(irq);
903 return retval;
904 }
905
906 return irq;
907}
908
e46cdb66
JF
909void unbind_from_irqhandler(unsigned int irq, void *dev_id)
910{
911 free_irq(irq, dev_id);
912 unbind_from_irq(irq);
913}
914EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
915
f87e4cac
JF
916void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
917{
918 int irq = per_cpu(ipi_to_irq, cpu)[vector];
919 BUG_ON(irq < 0);
920 notify_remote_via_irq(irq);
921}
922
ee523ca1
JF
923irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
924{
925 struct shared_info *sh = HYPERVISOR_shared_info;
926 int cpu = smp_processor_id();
cb52e6d9 927 unsigned long *cpu_evtchn = cpu_evtchn_mask(cpu);
ee523ca1
JF
928 int i;
929 unsigned long flags;
930 static DEFINE_SPINLOCK(debug_lock);
cb52e6d9 931 struct vcpu_info *v;
ee523ca1
JF
932
933 spin_lock_irqsave(&debug_lock, flags);
934
cb52e6d9 935 printk("\nvcpu %d\n ", cpu);
ee523ca1
JF
936
937 for_each_online_cpu(i) {
cb52e6d9
IC
938 int pending;
939 v = per_cpu(xen_vcpu, i);
940 pending = (get_irq_regs() && i == cpu)
941 ? xen_irqs_disabled(get_irq_regs())
942 : v->evtchn_upcall_mask;
943 printk("%d: masked=%d pending=%d event_sel %0*lx\n ", i,
944 pending, v->evtchn_upcall_pending,
945 (int)(sizeof(v->evtchn_pending_sel)*2),
946 v->evtchn_pending_sel);
947 }
948 v = per_cpu(xen_vcpu, cpu);
949
950 printk("\npending:\n ");
951 for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
952 printk("%0*lx%s", (int)sizeof(sh->evtchn_pending[0])*2,
953 sh->evtchn_pending[i],
954 i % 8 == 0 ? "\n " : " ");
955 printk("\nglobal mask:\n ");
956 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
957 printk("%0*lx%s",
958 (int)(sizeof(sh->evtchn_mask[0])*2),
959 sh->evtchn_mask[i],
960 i % 8 == 0 ? "\n " : " ");
961
962 printk("\nglobally unmasked:\n ");
963 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
964 printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
965 sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
966 i % 8 == 0 ? "\n " : " ");
967
968 printk("\nlocal cpu%d mask:\n ", cpu);
969 for (i = (NR_EVENT_CHANNELS/BITS_PER_LONG)-1; i >= 0; i--)
970 printk("%0*lx%s", (int)(sizeof(cpu_evtchn[0])*2),
971 cpu_evtchn[i],
972 i % 8 == 0 ? "\n " : " ");
973
974 printk("\nlocally unmasked:\n ");
975 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
976 unsigned long pending = sh->evtchn_pending[i]
977 & ~sh->evtchn_mask[i]
978 & cpu_evtchn[i];
979 printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
980 pending, i % 8 == 0 ? "\n " : " ");
ee523ca1 981 }
ee523ca1
JF
982
983 printk("\npending list:\n");
cb52e6d9 984 for (i = 0; i < NR_EVENT_CHANNELS; i++) {
ee523ca1 985 if (sync_test_bit(i, sh->evtchn_pending)) {
cb52e6d9
IC
986 int word_idx = i / BITS_PER_LONG;
987 printk(" %d: event %d -> irq %d%s%s%s\n",
ced40d0f 988 cpu_from_evtchn(i), i,
cb52e6d9
IC
989 evtchn_to_irq[i],
990 sync_test_bit(word_idx, &v->evtchn_pending_sel)
991 ? "" : " l2-clear",
992 !sync_test_bit(i, sh->evtchn_mask)
993 ? "" : " globally-masked",
994 sync_test_bit(i, cpu_evtchn)
995 ? "" : " locally-masked");
ee523ca1
JF
996 }
997 }
998
999 spin_unlock_irqrestore(&debug_lock, flags);
1000
1001 return IRQ_HANDLED;
1002}
1003
245b2e70
TH
1004static DEFINE_PER_CPU(unsigned, xed_nesting_count);
1005
e46cdb66
JF
1006/*
1007 * Search the CPUs pending events bitmasks. For each one found, map
1008 * the event number to an irq, and feed it into do_IRQ() for
1009 * handling.
1010 *
1011 * Xen uses a two-level bitmap to speed searching. The first level is
1012 * a bitset of words which contain pending event bits. The second
1013 * level is a bitset of pending events themselves.
1014 */
38e20b07 1015static void __xen_evtchn_do_upcall(void)
e46cdb66
JF
1016{
1017 int cpu = get_cpu();
1018 struct shared_info *s = HYPERVISOR_shared_info;
780f36d8 1019 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
229664be 1020 unsigned count;
e46cdb66 1021
229664be
JF
1022 do {
1023 unsigned long pending_words;
e46cdb66 1024
229664be 1025 vcpu_info->evtchn_upcall_pending = 0;
e46cdb66 1026
b2e4ae69 1027 if (__this_cpu_inc_return(xed_nesting_count) - 1)
229664be 1028 goto out;
e46cdb66 1029
e849c3e9
IY
1030#ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */
1031 /* Clear master flag /before/ clearing selector flag. */
6673cf63 1032 wmb();
e849c3e9 1033#endif
229664be
JF
1034 pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0);
1035 while (pending_words != 0) {
1036 unsigned long pending_bits;
1037 int word_idx = __ffs(pending_words);
1038 pending_words &= ~(1UL << word_idx);
1039
1040 while ((pending_bits = active_evtchns(cpu, s, word_idx)) != 0) {
1041 int bit_idx = __ffs(pending_bits);
1042 int port = (word_idx * BITS_PER_LONG) + bit_idx;
1043 int irq = evtchn_to_irq[port];
ca4dbc66 1044 struct irq_desc *desc;
229664be 1045
3588fe2e
JF
1046 mask_evtchn(port);
1047 clear_evtchn(port);
1048
ca4dbc66
EB
1049 if (irq != -1) {
1050 desc = irq_to_desc(irq);
1051 if (desc)
1052 generic_handle_irq_desc(irq, desc);
1053 }
e46cdb66
JF
1054 }
1055 }
e46cdb66 1056
229664be
JF
1057 BUG_ON(!irqs_disabled());
1058
780f36d8
CL
1059 count = __this_cpu_read(xed_nesting_count);
1060 __this_cpu_write(xed_nesting_count, 0);
183d03cc 1061 } while (count != 1 || vcpu_info->evtchn_upcall_pending);
229664be
JF
1062
1063out:
38e20b07
SY
1064
1065 put_cpu();
1066}
1067
1068void xen_evtchn_do_upcall(struct pt_regs *regs)
1069{
1070 struct pt_regs *old_regs = set_irq_regs(regs);
1071
1072 exit_idle();
1073 irq_enter();
1074
1075 __xen_evtchn_do_upcall();
1076
3445a8fd
JF
1077 irq_exit();
1078 set_irq_regs(old_regs);
38e20b07 1079}
3445a8fd 1080
38e20b07
SY
1081void xen_hvm_evtchn_do_upcall(void)
1082{
1083 __xen_evtchn_do_upcall();
e46cdb66 1084}
183d03cc 1085EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
e46cdb66 1086
eb1e305f
JF
1087/* Rebind a new event channel to an existing irq. */
1088void rebind_evtchn_irq(int evtchn, int irq)
1089{
d77bbd4d
JF
1090 struct irq_info *info = info_for_irq(irq);
1091
eb1e305f
JF
1092 /* Make sure the irq is masked, since the new event channel
1093 will also be masked. */
1094 disable_irq(irq);
1095
1096 spin_lock(&irq_mapping_update_lock);
1097
1098 /* After resume the irq<->evtchn mappings are all cleared out */
1099 BUG_ON(evtchn_to_irq[evtchn] != -1);
1100 /* Expect irq to have been bound before,
d77bbd4d
JF
1101 so there should be a proper type */
1102 BUG_ON(info->type == IRQT_UNBOUND);
eb1e305f
JF
1103
1104 evtchn_to_irq[evtchn] = irq;
ced40d0f 1105 irq_info[irq] = mk_evtchn_info(evtchn);
eb1e305f
JF
1106
1107 spin_unlock(&irq_mapping_update_lock);
1108
1109 /* new event channels are always bound to cpu 0 */
0de26520 1110 irq_set_affinity(irq, cpumask_of(0));
eb1e305f
JF
1111
1112 /* Unmask the event channel. */
1113 enable_irq(irq);
1114}
1115
e46cdb66 1116/* Rebind an evtchn so that it gets delivered to a specific cpu */
d5dedd45 1117static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
e46cdb66
JF
1118{
1119 struct evtchn_bind_vcpu bind_vcpu;
1120 int evtchn = evtchn_from_irq(irq);
1121
be49472f
IC
1122 if (!VALID_EVTCHN(evtchn))
1123 return -1;
1124
1125 /*
1126 * Events delivered via platform PCI interrupts are always
1127 * routed to vcpu 0 and hence cannot be rebound.
1128 */
1129 if (xen_hvm_domain() && !xen_have_vector_callback)
d5dedd45 1130 return -1;
e46cdb66
JF
1131
1132 /* Send future instances of this interrupt to other vcpu. */
1133 bind_vcpu.port = evtchn;
1134 bind_vcpu.vcpu = tcpu;
1135
1136 /*
1137 * If this fails, it usually just indicates that we're dealing with a
1138 * virq or IPI channel, which don't actually need to be rebound. Ignore
1139 * it, but don't do the xenlinux-level rebind in that case.
1140 */
1141 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
1142 bind_evtchn_to_cpu(evtchn, tcpu);
e46cdb66 1143
d5dedd45
YL
1144 return 0;
1145}
e46cdb66 1146
c9e265e0
TG
1147static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest,
1148 bool force)
e46cdb66 1149{
0de26520 1150 unsigned tcpu = cpumask_first(dest);
d5dedd45 1151
c9e265e0 1152 return rebind_irq_to_cpu(data->irq, tcpu);
e46cdb66
JF
1153}
1154
642e0c88
IY
1155int resend_irq_on_evtchn(unsigned int irq)
1156{
1157 int masked, evtchn = evtchn_from_irq(irq);
1158 struct shared_info *s = HYPERVISOR_shared_info;
1159
1160 if (!VALID_EVTCHN(evtchn))
1161 return 1;
1162
1163 masked = sync_test_and_set_bit(evtchn, s->evtchn_mask);
1164 sync_set_bit(evtchn, s->evtchn_pending);
1165 if (!masked)
1166 unmask_evtchn(evtchn);
1167
1168 return 1;
1169}
1170
c9e265e0 1171static void enable_dynirq(struct irq_data *data)
e46cdb66 1172{
c9e265e0 1173 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1174
1175 if (VALID_EVTCHN(evtchn))
1176 unmask_evtchn(evtchn);
1177}
1178
c9e265e0 1179static void disable_dynirq(struct irq_data *data)
e46cdb66 1180{
c9e265e0 1181 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1182
1183 if (VALID_EVTCHN(evtchn))
1184 mask_evtchn(evtchn);
1185}
1186
c9e265e0 1187static void ack_dynirq(struct irq_data *data)
e46cdb66 1188{
c9e265e0 1189 int evtchn = evtchn_from_irq(data->irq);
e46cdb66 1190
c9e265e0 1191 move_masked_irq(data->irq);
e46cdb66
JF
1192
1193 if (VALID_EVTCHN(evtchn))
3588fe2e 1194 unmask_evtchn(evtchn);
e46cdb66
JF
1195}
1196
c9e265e0 1197static int retrigger_dynirq(struct irq_data *data)
e46cdb66 1198{
c9e265e0 1199 int evtchn = evtchn_from_irq(data->irq);
ee8fa1c6 1200 struct shared_info *sh = HYPERVISOR_shared_info;
e46cdb66
JF
1201 int ret = 0;
1202
1203 if (VALID_EVTCHN(evtchn)) {
ee8fa1c6
JF
1204 int masked;
1205
1206 masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask);
1207 sync_set_bit(evtchn, sh->evtchn_pending);
1208 if (!masked)
1209 unmask_evtchn(evtchn);
e46cdb66
JF
1210 ret = 1;
1211 }
1212
1213 return ret;
1214}
1215
0a85226f 1216static void restore_pirqs(void)
9a069c33
SS
1217{
1218 int pirq, rc, irq, gsi;
1219 struct physdev_map_pirq map_irq;
1220
1221 for (pirq = 0; pirq < nr_irqs; pirq++) {
1222 irq = pirq_to_irq[pirq];
1223 if (irq == -1)
1224 continue;
1225
1226 /* save/restore of PT devices doesn't work, so at this point the
1227 * only devices present are GSI based emulated devices */
1228 gsi = gsi_from_irq(irq);
1229 if (!gsi)
1230 continue;
1231
1232 map_irq.domid = DOMID_SELF;
1233 map_irq.type = MAP_PIRQ_TYPE_GSI;
1234 map_irq.index = gsi;
1235 map_irq.pirq = pirq;
1236
1237 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
1238 if (rc) {
1239 printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
1240 gsi, irq, pirq, rc);
1241 irq_info[irq] = mk_unbound_info();
1242 pirq_to_irq[pirq] = -1;
1243 continue;
1244 }
1245
1246 printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
1247
c9e265e0 1248 __startup_pirq(irq);
9a069c33
SS
1249 }
1250}
1251
0e91398f
JF
1252static void restore_cpu_virqs(unsigned int cpu)
1253{
1254 struct evtchn_bind_virq bind_virq;
1255 int virq, irq, evtchn;
1256
1257 for (virq = 0; virq < NR_VIRQS; virq++) {
1258 if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
1259 continue;
1260
ced40d0f 1261 BUG_ON(virq_from_irq(irq) != virq);
0e91398f
JF
1262
1263 /* Get a new binding from Xen. */
1264 bind_virq.virq = virq;
1265 bind_virq.vcpu = cpu;
1266 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
1267 &bind_virq) != 0)
1268 BUG();
1269 evtchn = bind_virq.port;
1270
1271 /* Record the new mapping. */
1272 evtchn_to_irq[evtchn] = irq;
ced40d0f 1273 irq_info[irq] = mk_virq_info(evtchn, virq);
0e91398f 1274 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1275 }
1276}
1277
1278static void restore_cpu_ipis(unsigned int cpu)
1279{
1280 struct evtchn_bind_ipi bind_ipi;
1281 int ipi, irq, evtchn;
1282
1283 for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
1284 if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
1285 continue;
1286
ced40d0f 1287 BUG_ON(ipi_from_irq(irq) != ipi);
0e91398f
JF
1288
1289 /* Get a new binding from Xen. */
1290 bind_ipi.vcpu = cpu;
1291 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
1292 &bind_ipi) != 0)
1293 BUG();
1294 evtchn = bind_ipi.port;
1295
1296 /* Record the new mapping. */
1297 evtchn_to_irq[evtchn] = irq;
ced40d0f 1298 irq_info[irq] = mk_ipi_info(evtchn, ipi);
0e91398f 1299 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1300 }
1301}
1302
2d9e1e2f
JF
1303/* Clear an irq's pending state, in preparation for polling on it */
1304void xen_clear_irq_pending(int irq)
1305{
1306 int evtchn = evtchn_from_irq(irq);
1307
1308 if (VALID_EVTCHN(evtchn))
1309 clear_evtchn(evtchn);
1310}
d9a8814f 1311EXPORT_SYMBOL(xen_clear_irq_pending);
168d2f46
JF
1312void xen_set_irq_pending(int irq)
1313{
1314 int evtchn = evtchn_from_irq(irq);
1315
1316 if (VALID_EVTCHN(evtchn))
1317 set_evtchn(evtchn);
1318}
1319
1320bool xen_test_irq_pending(int irq)
1321{
1322 int evtchn = evtchn_from_irq(irq);
1323 bool ret = false;
1324
1325 if (VALID_EVTCHN(evtchn))
1326 ret = test_evtchn(evtchn);
1327
1328 return ret;
1329}
1330
d9a8814f
KRW
1331/* Poll waiting for an irq to become pending with timeout. In the usual case,
1332 * the irq will be disabled so it won't deliver an interrupt. */
1333void xen_poll_irq_timeout(int irq, u64 timeout)
2d9e1e2f
JF
1334{
1335 evtchn_port_t evtchn = evtchn_from_irq(irq);
1336
1337 if (VALID_EVTCHN(evtchn)) {
1338 struct sched_poll poll;
1339
1340 poll.nr_ports = 1;
d9a8814f 1341 poll.timeout = timeout;
ff3c5362 1342 set_xen_guest_handle(poll.ports, &evtchn);
2d9e1e2f
JF
1343
1344 if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
1345 BUG();
1346 }
1347}
d9a8814f
KRW
1348EXPORT_SYMBOL(xen_poll_irq_timeout);
1349/* Poll waiting for an irq to become pending. In the usual case, the
1350 * irq will be disabled so it won't deliver an interrupt. */
1351void xen_poll_irq(int irq)
1352{
1353 xen_poll_irq_timeout(irq, 0 /* no timeout */);
1354}
2d9e1e2f 1355
0e91398f
JF
1356void xen_irq_resume(void)
1357{
1358 unsigned int cpu, irq, evtchn;
1359
1360 init_evtchn_cpu_bindings();
1361
1362 /* New event-channel space is not 'live' yet. */
1363 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1364 mask_evtchn(evtchn);
1365
1366 /* No IRQ <-> event-channel mappings. */
0b8f1efa 1367 for (irq = 0; irq < nr_irqs; irq++)
0e91398f
JF
1368 irq_info[irq].evtchn = 0; /* zap event-channel binding */
1369
1370 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1371 evtchn_to_irq[evtchn] = -1;
1372
1373 for_each_possible_cpu(cpu) {
1374 restore_cpu_virqs(cpu);
1375 restore_cpu_ipis(cpu);
1376 }
6903591f 1377
0a85226f 1378 restore_pirqs();
0e91398f
JF
1379}
1380
e46cdb66 1381static struct irq_chip xen_dynamic_chip __read_mostly = {
c9e265e0 1382 .name = "xen-dyn",
54a353a0 1383
c9e265e0
TG
1384 .irq_disable = disable_dynirq,
1385 .irq_mask = disable_dynirq,
1386 .irq_unmask = enable_dynirq,
54a353a0 1387
c9e265e0
TG
1388 .irq_eoi = ack_dynirq,
1389 .irq_set_affinity = set_affinity_irq,
1390 .irq_retrigger = retrigger_dynirq,
e46cdb66
JF
1391};
1392
d46a78b0 1393static struct irq_chip xen_pirq_chip __read_mostly = {
c9e265e0 1394 .name = "xen-pirq",
d46a78b0 1395
c9e265e0
TG
1396 .irq_startup = startup_pirq,
1397 .irq_shutdown = shutdown_pirq,
d46a78b0 1398
c9e265e0
TG
1399 .irq_enable = enable_pirq,
1400 .irq_unmask = enable_pirq,
d46a78b0 1401
c9e265e0
TG
1402 .irq_disable = disable_pirq,
1403 .irq_mask = disable_pirq,
d46a78b0 1404
c9e265e0 1405 .irq_ack = ack_pirq,
d46a78b0 1406
c9e265e0 1407 .irq_set_affinity = set_affinity_irq,
d46a78b0 1408
c9e265e0 1409 .irq_retrigger = retrigger_dynirq,
d46a78b0
JF
1410};
1411
aaca4964 1412static struct irq_chip xen_percpu_chip __read_mostly = {
c9e265e0 1413 .name = "xen-percpu",
aaca4964 1414
c9e265e0
TG
1415 .irq_disable = disable_dynirq,
1416 .irq_mask = disable_dynirq,
1417 .irq_unmask = enable_dynirq,
aaca4964 1418
c9e265e0 1419 .irq_ack = ack_dynirq,
aaca4964
JF
1420};
1421
38e20b07
SY
1422int xen_set_callback_via(uint64_t via)
1423{
1424 struct xen_hvm_param a;
1425 a.domid = DOMID_SELF;
1426 a.index = HVM_PARAM_CALLBACK_IRQ;
1427 a.value = via;
1428 return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
1429}
1430EXPORT_SYMBOL_GPL(xen_set_callback_via);
1431
ca65f9fc 1432#ifdef CONFIG_XEN_PVHVM
38e20b07
SY
1433/* Vector callbacks are better than PCI interrupts to receive event
1434 * channel notifications because we can receive vector callbacks on any
1435 * vcpu and we don't need PCI support or APIC interactions. */
1436void xen_callback_vector(void)
1437{
1438 int rc;
1439 uint64_t callback_via;
1440 if (xen_have_vector_callback) {
1441 callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK);
1442 rc = xen_set_callback_via(callback_via);
1443 if (rc) {
1444 printk(KERN_ERR "Request for Xen HVM callback vector"
1445 " failed.\n");
1446 xen_have_vector_callback = 0;
1447 return;
1448 }
1449 printk(KERN_INFO "Xen HVM callback vector for event delivery is "
1450 "enabled\n");
1451 /* in the restore case the vector has already been allocated */
1452 if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors))
1453 alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector);
1454 }
1455}
ca65f9fc
SS
1456#else
1457void xen_callback_vector(void) {}
1458#endif
38e20b07 1459
e46cdb66
JF
1460void __init xen_init_IRQ(void)
1461{
e5fc7345 1462 int i;
c7a3589e 1463
a70c352a
PE
1464 cpu_evtchn_mask_p = kcalloc(nr_cpu_ids, sizeof(struct cpu_evtchn_s),
1465 GFP_KERNEL);
b21ddbf5
JF
1466 irq_info = kcalloc(nr_irqs, sizeof(*irq_info), GFP_KERNEL);
1467
e5fc7345
SS
1468 /* We are using nr_irqs as the maximum number of pirq available but
1469 * that number is actually chosen by Xen and we don't know exactly
1470 * what it is. Be careful choosing high pirq numbers. */
1471 pirq_to_irq = kcalloc(nr_irqs, sizeof(*pirq_to_irq), GFP_KERNEL);
1472 for (i = 0; i < nr_irqs; i++)
7a043f11
SS
1473 pirq_to_irq[i] = -1;
1474
b21ddbf5
JF
1475 evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
1476 GFP_KERNEL);
1477 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1478 evtchn_to_irq[i] = -1;
e46cdb66
JF
1479
1480 init_evtchn_cpu_bindings();
1481
1482 /* No event channels are 'live' right now. */
1483 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1484 mask_evtchn(i);
1485
38e20b07
SY
1486 if (xen_hvm_domain()) {
1487 xen_callback_vector();
1488 native_init_IRQ();
3942b740
SS
1489 /* pci_xen_hvm_init must be called after native_init_IRQ so that
1490 * __acpi_register_gsi can point at the right function */
1491 pci_xen_hvm_init();
38e20b07
SY
1492 } else {
1493 irq_ctx_init(smp_processor_id());
38aa66fc
JF
1494 if (xen_initial_domain())
1495 xen_setup_pirqs();
38e20b07 1496 }
e46cdb66 1497}
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