Merge branch 'x86-debug-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / drivers / xen / events.c
CommitLineData
e46cdb66
JF
1/*
2 * Xen event channels
3 *
4 * Xen models interrupts with abstract event channels. Because each
5 * domain gets 1024 event channels, but NR_IRQ is not that large, we
6 * must dynamically map irqs<->event channels. The event channels
7 * interface with the rest of the kernel by defining a xen interrupt
8 * chip. When an event is recieved, it is mapped to an irq and sent
9 * through the normal interrupt processing path.
10 *
11 * There are four kinds of events which can be mapped to an event
12 * channel:
13 *
14 * 1. Inter-domain notifications. This includes all the virtual
15 * device events, since they're driven by front-ends in another domain
16 * (typically dom0).
17 * 2. VIRQs, typically used for timers. These are per-cpu events.
18 * 3. IPIs.
d46a78b0 19 * 4. PIRQs - Hardware interrupts.
e46cdb66
JF
20 *
21 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
22 */
23
24#include <linux/linkage.h>
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/module.h>
28#include <linux/string.h>
28e08861 29#include <linux/bootmem.h>
5a0e3ad6 30#include <linux/slab.h>
b21ddbf5 31#include <linux/irqnr.h>
f731e3ef 32#include <linux/pci.h>
e46cdb66 33
38e20b07 34#include <asm/desc.h>
e46cdb66
JF
35#include <asm/ptrace.h>
36#include <asm/irq.h>
792dc4f6 37#include <asm/idle.h>
0794bfc7 38#include <asm/io_apic.h>
e46cdb66 39#include <asm/sync_bitops.h>
42a1de56 40#include <asm/xen/pci.h>
e46cdb66 41#include <asm/xen/hypercall.h>
8d1b8753 42#include <asm/xen/hypervisor.h>
e46cdb66 43
38e20b07
SY
44#include <xen/xen.h>
45#include <xen/hvm.h>
e04d0d07 46#include <xen/xen-ops.h>
e46cdb66
JF
47#include <xen/events.h>
48#include <xen/interface/xen.h>
49#include <xen/interface/event_channel.h>
38e20b07
SY
50#include <xen/interface/hvm/hvm_op.h>
51#include <xen/interface/hvm/params.h>
e46cdb66 52
e46cdb66
JF
53/*
54 * This lock protects updates to the following mapping and reference-count
55 * arrays. The lock does not need to be acquired to read the mapping tables.
56 */
57static DEFINE_SPINLOCK(irq_mapping_update_lock);
58
59/* IRQ <-> VIRQ mapping. */
204fba4a 60static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
e46cdb66 61
f87e4cac 62/* IRQ <-> IPI mapping */
204fba4a 63static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
f87e4cac 64
ced40d0f
JF
65/* Interrupt types. */
66enum xen_irq_type {
d77bbd4d 67 IRQT_UNBOUND = 0,
f87e4cac
JF
68 IRQT_PIRQ,
69 IRQT_VIRQ,
70 IRQT_IPI,
71 IRQT_EVTCHN
72};
e46cdb66 73
ced40d0f
JF
74/*
75 * Packed IRQ information:
76 * type - enum xen_irq_type
77 * event channel - irq->event channel mapping
78 * cpu - cpu this event channel is bound to
79 * index - type-specific information:
42a1de56
SS
80 * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM
81 * guest, or GSI (real passthrough IRQ) of the device.
ced40d0f
JF
82 * VIRQ - virq number
83 * IPI - IPI vector
84 * EVTCHN -
85 */
86struct irq_info
87{
88 enum xen_irq_type type; /* type */
89 unsigned short evtchn; /* event channel */
90 unsigned short cpu; /* cpu bound */
91
92 union {
93 unsigned short virq;
94 enum ipi_vector ipi;
95 struct {
7a043f11 96 unsigned short pirq;
ced40d0f 97 unsigned short gsi;
d46a78b0
JF
98 unsigned char vector;
99 unsigned char flags;
ced40d0f
JF
100 } pirq;
101 } u;
102};
d46a78b0 103#define PIRQ_NEEDS_EOI (1 << 0)
15ebbb82 104#define PIRQ_SHAREABLE (1 << 1)
ced40d0f 105
b21ddbf5 106static struct irq_info *irq_info;
7a043f11 107static int *pirq_to_irq;
e46cdb66 108
b21ddbf5 109static int *evtchn_to_irq;
c7a3589e
MT
110struct cpu_evtchn_s {
111 unsigned long bits[NR_EVENT_CHANNELS/BITS_PER_LONG];
112};
3b32f574
JF
113
114static __initdata struct cpu_evtchn_s init_evtchn_mask = {
115 .bits[0 ... (NR_EVENT_CHANNELS/BITS_PER_LONG)-1] = ~0ul,
116};
b052181a 117static struct cpu_evtchn_s __refdata *cpu_evtchn_mask_p = &init_evtchn_mask;
3b32f574 118
c7a3589e
MT
119static inline unsigned long *cpu_evtchn_mask(int cpu)
120{
121 return cpu_evtchn_mask_p[cpu].bits;
122}
e46cdb66 123
e46cdb66
JF
124/* Xen will never allocate port zero for any purpose. */
125#define VALID_EVTCHN(chn) ((chn) != 0)
126
e46cdb66 127static struct irq_chip xen_dynamic_chip;
aaca4964 128static struct irq_chip xen_percpu_chip;
d46a78b0 129static struct irq_chip xen_pirq_chip;
e46cdb66
JF
130
131/* Constructor for packed IRQ information. */
ced40d0f
JF
132static struct irq_info mk_unbound_info(void)
133{
134 return (struct irq_info) { .type = IRQT_UNBOUND };
135}
136
137static struct irq_info mk_evtchn_info(unsigned short evtchn)
138{
90af9514
IC
139 return (struct irq_info) { .type = IRQT_EVTCHN, .evtchn = evtchn,
140 .cpu = 0 };
ced40d0f
JF
141}
142
143static struct irq_info mk_ipi_info(unsigned short evtchn, enum ipi_vector ipi)
e46cdb66 144{
ced40d0f 145 return (struct irq_info) { .type = IRQT_IPI, .evtchn = evtchn,
90af9514 146 .cpu = 0, .u.ipi = ipi };
ced40d0f
JF
147}
148
149static struct irq_info mk_virq_info(unsigned short evtchn, unsigned short virq)
150{
151 return (struct irq_info) { .type = IRQT_VIRQ, .evtchn = evtchn,
90af9514 152 .cpu = 0, .u.virq = virq };
ced40d0f
JF
153}
154
7a043f11 155static struct irq_info mk_pirq_info(unsigned short evtchn, unsigned short pirq,
ced40d0f
JF
156 unsigned short gsi, unsigned short vector)
157{
158 return (struct irq_info) { .type = IRQT_PIRQ, .evtchn = evtchn,
7a043f11
SS
159 .cpu = 0,
160 .u.pirq = { .pirq = pirq, .gsi = gsi, .vector = vector } };
e46cdb66
JF
161}
162
163/*
164 * Accessors for packed IRQ information.
165 */
ced40d0f 166static struct irq_info *info_for_irq(unsigned irq)
e46cdb66 167{
ced40d0f 168 return &irq_info[irq];
e46cdb66
JF
169}
170
ced40d0f 171static unsigned int evtchn_from_irq(unsigned irq)
e46cdb66 172{
110e7c7e
JJ
173 if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
174 return 0;
175
ced40d0f 176 return info_for_irq(irq)->evtchn;
e46cdb66
JF
177}
178
d4c04536
IC
179unsigned irq_from_evtchn(unsigned int evtchn)
180{
181 return evtchn_to_irq[evtchn];
182}
183EXPORT_SYMBOL_GPL(irq_from_evtchn);
184
ced40d0f 185static enum ipi_vector ipi_from_irq(unsigned irq)
e46cdb66 186{
ced40d0f
JF
187 struct irq_info *info = info_for_irq(irq);
188
189 BUG_ON(info == NULL);
190 BUG_ON(info->type != IRQT_IPI);
191
192 return info->u.ipi;
193}
194
195static unsigned virq_from_irq(unsigned irq)
196{
197 struct irq_info *info = info_for_irq(irq);
198
199 BUG_ON(info == NULL);
200 BUG_ON(info->type != IRQT_VIRQ);
201
202 return info->u.virq;
203}
204
7a043f11
SS
205static unsigned pirq_from_irq(unsigned irq)
206{
207 struct irq_info *info = info_for_irq(irq);
208
209 BUG_ON(info == NULL);
210 BUG_ON(info->type != IRQT_PIRQ);
211
212 return info->u.pirq.pirq;
213}
214
ced40d0f
JF
215static unsigned gsi_from_irq(unsigned irq)
216{
217 struct irq_info *info = info_for_irq(irq);
218
219 BUG_ON(info == NULL);
220 BUG_ON(info->type != IRQT_PIRQ);
221
222 return info->u.pirq.gsi;
223}
224
225static unsigned vector_from_irq(unsigned irq)
226{
227 struct irq_info *info = info_for_irq(irq);
228
229 BUG_ON(info == NULL);
230 BUG_ON(info->type != IRQT_PIRQ);
231
232 return info->u.pirq.vector;
233}
234
235static enum xen_irq_type type_from_irq(unsigned irq)
236{
237 return info_for_irq(irq)->type;
238}
239
240static unsigned cpu_from_irq(unsigned irq)
241{
242 return info_for_irq(irq)->cpu;
243}
244
245static unsigned int cpu_from_evtchn(unsigned int evtchn)
246{
247 int irq = evtchn_to_irq[evtchn];
248 unsigned ret = 0;
249
250 if (irq != -1)
251 ret = cpu_from_irq(irq);
252
253 return ret;
e46cdb66
JF
254}
255
d46a78b0
JF
256static bool pirq_needs_eoi(unsigned irq)
257{
258 struct irq_info *info = info_for_irq(irq);
259
260 BUG_ON(info->type != IRQT_PIRQ);
261
262 return info->u.pirq.flags & PIRQ_NEEDS_EOI;
263}
264
e46cdb66
JF
265static inline unsigned long active_evtchns(unsigned int cpu,
266 struct shared_info *sh,
267 unsigned int idx)
268{
269 return (sh->evtchn_pending[idx] &
c7a3589e 270 cpu_evtchn_mask(cpu)[idx] &
e46cdb66
JF
271 ~sh->evtchn_mask[idx]);
272}
273
274static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
275{
276 int irq = evtchn_to_irq[chn];
277
278 BUG_ON(irq == -1);
279#ifdef CONFIG_SMP
c9e265e0 280 cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu));
e46cdb66
JF
281#endif
282
e0419564
JF
283 clear_bit(chn, cpu_evtchn_mask(cpu_from_irq(irq)));
284 set_bit(chn, cpu_evtchn_mask(cpu));
e46cdb66 285
ced40d0f 286 irq_info[irq].cpu = cpu;
e46cdb66
JF
287}
288
289static void init_evtchn_cpu_bindings(void)
290{
1c6969ec 291 int i;
e46cdb66 292#ifdef CONFIG_SMP
10e58084 293 struct irq_desc *desc;
10e58084 294
e46cdb66 295 /* By default all event channels notify CPU#0. */
0b8f1efa 296 for_each_irq_desc(i, desc) {
c9e265e0 297 cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
0b8f1efa 298 }
e46cdb66
JF
299#endif
300
1c6969ec
JB
301 for_each_possible_cpu(i)
302 memset(cpu_evtchn_mask(i),
303 (i == 0) ? ~0 : 0, sizeof(struct cpu_evtchn_s));
304
e46cdb66
JF
305}
306
e46cdb66
JF
307static inline void clear_evtchn(int port)
308{
309 struct shared_info *s = HYPERVISOR_shared_info;
310 sync_clear_bit(port, &s->evtchn_pending[0]);
311}
312
313static inline void set_evtchn(int port)
314{
315 struct shared_info *s = HYPERVISOR_shared_info;
316 sync_set_bit(port, &s->evtchn_pending[0]);
317}
318
168d2f46
JF
319static inline int test_evtchn(int port)
320{
321 struct shared_info *s = HYPERVISOR_shared_info;
322 return sync_test_bit(port, &s->evtchn_pending[0]);
323}
324
e46cdb66
JF
325
326/**
327 * notify_remote_via_irq - send event to remote end of event channel via irq
328 * @irq: irq of event channel to send event to
329 *
330 * Unlike notify_remote_via_evtchn(), this is safe to use across
331 * save/restore. Notifications on a broken connection are silently
332 * dropped.
333 */
334void notify_remote_via_irq(int irq)
335{
336 int evtchn = evtchn_from_irq(irq);
337
338 if (VALID_EVTCHN(evtchn))
339 notify_remote_via_evtchn(evtchn);
340}
341EXPORT_SYMBOL_GPL(notify_remote_via_irq);
342
343static void mask_evtchn(int port)
344{
345 struct shared_info *s = HYPERVISOR_shared_info;
346 sync_set_bit(port, &s->evtchn_mask[0]);
347}
348
349static void unmask_evtchn(int port)
350{
351 struct shared_info *s = HYPERVISOR_shared_info;
352 unsigned int cpu = get_cpu();
353
354 BUG_ON(!irqs_disabled());
355
356 /* Slow path (hypercall) if this is a non-local port. */
357 if (unlikely(cpu != cpu_from_evtchn(port))) {
358 struct evtchn_unmask unmask = { .port = port };
359 (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
360 } else {
780f36d8 361 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
e46cdb66
JF
362
363 sync_clear_bit(port, &s->evtchn_mask[0]);
364
365 /*
366 * The following is basically the equivalent of
367 * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
368 * the interrupt edge' if the channel is masked.
369 */
370 if (sync_test_bit(port, &s->evtchn_pending[0]) &&
371 !sync_test_and_set_bit(port / BITS_PER_LONG,
372 &vcpu_info->evtchn_pending_sel))
373 vcpu_info->evtchn_upcall_pending = 1;
374 }
375
376 put_cpu();
377}
378
89911501 379static int xen_allocate_irq_dynamic(void)
0794bfc7 380{
89911501
IC
381 int first = 0;
382 int irq;
0794bfc7
KRW
383
384#ifdef CONFIG_X86_IO_APIC
89911501
IC
385 /*
386 * For an HVM guest or domain 0 which see "real" (emulated or
387 * actual repectively) GSIs we allocate dynamic IRQs
388 * e.g. those corresponding to event channels or MSIs
389 * etc. from the range above those "real" GSIs to avoid
390 * collisions.
391 */
392 if (xen_initial_domain() || xen_hvm_domain())
393 first = get_nr_irqs_gsi();
0794bfc7
KRW
394#endif
395
89911501
IC
396retry:
397 irq = irq_alloc_desc_from(first, -1);
3a69e916 398
89911501
IC
399 if (irq == -ENOMEM && first > NR_IRQS_LEGACY) {
400 printk(KERN_ERR "Out of dynamic IRQ space and eating into GSI space. You should increase nr_irqs\n");
401 first = max(NR_IRQS_LEGACY, first - NR_IRQS_LEGACY);
402 goto retry;
99ad198c 403 }
e46cdb66 404
89911501
IC
405 if (irq < 0)
406 panic("No available IRQ to bind to: increase nr_irqs!\n");
ced40d0f 407
e46cdb66 408 return irq;
d46a78b0
JF
409}
410
c9df1ce5
IC
411static int xen_allocate_irq_gsi(unsigned gsi)
412{
413 int irq;
414
89911501
IC
415 /*
416 * A PV guest has no concept of a GSI (since it has no ACPI
417 * nor access to/knowledge of the physical APICs). Therefore
418 * all IRQs are dynamically allocated from the entire IRQ
419 * space.
420 */
421 if (xen_pv_domain() && !xen_initial_domain())
c9df1ce5
IC
422 return xen_allocate_irq_dynamic();
423
424 /* Legacy IRQ descriptors are already allocated by the arch. */
425 if (gsi < NR_IRQS_LEGACY)
426 return gsi;
427
428 irq = irq_alloc_desc_at(gsi, -1);
429 if (irq < 0)
430 panic("Unable to allocate to IRQ%d (%d)\n", gsi, irq);
431
432 return irq;
433}
434
435static void xen_free_irq(unsigned irq)
436{
72146104
IC
437 /* Legacy IRQ descriptors are managed by the arch. */
438 if (irq < NR_IRQS_LEGACY)
439 return;
440
c9df1ce5
IC
441 irq_free_desc(irq);
442}
443
d46a78b0
JF
444static void pirq_unmask_notify(int irq)
445{
7a043f11 446 struct physdev_eoi eoi = { .irq = pirq_from_irq(irq) };
d46a78b0
JF
447
448 if (unlikely(pirq_needs_eoi(irq))) {
449 int rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
450 WARN_ON(rc);
451 }
452}
453
454static void pirq_query_unmask(int irq)
455{
456 struct physdev_irq_status_query irq_status;
457 struct irq_info *info = info_for_irq(irq);
458
459 BUG_ON(info->type != IRQT_PIRQ);
460
7a043f11 461 irq_status.irq = pirq_from_irq(irq);
d46a78b0
JF
462 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
463 irq_status.flags = 0;
464
465 info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
466 if (irq_status.flags & XENIRQSTAT_needs_eoi)
467 info->u.pirq.flags |= PIRQ_NEEDS_EOI;
468}
469
470static bool probing_irq(int irq)
471{
472 struct irq_desc *desc = irq_to_desc(irq);
473
474 return desc && desc->action == NULL;
475}
476
c9e265e0 477static unsigned int __startup_pirq(unsigned int irq)
d46a78b0
JF
478{
479 struct evtchn_bind_pirq bind_pirq;
480 struct irq_info *info = info_for_irq(irq);
481 int evtchn = evtchn_from_irq(irq);
15ebbb82 482 int rc;
d46a78b0
JF
483
484 BUG_ON(info->type != IRQT_PIRQ);
485
486 if (VALID_EVTCHN(evtchn))
487 goto out;
488
7a043f11 489 bind_pirq.pirq = pirq_from_irq(irq);
d46a78b0 490 /* NB. We are happy to share unless we are probing. */
15ebbb82
KRW
491 bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
492 BIND_PIRQ__WILL_SHARE : 0;
493 rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
494 if (rc != 0) {
d46a78b0
JF
495 if (!probing_irq(irq))
496 printk(KERN_INFO "Failed to obtain physical IRQ %d\n",
497 irq);
498 return 0;
499 }
500 evtchn = bind_pirq.port;
501
502 pirq_query_unmask(irq);
503
504 evtchn_to_irq[evtchn] = irq;
505 bind_evtchn_to_cpu(evtchn, 0);
506 info->evtchn = evtchn;
507
508out:
509 unmask_evtchn(evtchn);
510 pirq_unmask_notify(irq);
511
512 return 0;
513}
514
c9e265e0
TG
515static unsigned int startup_pirq(struct irq_data *data)
516{
517 return __startup_pirq(data->irq);
518}
519
520static void shutdown_pirq(struct irq_data *data)
d46a78b0
JF
521{
522 struct evtchn_close close;
c9e265e0 523 unsigned int irq = data->irq;
d46a78b0
JF
524 struct irq_info *info = info_for_irq(irq);
525 int evtchn = evtchn_from_irq(irq);
526
527 BUG_ON(info->type != IRQT_PIRQ);
528
529 if (!VALID_EVTCHN(evtchn))
530 return;
531
532 mask_evtchn(evtchn);
533
534 close.port = evtchn;
535 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
536 BUG();
537
538 bind_evtchn_to_cpu(evtchn, 0);
539 evtchn_to_irq[evtchn] = -1;
540 info->evtchn = 0;
541}
542
c9e265e0 543static void enable_pirq(struct irq_data *data)
d46a78b0 544{
c9e265e0 545 startup_pirq(data);
d46a78b0
JF
546}
547
c9e265e0 548static void disable_pirq(struct irq_data *data)
d46a78b0
JF
549{
550}
551
c9e265e0 552static void ack_pirq(struct irq_data *data)
d46a78b0 553{
c9e265e0 554 int evtchn = evtchn_from_irq(data->irq);
d46a78b0 555
aa673c1c 556 move_native_irq(data->irq);
d46a78b0
JF
557
558 if (VALID_EVTCHN(evtchn)) {
559 mask_evtchn(evtchn);
560 clear_evtchn(evtchn);
561 }
562}
563
d46a78b0
JF
564static int find_irq_by_gsi(unsigned gsi)
565{
566 int irq;
567
b21ddbf5 568 for (irq = 0; irq < nr_irqs; irq++) {
d46a78b0
JF
569 struct irq_info *info = info_for_irq(irq);
570
571 if (info == NULL || info->type != IRQT_PIRQ)
572 continue;
573
574 if (gsi_from_irq(irq) == gsi)
575 return irq;
576 }
577
578 return -1;
579}
580
7a043f11
SS
581int xen_allocate_pirq(unsigned gsi, int shareable, char *name)
582{
583 return xen_map_pirq_gsi(gsi, gsi, shareable, name);
584}
585
586/* xen_map_pirq_gsi might allocate irqs from the top down, as a
3a69e916
KRW
587 * consequence don't assume that the irq number returned has a low value
588 * or can be used as a pirq number unless you know otherwise.
589 *
7a043f11 590 * One notable exception is when xen_map_pirq_gsi is called passing an
3a69e916 591 * hardware gsi as argument, in that case the irq number returned
7a043f11
SS
592 * matches the gsi number passed as second argument.
593 *
594 * Note: We don't assign an event channel until the irq actually started
595 * up. Return an existing irq if we've already got one for the gsi.
d46a78b0 596 */
7a043f11 597int xen_map_pirq_gsi(unsigned pirq, unsigned gsi, int shareable, char *name)
d46a78b0 598{
7a043f11 599 int irq = 0;
d46a78b0
JF
600 struct physdev_irq irq_op;
601
602 spin_lock(&irq_mapping_update_lock);
603
e5fc7345 604 if ((pirq > nr_irqs) || (gsi > nr_irqs)) {
01557baf 605 printk(KERN_WARNING "xen_map_pirq_gsi: %s %s is incorrect!\n",
e5fc7345
SS
606 pirq > nr_irqs ? "pirq" :"",
607 gsi > nr_irqs ? "gsi" : "");
01557baf
SS
608 goto out;
609 }
610
d46a78b0
JF
611 irq = find_irq_by_gsi(gsi);
612 if (irq != -1) {
7a043f11 613 printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n",
d46a78b0
JF
614 irq, gsi);
615 goto out; /* XXX need refcount? */
616 }
617
c9df1ce5 618 irq = xen_allocate_irq_gsi(gsi);
d46a78b0
JF
619
620 set_irq_chip_and_handler_name(irq, &xen_pirq_chip,
1a60d05f 621 handle_level_irq, name);
d46a78b0
JF
622
623 irq_op.irq = irq;
b5401a96
AN
624 irq_op.vector = 0;
625
626 /* Only the privileged domain can do this. For non-priv, the pcifront
627 * driver provides a PCI bus that does the call to do exactly
628 * this in the priv domain. */
629 if (xen_initial_domain() &&
630 HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
c9df1ce5 631 xen_free_irq(irq);
d46a78b0
JF
632 irq = -ENOSPC;
633 goto out;
634 }
635
7a043f11 636 irq_info[irq] = mk_pirq_info(0, pirq, gsi, irq_op.vector);
15ebbb82 637 irq_info[irq].u.pirq.flags |= shareable ? PIRQ_SHAREABLE : 0;
7a043f11 638 pirq_to_irq[pirq] = irq;
d46a78b0
JF
639
640out:
641 spin_unlock(&irq_mapping_update_lock);
642
643 return irq;
644}
645
f731e3ef 646#ifdef CONFIG_PCI_MSI
bf480d95 647int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc)
cbf6aa89 648{
5cad61a6 649 int rc;
cbf6aa89 650 struct physdev_get_free_pirq op_get_free_pirq;
cbf6aa89 651
bf480d95 652 op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI;
cbf6aa89 653 rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
cbf6aa89 654
5cad61a6
IC
655 WARN_ONCE(rc == -ENOSYS,
656 "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n");
657
658 return rc ? -1 : op_get_free_pirq.pirq;
cbf6aa89
IC
659}
660
bf480d95 661int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc,
ca1d8fe9 662 int pirq, int vector, const char *name)
809f9267 663{
bf480d95 664 int irq, ret;
4b41df7f 665
809f9267
SS
666 spin_lock(&irq_mapping_update_lock);
667
4b41df7f
IC
668 irq = xen_allocate_irq_dynamic();
669 if (irq == -1)
bb5d079a 670 goto out;
809f9267 671
4b41df7f 672 set_irq_chip_and_handler_name(irq, &xen_pirq_chip,
809f9267
SS
673 handle_level_irq, name);
674
ca1d8fe9 675 irq_info[irq] = mk_pirq_info(0, pirq, 0, vector);
bf480d95
IC
676 pirq_to_irq[pirq] = irq;
677 ret = set_irq_msi(irq, msidesc);
678 if (ret < 0)
679 goto error_irq;
809f9267
SS
680out:
681 spin_unlock(&irq_mapping_update_lock);
4b41df7f 682 return irq;
bf480d95
IC
683error_irq:
684 spin_unlock(&irq_mapping_update_lock);
685 xen_free_irq(irq);
686 return -1;
809f9267 687}
f731e3ef
QH
688#endif
689
b5401a96
AN
690int xen_destroy_irq(int irq)
691{
692 struct irq_desc *desc;
38aa66fc
JF
693 struct physdev_unmap_pirq unmap_irq;
694 struct irq_info *info = info_for_irq(irq);
b5401a96
AN
695 int rc = -ENOENT;
696
697 spin_lock(&irq_mapping_update_lock);
698
699 desc = irq_to_desc(irq);
700 if (!desc)
701 goto out;
702
38aa66fc 703 if (xen_initial_domain()) {
12334715 704 unmap_irq.pirq = info->u.pirq.pirq;
38aa66fc
JF
705 unmap_irq.domid = DOMID_SELF;
706 rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
707 if (rc) {
708 printk(KERN_WARNING "unmap irq failed %d\n", rc);
709 goto out;
710 }
711 }
1aa0b51a
KRW
712 pirq_to_irq[info->u.pirq.pirq] = -1;
713
b5401a96
AN
714 irq_info[irq] = mk_unbound_info();
715
c9df1ce5 716 xen_free_irq(irq);
b5401a96
AN
717
718out:
719 spin_unlock(&irq_mapping_update_lock);
720 return rc;
721}
722
d46a78b0
JF
723int xen_vector_from_irq(unsigned irq)
724{
725 return vector_from_irq(irq);
726}
727
728int xen_gsi_from_irq(unsigned irq)
729{
730 return gsi_from_irq(irq);
e46cdb66
JF
731}
732
af42b8d1
SS
733int xen_irq_from_pirq(unsigned pirq)
734{
735 return pirq_to_irq[pirq];
736}
737
b536b4b9 738int bind_evtchn_to_irq(unsigned int evtchn)
e46cdb66
JF
739{
740 int irq;
741
742 spin_lock(&irq_mapping_update_lock);
743
744 irq = evtchn_to_irq[evtchn];
745
746 if (irq == -1) {
c9df1ce5 747 irq = xen_allocate_irq_dynamic();
e46cdb66 748
e46cdb66 749 set_irq_chip_and_handler_name(irq, &xen_dynamic_chip,
3588fe2e 750 handle_fasteoi_irq, "event");
e46cdb66
JF
751
752 evtchn_to_irq[evtchn] = irq;
ced40d0f 753 irq_info[irq] = mk_evtchn_info(evtchn);
e46cdb66
JF
754 }
755
e46cdb66
JF
756 spin_unlock(&irq_mapping_update_lock);
757
758 return irq;
759}
b536b4b9 760EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
e46cdb66 761
f87e4cac
JF
762static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
763{
764 struct evtchn_bind_ipi bind_ipi;
765 int evtchn, irq;
766
767 spin_lock(&irq_mapping_update_lock);
768
769 irq = per_cpu(ipi_to_irq, cpu)[ipi];
90af9514 770
f87e4cac 771 if (irq == -1) {
c9df1ce5 772 irq = xen_allocate_irq_dynamic();
f87e4cac
JF
773 if (irq < 0)
774 goto out;
775
aaca4964
JF
776 set_irq_chip_and_handler_name(irq, &xen_percpu_chip,
777 handle_percpu_irq, "ipi");
f87e4cac
JF
778
779 bind_ipi.vcpu = cpu;
780 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
781 &bind_ipi) != 0)
782 BUG();
783 evtchn = bind_ipi.port;
784
785 evtchn_to_irq[evtchn] = irq;
ced40d0f 786 irq_info[irq] = mk_ipi_info(evtchn, ipi);
f87e4cac
JF
787 per_cpu(ipi_to_irq, cpu)[ipi] = irq;
788
789 bind_evtchn_to_cpu(evtchn, cpu);
790 }
791
f87e4cac
JF
792 out:
793 spin_unlock(&irq_mapping_update_lock);
794 return irq;
795}
796
797
4fe7d5a7 798int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
e46cdb66
JF
799{
800 struct evtchn_bind_virq bind_virq;
801 int evtchn, irq;
802
803 spin_lock(&irq_mapping_update_lock);
804
805 irq = per_cpu(virq_to_irq, cpu)[virq];
806
807 if (irq == -1) {
c9df1ce5 808 irq = xen_allocate_irq_dynamic();
a52521f1
JF
809
810 set_irq_chip_and_handler_name(irq, &xen_percpu_chip,
811 handle_percpu_irq, "virq");
812
e46cdb66
JF
813 bind_virq.virq = virq;
814 bind_virq.vcpu = cpu;
815 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
816 &bind_virq) != 0)
817 BUG();
818 evtchn = bind_virq.port;
819
e46cdb66 820 evtchn_to_irq[evtchn] = irq;
ced40d0f 821 irq_info[irq] = mk_virq_info(evtchn, virq);
e46cdb66
JF
822
823 per_cpu(virq_to_irq, cpu)[virq] = irq;
824
825 bind_evtchn_to_cpu(evtchn, cpu);
826 }
827
e46cdb66
JF
828 spin_unlock(&irq_mapping_update_lock);
829
830 return irq;
831}
832
833static void unbind_from_irq(unsigned int irq)
834{
835 struct evtchn_close close;
836 int evtchn = evtchn_from_irq(irq);
837
838 spin_lock(&irq_mapping_update_lock);
839
d77bbd4d 840 if (VALID_EVTCHN(evtchn)) {
e46cdb66
JF
841 close.port = evtchn;
842 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
843 BUG();
844
845 switch (type_from_irq(irq)) {
846 case IRQT_VIRQ:
847 per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 848 [virq_from_irq(irq)] = -1;
e46cdb66 849 break;
d68d82af
AN
850 case IRQT_IPI:
851 per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 852 [ipi_from_irq(irq)] = -1;
d68d82af 853 break;
e46cdb66
JF
854 default:
855 break;
856 }
857
858 /* Closed ports are implicitly re-bound to VCPU0. */
859 bind_evtchn_to_cpu(evtchn, 0);
860
861 evtchn_to_irq[evtchn] = -1;
fed5ea87
IC
862 }
863
864 if (irq_info[irq].type != IRQT_UNBOUND) {
ced40d0f 865 irq_info[irq] = mk_unbound_info();
e46cdb66 866
c9df1ce5 867 xen_free_irq(irq);
e46cdb66
JF
868 }
869
870 spin_unlock(&irq_mapping_update_lock);
871}
872
873int bind_evtchn_to_irqhandler(unsigned int evtchn,
7c239975 874 irq_handler_t handler,
e46cdb66
JF
875 unsigned long irqflags,
876 const char *devname, void *dev_id)
877{
878 unsigned int irq;
879 int retval;
880
881 irq = bind_evtchn_to_irq(evtchn);
882 retval = request_irq(irq, handler, irqflags, devname, dev_id);
883 if (retval != 0) {
884 unbind_from_irq(irq);
885 return retval;
886 }
887
888 return irq;
889}
890EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
891
892int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
7c239975 893 irq_handler_t handler,
e46cdb66
JF
894 unsigned long irqflags, const char *devname, void *dev_id)
895{
896 unsigned int irq;
897 int retval;
898
899 irq = bind_virq_to_irq(virq, cpu);
900 retval = request_irq(irq, handler, irqflags, devname, dev_id);
901 if (retval != 0) {
902 unbind_from_irq(irq);
903 return retval;
904 }
905
906 return irq;
907}
908EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
909
f87e4cac
JF
910int bind_ipi_to_irqhandler(enum ipi_vector ipi,
911 unsigned int cpu,
912 irq_handler_t handler,
913 unsigned long irqflags,
914 const char *devname,
915 void *dev_id)
916{
917 int irq, retval;
918
919 irq = bind_ipi_to_irq(ipi, cpu);
920 if (irq < 0)
921 return irq;
922
676dc3cf 923 irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME;
f87e4cac
JF
924 retval = request_irq(irq, handler, irqflags, devname, dev_id);
925 if (retval != 0) {
926 unbind_from_irq(irq);
927 return retval;
928 }
929
930 return irq;
931}
932
e46cdb66
JF
933void unbind_from_irqhandler(unsigned int irq, void *dev_id)
934{
935 free_irq(irq, dev_id);
936 unbind_from_irq(irq);
937}
938EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
939
f87e4cac
JF
940void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
941{
942 int irq = per_cpu(ipi_to_irq, cpu)[vector];
943 BUG_ON(irq < 0);
944 notify_remote_via_irq(irq);
945}
946
ee523ca1
JF
947irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
948{
949 struct shared_info *sh = HYPERVISOR_shared_info;
950 int cpu = smp_processor_id();
cb52e6d9 951 unsigned long *cpu_evtchn = cpu_evtchn_mask(cpu);
ee523ca1
JF
952 int i;
953 unsigned long flags;
954 static DEFINE_SPINLOCK(debug_lock);
cb52e6d9 955 struct vcpu_info *v;
ee523ca1
JF
956
957 spin_lock_irqsave(&debug_lock, flags);
958
cb52e6d9 959 printk("\nvcpu %d\n ", cpu);
ee523ca1
JF
960
961 for_each_online_cpu(i) {
cb52e6d9
IC
962 int pending;
963 v = per_cpu(xen_vcpu, i);
964 pending = (get_irq_regs() && i == cpu)
965 ? xen_irqs_disabled(get_irq_regs())
966 : v->evtchn_upcall_mask;
967 printk("%d: masked=%d pending=%d event_sel %0*lx\n ", i,
968 pending, v->evtchn_upcall_pending,
969 (int)(sizeof(v->evtchn_pending_sel)*2),
970 v->evtchn_pending_sel);
971 }
972 v = per_cpu(xen_vcpu, cpu);
973
974 printk("\npending:\n ");
975 for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
976 printk("%0*lx%s", (int)sizeof(sh->evtchn_pending[0])*2,
977 sh->evtchn_pending[i],
978 i % 8 == 0 ? "\n " : " ");
979 printk("\nglobal mask:\n ");
980 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
981 printk("%0*lx%s",
982 (int)(sizeof(sh->evtchn_mask[0])*2),
983 sh->evtchn_mask[i],
984 i % 8 == 0 ? "\n " : " ");
985
986 printk("\nglobally unmasked:\n ");
987 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
988 printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
989 sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
990 i % 8 == 0 ? "\n " : " ");
991
992 printk("\nlocal cpu%d mask:\n ", cpu);
993 for (i = (NR_EVENT_CHANNELS/BITS_PER_LONG)-1; i >= 0; i--)
994 printk("%0*lx%s", (int)(sizeof(cpu_evtchn[0])*2),
995 cpu_evtchn[i],
996 i % 8 == 0 ? "\n " : " ");
997
998 printk("\nlocally unmasked:\n ");
999 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
1000 unsigned long pending = sh->evtchn_pending[i]
1001 & ~sh->evtchn_mask[i]
1002 & cpu_evtchn[i];
1003 printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
1004 pending, i % 8 == 0 ? "\n " : " ");
ee523ca1 1005 }
ee523ca1
JF
1006
1007 printk("\npending list:\n");
cb52e6d9 1008 for (i = 0; i < NR_EVENT_CHANNELS; i++) {
ee523ca1 1009 if (sync_test_bit(i, sh->evtchn_pending)) {
cb52e6d9
IC
1010 int word_idx = i / BITS_PER_LONG;
1011 printk(" %d: event %d -> irq %d%s%s%s\n",
ced40d0f 1012 cpu_from_evtchn(i), i,
cb52e6d9
IC
1013 evtchn_to_irq[i],
1014 sync_test_bit(word_idx, &v->evtchn_pending_sel)
1015 ? "" : " l2-clear",
1016 !sync_test_bit(i, sh->evtchn_mask)
1017 ? "" : " globally-masked",
1018 sync_test_bit(i, cpu_evtchn)
1019 ? "" : " locally-masked");
ee523ca1
JF
1020 }
1021 }
1022
1023 spin_unlock_irqrestore(&debug_lock, flags);
1024
1025 return IRQ_HANDLED;
1026}
1027
245b2e70
TH
1028static DEFINE_PER_CPU(unsigned, xed_nesting_count);
1029
e46cdb66
JF
1030/*
1031 * Search the CPUs pending events bitmasks. For each one found, map
1032 * the event number to an irq, and feed it into do_IRQ() for
1033 * handling.
1034 *
1035 * Xen uses a two-level bitmap to speed searching. The first level is
1036 * a bitset of words which contain pending event bits. The second
1037 * level is a bitset of pending events themselves.
1038 */
38e20b07 1039static void __xen_evtchn_do_upcall(void)
e46cdb66
JF
1040{
1041 int cpu = get_cpu();
1042 struct shared_info *s = HYPERVISOR_shared_info;
780f36d8 1043 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
229664be 1044 unsigned count;
e46cdb66 1045
229664be
JF
1046 do {
1047 unsigned long pending_words;
e46cdb66 1048
229664be 1049 vcpu_info->evtchn_upcall_pending = 0;
e46cdb66 1050
b2e4ae69 1051 if (__this_cpu_inc_return(xed_nesting_count) - 1)
229664be 1052 goto out;
e46cdb66 1053
e849c3e9
IY
1054#ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */
1055 /* Clear master flag /before/ clearing selector flag. */
6673cf63 1056 wmb();
e849c3e9 1057#endif
229664be
JF
1058 pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0);
1059 while (pending_words != 0) {
1060 unsigned long pending_bits;
1061 int word_idx = __ffs(pending_words);
1062 pending_words &= ~(1UL << word_idx);
1063
1064 while ((pending_bits = active_evtchns(cpu, s, word_idx)) != 0) {
1065 int bit_idx = __ffs(pending_bits);
1066 int port = (word_idx * BITS_PER_LONG) + bit_idx;
1067 int irq = evtchn_to_irq[port];
ca4dbc66 1068 struct irq_desc *desc;
229664be 1069
3588fe2e
JF
1070 mask_evtchn(port);
1071 clear_evtchn(port);
1072
ca4dbc66
EB
1073 if (irq != -1) {
1074 desc = irq_to_desc(irq);
1075 if (desc)
1076 generic_handle_irq_desc(irq, desc);
1077 }
e46cdb66
JF
1078 }
1079 }
e46cdb66 1080
229664be
JF
1081 BUG_ON(!irqs_disabled());
1082
780f36d8
CL
1083 count = __this_cpu_read(xed_nesting_count);
1084 __this_cpu_write(xed_nesting_count, 0);
183d03cc 1085 } while (count != 1 || vcpu_info->evtchn_upcall_pending);
229664be
JF
1086
1087out:
38e20b07
SY
1088
1089 put_cpu();
1090}
1091
1092void xen_evtchn_do_upcall(struct pt_regs *regs)
1093{
1094 struct pt_regs *old_regs = set_irq_regs(regs);
1095
1096 exit_idle();
1097 irq_enter();
1098
1099 __xen_evtchn_do_upcall();
1100
3445a8fd
JF
1101 irq_exit();
1102 set_irq_regs(old_regs);
38e20b07 1103}
3445a8fd 1104
38e20b07
SY
1105void xen_hvm_evtchn_do_upcall(void)
1106{
1107 __xen_evtchn_do_upcall();
e46cdb66 1108}
183d03cc 1109EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
e46cdb66 1110
eb1e305f
JF
1111/* Rebind a new event channel to an existing irq. */
1112void rebind_evtchn_irq(int evtchn, int irq)
1113{
d77bbd4d
JF
1114 struct irq_info *info = info_for_irq(irq);
1115
eb1e305f
JF
1116 /* Make sure the irq is masked, since the new event channel
1117 will also be masked. */
1118 disable_irq(irq);
1119
1120 spin_lock(&irq_mapping_update_lock);
1121
1122 /* After resume the irq<->evtchn mappings are all cleared out */
1123 BUG_ON(evtchn_to_irq[evtchn] != -1);
1124 /* Expect irq to have been bound before,
d77bbd4d
JF
1125 so there should be a proper type */
1126 BUG_ON(info->type == IRQT_UNBOUND);
eb1e305f
JF
1127
1128 evtchn_to_irq[evtchn] = irq;
ced40d0f 1129 irq_info[irq] = mk_evtchn_info(evtchn);
eb1e305f
JF
1130
1131 spin_unlock(&irq_mapping_update_lock);
1132
1133 /* new event channels are always bound to cpu 0 */
0de26520 1134 irq_set_affinity(irq, cpumask_of(0));
eb1e305f
JF
1135
1136 /* Unmask the event channel. */
1137 enable_irq(irq);
1138}
1139
e46cdb66 1140/* Rebind an evtchn so that it gets delivered to a specific cpu */
d5dedd45 1141static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
e46cdb66
JF
1142{
1143 struct evtchn_bind_vcpu bind_vcpu;
1144 int evtchn = evtchn_from_irq(irq);
1145
183d03cc
SS
1146 /* events delivered via platform PCI interrupts are always
1147 * routed to vcpu 0 */
1148 if (!VALID_EVTCHN(evtchn) ||
1149 (xen_hvm_domain() && !xen_have_vector_callback))
d5dedd45 1150 return -1;
e46cdb66
JF
1151
1152 /* Send future instances of this interrupt to other vcpu. */
1153 bind_vcpu.port = evtchn;
1154 bind_vcpu.vcpu = tcpu;
1155
1156 /*
1157 * If this fails, it usually just indicates that we're dealing with a
1158 * virq or IPI channel, which don't actually need to be rebound. Ignore
1159 * it, but don't do the xenlinux-level rebind in that case.
1160 */
1161 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
1162 bind_evtchn_to_cpu(evtchn, tcpu);
e46cdb66 1163
d5dedd45
YL
1164 return 0;
1165}
e46cdb66 1166
c9e265e0
TG
1167static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest,
1168 bool force)
e46cdb66 1169{
0de26520 1170 unsigned tcpu = cpumask_first(dest);
d5dedd45 1171
c9e265e0 1172 return rebind_irq_to_cpu(data->irq, tcpu);
e46cdb66
JF
1173}
1174
642e0c88
IY
1175int resend_irq_on_evtchn(unsigned int irq)
1176{
1177 int masked, evtchn = evtchn_from_irq(irq);
1178 struct shared_info *s = HYPERVISOR_shared_info;
1179
1180 if (!VALID_EVTCHN(evtchn))
1181 return 1;
1182
1183 masked = sync_test_and_set_bit(evtchn, s->evtchn_mask);
1184 sync_set_bit(evtchn, s->evtchn_pending);
1185 if (!masked)
1186 unmask_evtchn(evtchn);
1187
1188 return 1;
1189}
1190
c9e265e0 1191static void enable_dynirq(struct irq_data *data)
e46cdb66 1192{
c9e265e0 1193 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1194
1195 if (VALID_EVTCHN(evtchn))
1196 unmask_evtchn(evtchn);
1197}
1198
c9e265e0 1199static void disable_dynirq(struct irq_data *data)
e46cdb66 1200{
c9e265e0 1201 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1202
1203 if (VALID_EVTCHN(evtchn))
1204 mask_evtchn(evtchn);
1205}
1206
c9e265e0 1207static void ack_dynirq(struct irq_data *data)
e46cdb66 1208{
c9e265e0 1209 int evtchn = evtchn_from_irq(data->irq);
e46cdb66 1210
c9e265e0 1211 move_masked_irq(data->irq);
e46cdb66
JF
1212
1213 if (VALID_EVTCHN(evtchn))
3588fe2e 1214 unmask_evtchn(evtchn);
e46cdb66
JF
1215}
1216
c9e265e0 1217static int retrigger_dynirq(struct irq_data *data)
e46cdb66 1218{
c9e265e0 1219 int evtchn = evtchn_from_irq(data->irq);
ee8fa1c6 1220 struct shared_info *sh = HYPERVISOR_shared_info;
e46cdb66
JF
1221 int ret = 0;
1222
1223 if (VALID_EVTCHN(evtchn)) {
ee8fa1c6
JF
1224 int masked;
1225
1226 masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask);
1227 sync_set_bit(evtchn, sh->evtchn_pending);
1228 if (!masked)
1229 unmask_evtchn(evtchn);
e46cdb66
JF
1230 ret = 1;
1231 }
1232
1233 return ret;
1234}
1235
9a069c33
SS
1236static void restore_cpu_pirqs(void)
1237{
1238 int pirq, rc, irq, gsi;
1239 struct physdev_map_pirq map_irq;
1240
1241 for (pirq = 0; pirq < nr_irqs; pirq++) {
1242 irq = pirq_to_irq[pirq];
1243 if (irq == -1)
1244 continue;
1245
1246 /* save/restore of PT devices doesn't work, so at this point the
1247 * only devices present are GSI based emulated devices */
1248 gsi = gsi_from_irq(irq);
1249 if (!gsi)
1250 continue;
1251
1252 map_irq.domid = DOMID_SELF;
1253 map_irq.type = MAP_PIRQ_TYPE_GSI;
1254 map_irq.index = gsi;
1255 map_irq.pirq = pirq;
1256
1257 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
1258 if (rc) {
1259 printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
1260 gsi, irq, pirq, rc);
1261 irq_info[irq] = mk_unbound_info();
1262 pirq_to_irq[pirq] = -1;
1263 continue;
1264 }
1265
1266 printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
1267
c9e265e0 1268 __startup_pirq(irq);
9a069c33
SS
1269 }
1270}
1271
0e91398f
JF
1272static void restore_cpu_virqs(unsigned int cpu)
1273{
1274 struct evtchn_bind_virq bind_virq;
1275 int virq, irq, evtchn;
1276
1277 for (virq = 0; virq < NR_VIRQS; virq++) {
1278 if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
1279 continue;
1280
ced40d0f 1281 BUG_ON(virq_from_irq(irq) != virq);
0e91398f
JF
1282
1283 /* Get a new binding from Xen. */
1284 bind_virq.virq = virq;
1285 bind_virq.vcpu = cpu;
1286 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
1287 &bind_virq) != 0)
1288 BUG();
1289 evtchn = bind_virq.port;
1290
1291 /* Record the new mapping. */
1292 evtchn_to_irq[evtchn] = irq;
ced40d0f 1293 irq_info[irq] = mk_virq_info(evtchn, virq);
0e91398f 1294 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1295 }
1296}
1297
1298static void restore_cpu_ipis(unsigned int cpu)
1299{
1300 struct evtchn_bind_ipi bind_ipi;
1301 int ipi, irq, evtchn;
1302
1303 for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
1304 if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
1305 continue;
1306
ced40d0f 1307 BUG_ON(ipi_from_irq(irq) != ipi);
0e91398f
JF
1308
1309 /* Get a new binding from Xen. */
1310 bind_ipi.vcpu = cpu;
1311 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
1312 &bind_ipi) != 0)
1313 BUG();
1314 evtchn = bind_ipi.port;
1315
1316 /* Record the new mapping. */
1317 evtchn_to_irq[evtchn] = irq;
ced40d0f 1318 irq_info[irq] = mk_ipi_info(evtchn, ipi);
0e91398f 1319 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1320 }
1321}
1322
2d9e1e2f
JF
1323/* Clear an irq's pending state, in preparation for polling on it */
1324void xen_clear_irq_pending(int irq)
1325{
1326 int evtchn = evtchn_from_irq(irq);
1327
1328 if (VALID_EVTCHN(evtchn))
1329 clear_evtchn(evtchn);
1330}
d9a8814f 1331EXPORT_SYMBOL(xen_clear_irq_pending);
168d2f46
JF
1332void xen_set_irq_pending(int irq)
1333{
1334 int evtchn = evtchn_from_irq(irq);
1335
1336 if (VALID_EVTCHN(evtchn))
1337 set_evtchn(evtchn);
1338}
1339
1340bool xen_test_irq_pending(int irq)
1341{
1342 int evtchn = evtchn_from_irq(irq);
1343 bool ret = false;
1344
1345 if (VALID_EVTCHN(evtchn))
1346 ret = test_evtchn(evtchn);
1347
1348 return ret;
1349}
1350
d9a8814f
KRW
1351/* Poll waiting for an irq to become pending with timeout. In the usual case,
1352 * the irq will be disabled so it won't deliver an interrupt. */
1353void xen_poll_irq_timeout(int irq, u64 timeout)
2d9e1e2f
JF
1354{
1355 evtchn_port_t evtchn = evtchn_from_irq(irq);
1356
1357 if (VALID_EVTCHN(evtchn)) {
1358 struct sched_poll poll;
1359
1360 poll.nr_ports = 1;
d9a8814f 1361 poll.timeout = timeout;
ff3c5362 1362 set_xen_guest_handle(poll.ports, &evtchn);
2d9e1e2f
JF
1363
1364 if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
1365 BUG();
1366 }
1367}
d9a8814f
KRW
1368EXPORT_SYMBOL(xen_poll_irq_timeout);
1369/* Poll waiting for an irq to become pending. In the usual case, the
1370 * irq will be disabled so it won't deliver an interrupt. */
1371void xen_poll_irq(int irq)
1372{
1373 xen_poll_irq_timeout(irq, 0 /* no timeout */);
1374}
2d9e1e2f 1375
0e91398f
JF
1376void xen_irq_resume(void)
1377{
1378 unsigned int cpu, irq, evtchn;
1379
1380 init_evtchn_cpu_bindings();
1381
1382 /* New event-channel space is not 'live' yet. */
1383 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1384 mask_evtchn(evtchn);
1385
1386 /* No IRQ <-> event-channel mappings. */
0b8f1efa 1387 for (irq = 0; irq < nr_irqs; irq++)
0e91398f
JF
1388 irq_info[irq].evtchn = 0; /* zap event-channel binding */
1389
1390 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1391 evtchn_to_irq[evtchn] = -1;
1392
1393 for_each_possible_cpu(cpu) {
1394 restore_cpu_virqs(cpu);
1395 restore_cpu_ipis(cpu);
1396 }
6903591f 1397
9a069c33 1398 restore_cpu_pirqs();
0e91398f
JF
1399}
1400
e46cdb66 1401static struct irq_chip xen_dynamic_chip __read_mostly = {
c9e265e0 1402 .name = "xen-dyn",
54a353a0 1403
c9e265e0
TG
1404 .irq_disable = disable_dynirq,
1405 .irq_mask = disable_dynirq,
1406 .irq_unmask = enable_dynirq,
54a353a0 1407
c9e265e0
TG
1408 .irq_eoi = ack_dynirq,
1409 .irq_set_affinity = set_affinity_irq,
1410 .irq_retrigger = retrigger_dynirq,
e46cdb66
JF
1411};
1412
d46a78b0 1413static struct irq_chip xen_pirq_chip __read_mostly = {
c9e265e0 1414 .name = "xen-pirq",
d46a78b0 1415
c9e265e0
TG
1416 .irq_startup = startup_pirq,
1417 .irq_shutdown = shutdown_pirq,
d46a78b0 1418
c9e265e0
TG
1419 .irq_enable = enable_pirq,
1420 .irq_unmask = enable_pirq,
d46a78b0 1421
c9e265e0
TG
1422 .irq_disable = disable_pirq,
1423 .irq_mask = disable_pirq,
d46a78b0 1424
c9e265e0 1425 .irq_ack = ack_pirq,
d46a78b0 1426
c9e265e0 1427 .irq_set_affinity = set_affinity_irq,
d46a78b0 1428
c9e265e0 1429 .irq_retrigger = retrigger_dynirq,
d46a78b0
JF
1430};
1431
aaca4964 1432static struct irq_chip xen_percpu_chip __read_mostly = {
c9e265e0 1433 .name = "xen-percpu",
aaca4964 1434
c9e265e0
TG
1435 .irq_disable = disable_dynirq,
1436 .irq_mask = disable_dynirq,
1437 .irq_unmask = enable_dynirq,
aaca4964 1438
c9e265e0 1439 .irq_ack = ack_dynirq,
aaca4964
JF
1440};
1441
38e20b07
SY
1442int xen_set_callback_via(uint64_t via)
1443{
1444 struct xen_hvm_param a;
1445 a.domid = DOMID_SELF;
1446 a.index = HVM_PARAM_CALLBACK_IRQ;
1447 a.value = via;
1448 return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
1449}
1450EXPORT_SYMBOL_GPL(xen_set_callback_via);
1451
ca65f9fc 1452#ifdef CONFIG_XEN_PVHVM
38e20b07
SY
1453/* Vector callbacks are better than PCI interrupts to receive event
1454 * channel notifications because we can receive vector callbacks on any
1455 * vcpu and we don't need PCI support or APIC interactions. */
1456void xen_callback_vector(void)
1457{
1458 int rc;
1459 uint64_t callback_via;
1460 if (xen_have_vector_callback) {
1461 callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK);
1462 rc = xen_set_callback_via(callback_via);
1463 if (rc) {
1464 printk(KERN_ERR "Request for Xen HVM callback vector"
1465 " failed.\n");
1466 xen_have_vector_callback = 0;
1467 return;
1468 }
1469 printk(KERN_INFO "Xen HVM callback vector for event delivery is "
1470 "enabled\n");
1471 /* in the restore case the vector has already been allocated */
1472 if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors))
1473 alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector);
1474 }
1475}
ca65f9fc
SS
1476#else
1477void xen_callback_vector(void) {}
1478#endif
38e20b07 1479
e46cdb66
JF
1480void __init xen_init_IRQ(void)
1481{
e5fc7345 1482 int i;
c7a3589e 1483
a70c352a
PE
1484 cpu_evtchn_mask_p = kcalloc(nr_cpu_ids, sizeof(struct cpu_evtchn_s),
1485 GFP_KERNEL);
b21ddbf5
JF
1486 irq_info = kcalloc(nr_irqs, sizeof(*irq_info), GFP_KERNEL);
1487
e5fc7345
SS
1488 /* We are using nr_irqs as the maximum number of pirq available but
1489 * that number is actually chosen by Xen and we don't know exactly
1490 * what it is. Be careful choosing high pirq numbers. */
1491 pirq_to_irq = kcalloc(nr_irqs, sizeof(*pirq_to_irq), GFP_KERNEL);
1492 for (i = 0; i < nr_irqs; i++)
7a043f11
SS
1493 pirq_to_irq[i] = -1;
1494
b21ddbf5
JF
1495 evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
1496 GFP_KERNEL);
1497 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1498 evtchn_to_irq[i] = -1;
e46cdb66
JF
1499
1500 init_evtchn_cpu_bindings();
1501
1502 /* No event channels are 'live' right now. */
1503 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1504 mask_evtchn(i);
1505
38e20b07
SY
1506 if (xen_hvm_domain()) {
1507 xen_callback_vector();
1508 native_init_IRQ();
3942b740
SS
1509 /* pci_xen_hvm_init must be called after native_init_IRQ so that
1510 * __acpi_register_gsi can point at the right function */
1511 pci_xen_hvm_init();
38e20b07
SY
1512 } else {
1513 irq_ctx_init(smp_processor_id());
38aa66fc
JF
1514 if (xen_initial_domain())
1515 xen_setup_pirqs();
38e20b07 1516 }
e46cdb66 1517}
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