xen: events: push setup of irq<->{evtchn,ipi,virq,pirq} maps into irq_info init functions
[deliverable/linux.git] / drivers / xen / events.c
CommitLineData
e46cdb66
JF
1/*
2 * Xen event channels
3 *
4 * Xen models interrupts with abstract event channels. Because each
5 * domain gets 1024 event channels, but NR_IRQ is not that large, we
6 * must dynamically map irqs<->event channels. The event channels
7 * interface with the rest of the kernel by defining a xen interrupt
8 * chip. When an event is recieved, it is mapped to an irq and sent
9 * through the normal interrupt processing path.
10 *
11 * There are four kinds of events which can be mapped to an event
12 * channel:
13 *
14 * 1. Inter-domain notifications. This includes all the virtual
15 * device events, since they're driven by front-ends in another domain
16 * (typically dom0).
17 * 2. VIRQs, typically used for timers. These are per-cpu events.
18 * 3. IPIs.
d46a78b0 19 * 4. PIRQs - Hardware interrupts.
e46cdb66
JF
20 *
21 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
22 */
23
24#include <linux/linkage.h>
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/module.h>
28#include <linux/string.h>
28e08861 29#include <linux/bootmem.h>
5a0e3ad6 30#include <linux/slab.h>
b21ddbf5 31#include <linux/irqnr.h>
f731e3ef 32#include <linux/pci.h>
e46cdb66 33
38e20b07 34#include <asm/desc.h>
e46cdb66
JF
35#include <asm/ptrace.h>
36#include <asm/irq.h>
792dc4f6 37#include <asm/idle.h>
0794bfc7 38#include <asm/io_apic.h>
e46cdb66 39#include <asm/sync_bitops.h>
42a1de56 40#include <asm/xen/pci.h>
e46cdb66 41#include <asm/xen/hypercall.h>
8d1b8753 42#include <asm/xen/hypervisor.h>
e46cdb66 43
38e20b07
SY
44#include <xen/xen.h>
45#include <xen/hvm.h>
e04d0d07 46#include <xen/xen-ops.h>
e46cdb66
JF
47#include <xen/events.h>
48#include <xen/interface/xen.h>
49#include <xen/interface/event_channel.h>
38e20b07
SY
50#include <xen/interface/hvm/hvm_op.h>
51#include <xen/interface/hvm/params.h>
e46cdb66 52
e46cdb66
JF
53/*
54 * This lock protects updates to the following mapping and reference-count
55 * arrays. The lock does not need to be acquired to read the mapping tables.
56 */
57static DEFINE_SPINLOCK(irq_mapping_update_lock);
58
59/* IRQ <-> VIRQ mapping. */
204fba4a 60static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
e46cdb66 61
f87e4cac 62/* IRQ <-> IPI mapping */
204fba4a 63static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
f87e4cac 64
ced40d0f
JF
65/* Interrupt types. */
66enum xen_irq_type {
d77bbd4d 67 IRQT_UNBOUND = 0,
f87e4cac
JF
68 IRQT_PIRQ,
69 IRQT_VIRQ,
70 IRQT_IPI,
71 IRQT_EVTCHN
72};
e46cdb66 73
ced40d0f
JF
74/*
75 * Packed IRQ information:
76 * type - enum xen_irq_type
77 * event channel - irq->event channel mapping
78 * cpu - cpu this event channel is bound to
79 * index - type-specific information:
42a1de56
SS
80 * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM
81 * guest, or GSI (real passthrough IRQ) of the device.
ced40d0f
JF
82 * VIRQ - virq number
83 * IPI - IPI vector
84 * EVTCHN -
85 */
86struct irq_info
87{
88 enum xen_irq_type type; /* type */
89 unsigned short evtchn; /* event channel */
90 unsigned short cpu; /* cpu bound */
91
92 union {
93 unsigned short virq;
94 enum ipi_vector ipi;
95 struct {
7a043f11 96 unsigned short pirq;
ced40d0f 97 unsigned short gsi;
d46a78b0
JF
98 unsigned char vector;
99 unsigned char flags;
ced40d0f
JF
100 } pirq;
101 } u;
102};
d46a78b0 103#define PIRQ_NEEDS_EOI (1 << 0)
15ebbb82 104#define PIRQ_SHAREABLE (1 << 1)
ced40d0f 105
b21ddbf5 106static struct irq_info *irq_info;
7a043f11 107static int *pirq_to_irq;
e46cdb66 108
b21ddbf5 109static int *evtchn_to_irq;
3b32f574 110
cb60d114
IC
111static DEFINE_PER_CPU(unsigned long [NR_EVENT_CHANNELS/BITS_PER_LONG],
112 cpu_evtchn_mask);
e46cdb66 113
e46cdb66
JF
114/* Xen will never allocate port zero for any purpose. */
115#define VALID_EVTCHN(chn) ((chn) != 0)
116
e46cdb66 117static struct irq_chip xen_dynamic_chip;
aaca4964 118static struct irq_chip xen_percpu_chip;
d46a78b0 119static struct irq_chip xen_pirq_chip;
e46cdb66 120
9158c358
IC
121/* Get info for IRQ */
122static struct irq_info *info_for_irq(unsigned irq)
ced40d0f 123{
9158c358 124 return &irq_info[irq];
ced40d0f
JF
125}
126
9158c358
IC
127/* Constructors for packed IRQ information. */
128static void xen_irq_info_common_init(struct irq_info *info,
3d4cfa37 129 unsigned irq,
9158c358
IC
130 enum xen_irq_type type,
131 unsigned short evtchn,
132 unsigned short cpu)
ced40d0f 133{
9158c358
IC
134
135 BUG_ON(info->type != IRQT_UNBOUND && info->type != type);
136
137 info->type = type;
138 info->evtchn = evtchn;
139 info->cpu = cpu;
3d4cfa37
IC
140
141 evtchn_to_irq[evtchn] = irq;
ced40d0f
JF
142}
143
9158c358
IC
144static void xen_irq_info_evtchn_init(unsigned irq,
145 unsigned short evtchn)
e46cdb66 146{
9158c358
IC
147 struct irq_info *info = info_for_irq(irq);
148
3d4cfa37 149 xen_irq_info_common_init(info, irq, IRQT_EVTCHN, evtchn, 0);
ced40d0f
JF
150}
151
3d4cfa37
IC
152static void xen_irq_info_ipi_init(unsigned cpu,
153 unsigned irq,
9158c358
IC
154 unsigned short evtchn,
155 enum ipi_vector ipi)
ced40d0f 156{
9158c358
IC
157 struct irq_info *info = info_for_irq(irq);
158
3d4cfa37 159 xen_irq_info_common_init(info, irq, IRQT_IPI, evtchn, 0);
9158c358
IC
160
161 info->u.ipi = ipi;
3d4cfa37
IC
162
163 per_cpu(ipi_to_irq, cpu)[ipi] = irq;
ced40d0f
JF
164}
165
3d4cfa37
IC
166static void xen_irq_info_virq_init(unsigned cpu,
167 unsigned irq,
9158c358
IC
168 unsigned short evtchn,
169 unsigned short virq)
ced40d0f 170{
9158c358
IC
171 struct irq_info *info = info_for_irq(irq);
172
3d4cfa37 173 xen_irq_info_common_init(info, irq, IRQT_VIRQ, evtchn, 0);
9158c358
IC
174
175 info->u.virq = virq;
3d4cfa37
IC
176
177 per_cpu(virq_to_irq, cpu)[virq] = irq;
e46cdb66
JF
178}
179
9158c358
IC
180static void xen_irq_info_pirq_init(unsigned irq,
181 unsigned short evtchn,
182 unsigned short pirq,
183 unsigned short gsi,
184 unsigned short vector,
185 unsigned char flags)
e46cdb66 186{
9158c358
IC
187 struct irq_info *info = info_for_irq(irq);
188
3d4cfa37 189 xen_irq_info_common_init(info, irq, IRQT_PIRQ, evtchn, 0);
9158c358
IC
190
191 info->u.pirq.pirq = pirq;
192 info->u.pirq.gsi = gsi;
193 info->u.pirq.vector = vector;
194 info->u.pirq.flags = flags;
3d4cfa37
IC
195
196 pirq_to_irq[pirq] = irq;
e46cdb66
JF
197}
198
9158c358
IC
199/*
200 * Accessors for packed IRQ information.
201 */
ced40d0f 202static unsigned int evtchn_from_irq(unsigned irq)
e46cdb66 203{
110e7c7e
JJ
204 if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
205 return 0;
206
ced40d0f 207 return info_for_irq(irq)->evtchn;
e46cdb66
JF
208}
209
d4c04536
IC
210unsigned irq_from_evtchn(unsigned int evtchn)
211{
212 return evtchn_to_irq[evtchn];
213}
214EXPORT_SYMBOL_GPL(irq_from_evtchn);
215
ced40d0f 216static enum ipi_vector ipi_from_irq(unsigned irq)
e46cdb66 217{
ced40d0f
JF
218 struct irq_info *info = info_for_irq(irq);
219
220 BUG_ON(info == NULL);
221 BUG_ON(info->type != IRQT_IPI);
222
223 return info->u.ipi;
224}
225
226static unsigned virq_from_irq(unsigned irq)
227{
228 struct irq_info *info = info_for_irq(irq);
229
230 BUG_ON(info == NULL);
231 BUG_ON(info->type != IRQT_VIRQ);
232
233 return info->u.virq;
234}
235
7a043f11
SS
236static unsigned pirq_from_irq(unsigned irq)
237{
238 struct irq_info *info = info_for_irq(irq);
239
240 BUG_ON(info == NULL);
241 BUG_ON(info->type != IRQT_PIRQ);
242
243 return info->u.pirq.pirq;
244}
245
ced40d0f
JF
246static unsigned gsi_from_irq(unsigned irq)
247{
248 struct irq_info *info = info_for_irq(irq);
249
250 BUG_ON(info == NULL);
251 BUG_ON(info->type != IRQT_PIRQ);
252
253 return info->u.pirq.gsi;
254}
255
ced40d0f
JF
256static enum xen_irq_type type_from_irq(unsigned irq)
257{
258 return info_for_irq(irq)->type;
259}
260
261static unsigned cpu_from_irq(unsigned irq)
262{
263 return info_for_irq(irq)->cpu;
264}
265
266static unsigned int cpu_from_evtchn(unsigned int evtchn)
267{
268 int irq = evtchn_to_irq[evtchn];
269 unsigned ret = 0;
270
271 if (irq != -1)
272 ret = cpu_from_irq(irq);
273
274 return ret;
e46cdb66
JF
275}
276
d46a78b0
JF
277static bool pirq_needs_eoi(unsigned irq)
278{
279 struct irq_info *info = info_for_irq(irq);
280
281 BUG_ON(info->type != IRQT_PIRQ);
282
283 return info->u.pirq.flags & PIRQ_NEEDS_EOI;
284}
285
e46cdb66
JF
286static inline unsigned long active_evtchns(unsigned int cpu,
287 struct shared_info *sh,
288 unsigned int idx)
289{
290 return (sh->evtchn_pending[idx] &
cb60d114 291 per_cpu(cpu_evtchn_mask, cpu)[idx] &
e46cdb66
JF
292 ~sh->evtchn_mask[idx]);
293}
294
295static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
296{
297 int irq = evtchn_to_irq[chn];
298
299 BUG_ON(irq == -1);
300#ifdef CONFIG_SMP
c9e265e0 301 cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu));
e46cdb66
JF
302#endif
303
cb60d114
IC
304 clear_bit(chn, per_cpu(cpu_evtchn_mask, cpu_from_irq(irq)));
305 set_bit(chn, per_cpu(cpu_evtchn_mask, cpu));
e46cdb66 306
ced40d0f 307 irq_info[irq].cpu = cpu;
e46cdb66
JF
308}
309
310static void init_evtchn_cpu_bindings(void)
311{
1c6969ec 312 int i;
e46cdb66 313#ifdef CONFIG_SMP
10e58084 314 struct irq_desc *desc;
10e58084 315
e46cdb66 316 /* By default all event channels notify CPU#0. */
0b8f1efa 317 for_each_irq_desc(i, desc) {
c9e265e0 318 cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
0b8f1efa 319 }
e46cdb66
JF
320#endif
321
1c6969ec 322 for_each_possible_cpu(i)
cb60d114
IC
323 memset(per_cpu(cpu_evtchn_mask, i),
324 (i == 0) ? ~0 : 0, sizeof(*per_cpu(cpu_evtchn_mask, i)));
1c6969ec 325
e46cdb66
JF
326}
327
e46cdb66
JF
328static inline void clear_evtchn(int port)
329{
330 struct shared_info *s = HYPERVISOR_shared_info;
331 sync_clear_bit(port, &s->evtchn_pending[0]);
332}
333
334static inline void set_evtchn(int port)
335{
336 struct shared_info *s = HYPERVISOR_shared_info;
337 sync_set_bit(port, &s->evtchn_pending[0]);
338}
339
168d2f46
JF
340static inline int test_evtchn(int port)
341{
342 struct shared_info *s = HYPERVISOR_shared_info;
343 return sync_test_bit(port, &s->evtchn_pending[0]);
344}
345
e46cdb66
JF
346
347/**
348 * notify_remote_via_irq - send event to remote end of event channel via irq
349 * @irq: irq of event channel to send event to
350 *
351 * Unlike notify_remote_via_evtchn(), this is safe to use across
352 * save/restore. Notifications on a broken connection are silently
353 * dropped.
354 */
355void notify_remote_via_irq(int irq)
356{
357 int evtchn = evtchn_from_irq(irq);
358
359 if (VALID_EVTCHN(evtchn))
360 notify_remote_via_evtchn(evtchn);
361}
362EXPORT_SYMBOL_GPL(notify_remote_via_irq);
363
364static void mask_evtchn(int port)
365{
366 struct shared_info *s = HYPERVISOR_shared_info;
367 sync_set_bit(port, &s->evtchn_mask[0]);
368}
369
370static void unmask_evtchn(int port)
371{
372 struct shared_info *s = HYPERVISOR_shared_info;
373 unsigned int cpu = get_cpu();
374
375 BUG_ON(!irqs_disabled());
376
377 /* Slow path (hypercall) if this is a non-local port. */
378 if (unlikely(cpu != cpu_from_evtchn(port))) {
379 struct evtchn_unmask unmask = { .port = port };
380 (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
381 } else {
780f36d8 382 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
e46cdb66
JF
383
384 sync_clear_bit(port, &s->evtchn_mask[0]);
385
386 /*
387 * The following is basically the equivalent of
388 * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
389 * the interrupt edge' if the channel is masked.
390 */
391 if (sync_test_bit(port, &s->evtchn_pending[0]) &&
392 !sync_test_and_set_bit(port / BITS_PER_LONG,
393 &vcpu_info->evtchn_pending_sel))
394 vcpu_info->evtchn_upcall_pending = 1;
395 }
396
397 put_cpu();
398}
399
89911501 400static int xen_allocate_irq_dynamic(void)
0794bfc7 401{
89911501
IC
402 int first = 0;
403 int irq;
0794bfc7
KRW
404
405#ifdef CONFIG_X86_IO_APIC
89911501
IC
406 /*
407 * For an HVM guest or domain 0 which see "real" (emulated or
408 * actual repectively) GSIs we allocate dynamic IRQs
409 * e.g. those corresponding to event channels or MSIs
410 * etc. from the range above those "real" GSIs to avoid
411 * collisions.
412 */
413 if (xen_initial_domain() || xen_hvm_domain())
414 first = get_nr_irqs_gsi();
0794bfc7
KRW
415#endif
416
89911501
IC
417retry:
418 irq = irq_alloc_desc_from(first, -1);
3a69e916 419
89911501
IC
420 if (irq == -ENOMEM && first > NR_IRQS_LEGACY) {
421 printk(KERN_ERR "Out of dynamic IRQ space and eating into GSI space. You should increase nr_irqs\n");
422 first = max(NR_IRQS_LEGACY, first - NR_IRQS_LEGACY);
423 goto retry;
99ad198c 424 }
e46cdb66 425
89911501
IC
426 if (irq < 0)
427 panic("No available IRQ to bind to: increase nr_irqs!\n");
ced40d0f 428
e46cdb66 429 return irq;
d46a78b0
JF
430}
431
c9df1ce5
IC
432static int xen_allocate_irq_gsi(unsigned gsi)
433{
434 int irq;
435
89911501
IC
436 /*
437 * A PV guest has no concept of a GSI (since it has no ACPI
438 * nor access to/knowledge of the physical APICs). Therefore
439 * all IRQs are dynamically allocated from the entire IRQ
440 * space.
441 */
442 if (xen_pv_domain() && !xen_initial_domain())
c9df1ce5
IC
443 return xen_allocate_irq_dynamic();
444
445 /* Legacy IRQ descriptors are already allocated by the arch. */
446 if (gsi < NR_IRQS_LEGACY)
447 return gsi;
448
449 irq = irq_alloc_desc_at(gsi, -1);
450 if (irq < 0)
451 panic("Unable to allocate to IRQ%d (%d)\n", gsi, irq);
452
453 return irq;
454}
455
456static void xen_free_irq(unsigned irq)
457{
9158c358
IC
458 irq_info[irq].type = IRQT_UNBOUND;
459
72146104
IC
460 /* Legacy IRQ descriptors are managed by the arch. */
461 if (irq < NR_IRQS_LEGACY)
462 return;
463
c9df1ce5
IC
464 irq_free_desc(irq);
465}
466
d46a78b0
JF
467static void pirq_unmask_notify(int irq)
468{
7a043f11 469 struct physdev_eoi eoi = { .irq = pirq_from_irq(irq) };
d46a78b0
JF
470
471 if (unlikely(pirq_needs_eoi(irq))) {
472 int rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
473 WARN_ON(rc);
474 }
475}
476
477static void pirq_query_unmask(int irq)
478{
479 struct physdev_irq_status_query irq_status;
480 struct irq_info *info = info_for_irq(irq);
481
482 BUG_ON(info->type != IRQT_PIRQ);
483
7a043f11 484 irq_status.irq = pirq_from_irq(irq);
d46a78b0
JF
485 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
486 irq_status.flags = 0;
487
488 info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
489 if (irq_status.flags & XENIRQSTAT_needs_eoi)
490 info->u.pirq.flags |= PIRQ_NEEDS_EOI;
491}
492
493static bool probing_irq(int irq)
494{
495 struct irq_desc *desc = irq_to_desc(irq);
496
497 return desc && desc->action == NULL;
498}
499
c9e265e0 500static unsigned int __startup_pirq(unsigned int irq)
d46a78b0
JF
501{
502 struct evtchn_bind_pirq bind_pirq;
503 struct irq_info *info = info_for_irq(irq);
504 int evtchn = evtchn_from_irq(irq);
15ebbb82 505 int rc;
d46a78b0
JF
506
507 BUG_ON(info->type != IRQT_PIRQ);
508
509 if (VALID_EVTCHN(evtchn))
510 goto out;
511
7a043f11 512 bind_pirq.pirq = pirq_from_irq(irq);
d46a78b0 513 /* NB. We are happy to share unless we are probing. */
15ebbb82
KRW
514 bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
515 BIND_PIRQ__WILL_SHARE : 0;
516 rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
517 if (rc != 0) {
d46a78b0
JF
518 if (!probing_irq(irq))
519 printk(KERN_INFO "Failed to obtain physical IRQ %d\n",
520 irq);
521 return 0;
522 }
523 evtchn = bind_pirq.port;
524
525 pirq_query_unmask(irq);
526
527 evtchn_to_irq[evtchn] = irq;
528 bind_evtchn_to_cpu(evtchn, 0);
529 info->evtchn = evtchn;
530
531out:
532 unmask_evtchn(evtchn);
533 pirq_unmask_notify(irq);
534
535 return 0;
536}
537
c9e265e0
TG
538static unsigned int startup_pirq(struct irq_data *data)
539{
540 return __startup_pirq(data->irq);
541}
542
543static void shutdown_pirq(struct irq_data *data)
d46a78b0
JF
544{
545 struct evtchn_close close;
c9e265e0 546 unsigned int irq = data->irq;
d46a78b0
JF
547 struct irq_info *info = info_for_irq(irq);
548 int evtchn = evtchn_from_irq(irq);
549
550 BUG_ON(info->type != IRQT_PIRQ);
551
552 if (!VALID_EVTCHN(evtchn))
553 return;
554
555 mask_evtchn(evtchn);
556
557 close.port = evtchn;
558 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
559 BUG();
560
561 bind_evtchn_to_cpu(evtchn, 0);
562 evtchn_to_irq[evtchn] = -1;
563 info->evtchn = 0;
564}
565
c9e265e0 566static void enable_pirq(struct irq_data *data)
d46a78b0 567{
c9e265e0 568 startup_pirq(data);
d46a78b0
JF
569}
570
c9e265e0 571static void disable_pirq(struct irq_data *data)
d46a78b0
JF
572{
573}
574
c9e265e0 575static void ack_pirq(struct irq_data *data)
d46a78b0 576{
c9e265e0 577 int evtchn = evtchn_from_irq(data->irq);
d46a78b0 578
aa673c1c 579 move_native_irq(data->irq);
d46a78b0
JF
580
581 if (VALID_EVTCHN(evtchn)) {
582 mask_evtchn(evtchn);
583 clear_evtchn(evtchn);
584 }
585}
586
d46a78b0
JF
587static int find_irq_by_gsi(unsigned gsi)
588{
589 int irq;
590
b21ddbf5 591 for (irq = 0; irq < nr_irqs; irq++) {
d46a78b0
JF
592 struct irq_info *info = info_for_irq(irq);
593
594 if (info == NULL || info->type != IRQT_PIRQ)
595 continue;
596
597 if (gsi_from_irq(irq) == gsi)
598 return irq;
599 }
600
601 return -1;
602}
603
f4d0635b 604int xen_allocate_pirq_gsi(unsigned gsi)
7a043f11 605{
f4d0635b 606 return gsi;
7a043f11
SS
607}
608
653378ac
IC
609/*
610 * Do not make any assumptions regarding the relationship between the
611 * IRQ number returned here and the Xen pirq argument.
7a043f11
SS
612 *
613 * Note: We don't assign an event channel until the irq actually started
614 * up. Return an existing irq if we've already got one for the gsi.
d46a78b0 615 */
f4d0635b
IC
616int xen_bind_pirq_gsi_to_irq(unsigned gsi,
617 unsigned pirq, int shareable, char *name)
d46a78b0 618{
a0e18116 619 int irq = -1;
d46a78b0
JF
620 struct physdev_irq irq_op;
621
622 spin_lock(&irq_mapping_update_lock);
623
e5fc7345 624 if ((pirq > nr_irqs) || (gsi > nr_irqs)) {
01557baf 625 printk(KERN_WARNING "xen_map_pirq_gsi: %s %s is incorrect!\n",
e5fc7345
SS
626 pirq > nr_irqs ? "pirq" :"",
627 gsi > nr_irqs ? "gsi" : "");
01557baf
SS
628 goto out;
629 }
630
d46a78b0
JF
631 irq = find_irq_by_gsi(gsi);
632 if (irq != -1) {
7a043f11 633 printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n",
d46a78b0
JF
634 irq, gsi);
635 goto out; /* XXX need refcount? */
636 }
637
c9df1ce5 638 irq = xen_allocate_irq_gsi(gsi);
d46a78b0
JF
639
640 set_irq_chip_and_handler_name(irq, &xen_pirq_chip,
1a60d05f 641 handle_level_irq, name);
d46a78b0
JF
642
643 irq_op.irq = irq;
b5401a96
AN
644 irq_op.vector = 0;
645
646 /* Only the privileged domain can do this. For non-priv, the pcifront
647 * driver provides a PCI bus that does the call to do exactly
648 * this in the priv domain. */
649 if (xen_initial_domain() &&
650 HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
c9df1ce5 651 xen_free_irq(irq);
d46a78b0
JF
652 irq = -ENOSPC;
653 goto out;
654 }
655
9158c358
IC
656 xen_irq_info_pirq_init(irq, 0, pirq, gsi, irq_op.vector,
657 shareable ? PIRQ_SHAREABLE : 0);
d46a78b0
JF
658
659out:
660 spin_unlock(&irq_mapping_update_lock);
661
662 return irq;
663}
664
f731e3ef 665#ifdef CONFIG_PCI_MSI
bf480d95 666int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc)
cbf6aa89 667{
5cad61a6 668 int rc;
cbf6aa89 669 struct physdev_get_free_pirq op_get_free_pirq;
cbf6aa89 670
bf480d95 671 op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI;
cbf6aa89 672 rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
cbf6aa89 673
5cad61a6
IC
674 WARN_ONCE(rc == -ENOSYS,
675 "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n");
676
677 return rc ? -1 : op_get_free_pirq.pirq;
cbf6aa89
IC
678}
679
bf480d95 680int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc,
ca1d8fe9 681 int pirq, int vector, const char *name)
809f9267 682{
bf480d95 683 int irq, ret;
4b41df7f 684
809f9267
SS
685 spin_lock(&irq_mapping_update_lock);
686
4b41df7f
IC
687 irq = xen_allocate_irq_dynamic();
688 if (irq == -1)
bb5d079a 689 goto out;
809f9267 690
4b41df7f 691 set_irq_chip_and_handler_name(irq, &xen_pirq_chip,
809f9267
SS
692 handle_level_irq, name);
693
9158c358 694 xen_irq_info_pirq_init(irq, 0, pirq, 0, vector, 0);
bf480d95
IC
695 ret = set_irq_msi(irq, msidesc);
696 if (ret < 0)
697 goto error_irq;
809f9267
SS
698out:
699 spin_unlock(&irq_mapping_update_lock);
4b41df7f 700 return irq;
bf480d95
IC
701error_irq:
702 spin_unlock(&irq_mapping_update_lock);
703 xen_free_irq(irq);
704 return -1;
809f9267 705}
f731e3ef
QH
706#endif
707
b5401a96
AN
708int xen_destroy_irq(int irq)
709{
710 struct irq_desc *desc;
38aa66fc
JF
711 struct physdev_unmap_pirq unmap_irq;
712 struct irq_info *info = info_for_irq(irq);
b5401a96
AN
713 int rc = -ENOENT;
714
715 spin_lock(&irq_mapping_update_lock);
716
717 desc = irq_to_desc(irq);
718 if (!desc)
719 goto out;
720
38aa66fc 721 if (xen_initial_domain()) {
12334715 722 unmap_irq.pirq = info->u.pirq.pirq;
38aa66fc
JF
723 unmap_irq.domid = DOMID_SELF;
724 rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
725 if (rc) {
726 printk(KERN_WARNING "unmap irq failed %d\n", rc);
727 goto out;
728 }
729 }
1aa0b51a
KRW
730 pirq_to_irq[info->u.pirq.pirq] = -1;
731
c9df1ce5 732 xen_free_irq(irq);
b5401a96
AN
733
734out:
735 spin_unlock(&irq_mapping_update_lock);
736 return rc;
737}
738
af42b8d1
SS
739int xen_irq_from_pirq(unsigned pirq)
740{
741 return pirq_to_irq[pirq];
742}
743
b536b4b9 744int bind_evtchn_to_irq(unsigned int evtchn)
e46cdb66
JF
745{
746 int irq;
747
748 spin_lock(&irq_mapping_update_lock);
749
750 irq = evtchn_to_irq[evtchn];
751
752 if (irq == -1) {
c9df1ce5 753 irq = xen_allocate_irq_dynamic();
e46cdb66 754
e46cdb66 755 set_irq_chip_and_handler_name(irq, &xen_dynamic_chip,
3588fe2e 756 handle_fasteoi_irq, "event");
e46cdb66 757
9158c358 758 xen_irq_info_evtchn_init(irq, evtchn);
e46cdb66
JF
759 }
760
e46cdb66
JF
761 spin_unlock(&irq_mapping_update_lock);
762
763 return irq;
764}
b536b4b9 765EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
e46cdb66 766
f87e4cac
JF
767static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
768{
769 struct evtchn_bind_ipi bind_ipi;
770 int evtchn, irq;
771
772 spin_lock(&irq_mapping_update_lock);
773
774 irq = per_cpu(ipi_to_irq, cpu)[ipi];
90af9514 775
f87e4cac 776 if (irq == -1) {
c9df1ce5 777 irq = xen_allocate_irq_dynamic();
f87e4cac
JF
778 if (irq < 0)
779 goto out;
780
aaca4964
JF
781 set_irq_chip_and_handler_name(irq, &xen_percpu_chip,
782 handle_percpu_irq, "ipi");
f87e4cac
JF
783
784 bind_ipi.vcpu = cpu;
785 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
786 &bind_ipi) != 0)
787 BUG();
788 evtchn = bind_ipi.port;
789
3d4cfa37 790 xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
f87e4cac
JF
791
792 bind_evtchn_to_cpu(evtchn, cpu);
793 }
794
f87e4cac
JF
795 out:
796 spin_unlock(&irq_mapping_update_lock);
797 return irq;
798}
799
800
4fe7d5a7 801int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
e46cdb66
JF
802{
803 struct evtchn_bind_virq bind_virq;
804 int evtchn, irq;
805
806 spin_lock(&irq_mapping_update_lock);
807
808 irq = per_cpu(virq_to_irq, cpu)[virq];
809
810 if (irq == -1) {
c9df1ce5 811 irq = xen_allocate_irq_dynamic();
a52521f1
JF
812
813 set_irq_chip_and_handler_name(irq, &xen_percpu_chip,
814 handle_percpu_irq, "virq");
815
e46cdb66
JF
816 bind_virq.virq = virq;
817 bind_virq.vcpu = cpu;
818 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
819 &bind_virq) != 0)
820 BUG();
821 evtchn = bind_virq.port;
822
3d4cfa37 823 xen_irq_info_virq_init(cpu, irq, evtchn, virq);
e46cdb66
JF
824
825 bind_evtchn_to_cpu(evtchn, cpu);
826 }
827
e46cdb66
JF
828 spin_unlock(&irq_mapping_update_lock);
829
830 return irq;
831}
832
833static void unbind_from_irq(unsigned int irq)
834{
835 struct evtchn_close close;
836 int evtchn = evtchn_from_irq(irq);
837
838 spin_lock(&irq_mapping_update_lock);
839
d77bbd4d 840 if (VALID_EVTCHN(evtchn)) {
e46cdb66
JF
841 close.port = evtchn;
842 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
843 BUG();
844
845 switch (type_from_irq(irq)) {
846 case IRQT_VIRQ:
847 per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 848 [virq_from_irq(irq)] = -1;
e46cdb66 849 break;
d68d82af
AN
850 case IRQT_IPI:
851 per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 852 [ipi_from_irq(irq)] = -1;
d68d82af 853 break;
e46cdb66
JF
854 default:
855 break;
856 }
857
858 /* Closed ports are implicitly re-bound to VCPU0. */
859 bind_evtchn_to_cpu(evtchn, 0);
860
861 evtchn_to_irq[evtchn] = -1;
fed5ea87
IC
862 }
863
9158c358 864 BUG_ON(irq_info[irq].type == IRQT_UNBOUND);
e46cdb66 865
9158c358 866 xen_free_irq(irq);
e46cdb66
JF
867
868 spin_unlock(&irq_mapping_update_lock);
869}
870
871int bind_evtchn_to_irqhandler(unsigned int evtchn,
7c239975 872 irq_handler_t handler,
e46cdb66
JF
873 unsigned long irqflags,
874 const char *devname, void *dev_id)
875{
876 unsigned int irq;
877 int retval;
878
879 irq = bind_evtchn_to_irq(evtchn);
880 retval = request_irq(irq, handler, irqflags, devname, dev_id);
881 if (retval != 0) {
882 unbind_from_irq(irq);
883 return retval;
884 }
885
886 return irq;
887}
888EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
889
890int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
7c239975 891 irq_handler_t handler,
e46cdb66
JF
892 unsigned long irqflags, const char *devname, void *dev_id)
893{
894 unsigned int irq;
895 int retval;
896
897 irq = bind_virq_to_irq(virq, cpu);
898 retval = request_irq(irq, handler, irqflags, devname, dev_id);
899 if (retval != 0) {
900 unbind_from_irq(irq);
901 return retval;
902 }
903
904 return irq;
905}
906EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
907
f87e4cac
JF
908int bind_ipi_to_irqhandler(enum ipi_vector ipi,
909 unsigned int cpu,
910 irq_handler_t handler,
911 unsigned long irqflags,
912 const char *devname,
913 void *dev_id)
914{
915 int irq, retval;
916
917 irq = bind_ipi_to_irq(ipi, cpu);
918 if (irq < 0)
919 return irq;
920
676dc3cf 921 irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME;
f87e4cac
JF
922 retval = request_irq(irq, handler, irqflags, devname, dev_id);
923 if (retval != 0) {
924 unbind_from_irq(irq);
925 return retval;
926 }
927
928 return irq;
929}
930
e46cdb66
JF
931void unbind_from_irqhandler(unsigned int irq, void *dev_id)
932{
933 free_irq(irq, dev_id);
934 unbind_from_irq(irq);
935}
936EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
937
f87e4cac
JF
938void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
939{
940 int irq = per_cpu(ipi_to_irq, cpu)[vector];
941 BUG_ON(irq < 0);
942 notify_remote_via_irq(irq);
943}
944
ee523ca1
JF
945irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
946{
947 struct shared_info *sh = HYPERVISOR_shared_info;
948 int cpu = smp_processor_id();
cb60d114 949 unsigned long *cpu_evtchn = per_cpu(cpu_evtchn_mask, cpu);
ee523ca1
JF
950 int i;
951 unsigned long flags;
952 static DEFINE_SPINLOCK(debug_lock);
cb52e6d9 953 struct vcpu_info *v;
ee523ca1
JF
954
955 spin_lock_irqsave(&debug_lock, flags);
956
cb52e6d9 957 printk("\nvcpu %d\n ", cpu);
ee523ca1
JF
958
959 for_each_online_cpu(i) {
cb52e6d9
IC
960 int pending;
961 v = per_cpu(xen_vcpu, i);
962 pending = (get_irq_regs() && i == cpu)
963 ? xen_irqs_disabled(get_irq_regs())
964 : v->evtchn_upcall_mask;
965 printk("%d: masked=%d pending=%d event_sel %0*lx\n ", i,
966 pending, v->evtchn_upcall_pending,
967 (int)(sizeof(v->evtchn_pending_sel)*2),
968 v->evtchn_pending_sel);
969 }
970 v = per_cpu(xen_vcpu, cpu);
971
972 printk("\npending:\n ");
973 for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
974 printk("%0*lx%s", (int)sizeof(sh->evtchn_pending[0])*2,
975 sh->evtchn_pending[i],
976 i % 8 == 0 ? "\n " : " ");
977 printk("\nglobal mask:\n ");
978 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
979 printk("%0*lx%s",
980 (int)(sizeof(sh->evtchn_mask[0])*2),
981 sh->evtchn_mask[i],
982 i % 8 == 0 ? "\n " : " ");
983
984 printk("\nglobally unmasked:\n ");
985 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
986 printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
987 sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
988 i % 8 == 0 ? "\n " : " ");
989
990 printk("\nlocal cpu%d mask:\n ", cpu);
991 for (i = (NR_EVENT_CHANNELS/BITS_PER_LONG)-1; i >= 0; i--)
992 printk("%0*lx%s", (int)(sizeof(cpu_evtchn[0])*2),
993 cpu_evtchn[i],
994 i % 8 == 0 ? "\n " : " ");
995
996 printk("\nlocally unmasked:\n ");
997 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
998 unsigned long pending = sh->evtchn_pending[i]
999 & ~sh->evtchn_mask[i]
1000 & cpu_evtchn[i];
1001 printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
1002 pending, i % 8 == 0 ? "\n " : " ");
ee523ca1 1003 }
ee523ca1
JF
1004
1005 printk("\npending list:\n");
cb52e6d9 1006 for (i = 0; i < NR_EVENT_CHANNELS; i++) {
ee523ca1 1007 if (sync_test_bit(i, sh->evtchn_pending)) {
cb52e6d9
IC
1008 int word_idx = i / BITS_PER_LONG;
1009 printk(" %d: event %d -> irq %d%s%s%s\n",
ced40d0f 1010 cpu_from_evtchn(i), i,
cb52e6d9
IC
1011 evtchn_to_irq[i],
1012 sync_test_bit(word_idx, &v->evtchn_pending_sel)
1013 ? "" : " l2-clear",
1014 !sync_test_bit(i, sh->evtchn_mask)
1015 ? "" : " globally-masked",
1016 sync_test_bit(i, cpu_evtchn)
1017 ? "" : " locally-masked");
ee523ca1
JF
1018 }
1019 }
1020
1021 spin_unlock_irqrestore(&debug_lock, flags);
1022
1023 return IRQ_HANDLED;
1024}
1025
245b2e70
TH
1026static DEFINE_PER_CPU(unsigned, xed_nesting_count);
1027
e46cdb66
JF
1028/*
1029 * Search the CPUs pending events bitmasks. For each one found, map
1030 * the event number to an irq, and feed it into do_IRQ() for
1031 * handling.
1032 *
1033 * Xen uses a two-level bitmap to speed searching. The first level is
1034 * a bitset of words which contain pending event bits. The second
1035 * level is a bitset of pending events themselves.
1036 */
38e20b07 1037static void __xen_evtchn_do_upcall(void)
e46cdb66
JF
1038{
1039 int cpu = get_cpu();
1040 struct shared_info *s = HYPERVISOR_shared_info;
780f36d8 1041 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
229664be 1042 unsigned count;
e46cdb66 1043
229664be
JF
1044 do {
1045 unsigned long pending_words;
e46cdb66 1046
229664be 1047 vcpu_info->evtchn_upcall_pending = 0;
e46cdb66 1048
b2e4ae69 1049 if (__this_cpu_inc_return(xed_nesting_count) - 1)
229664be 1050 goto out;
e46cdb66 1051
e849c3e9
IY
1052#ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */
1053 /* Clear master flag /before/ clearing selector flag. */
6673cf63 1054 wmb();
e849c3e9 1055#endif
229664be
JF
1056 pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0);
1057 while (pending_words != 0) {
1058 unsigned long pending_bits;
1059 int word_idx = __ffs(pending_words);
1060 pending_words &= ~(1UL << word_idx);
1061
1062 while ((pending_bits = active_evtchns(cpu, s, word_idx)) != 0) {
1063 int bit_idx = __ffs(pending_bits);
1064 int port = (word_idx * BITS_PER_LONG) + bit_idx;
1065 int irq = evtchn_to_irq[port];
ca4dbc66 1066 struct irq_desc *desc;
229664be 1067
3588fe2e
JF
1068 mask_evtchn(port);
1069 clear_evtchn(port);
1070
ca4dbc66
EB
1071 if (irq != -1) {
1072 desc = irq_to_desc(irq);
1073 if (desc)
1074 generic_handle_irq_desc(irq, desc);
1075 }
e46cdb66
JF
1076 }
1077 }
e46cdb66 1078
229664be
JF
1079 BUG_ON(!irqs_disabled());
1080
780f36d8
CL
1081 count = __this_cpu_read(xed_nesting_count);
1082 __this_cpu_write(xed_nesting_count, 0);
183d03cc 1083 } while (count != 1 || vcpu_info->evtchn_upcall_pending);
229664be
JF
1084
1085out:
38e20b07
SY
1086
1087 put_cpu();
1088}
1089
1090void xen_evtchn_do_upcall(struct pt_regs *regs)
1091{
1092 struct pt_regs *old_regs = set_irq_regs(regs);
1093
1094 exit_idle();
1095 irq_enter();
1096
1097 __xen_evtchn_do_upcall();
1098
3445a8fd
JF
1099 irq_exit();
1100 set_irq_regs(old_regs);
38e20b07 1101}
3445a8fd 1102
38e20b07
SY
1103void xen_hvm_evtchn_do_upcall(void)
1104{
1105 __xen_evtchn_do_upcall();
e46cdb66 1106}
183d03cc 1107EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
e46cdb66 1108
eb1e305f
JF
1109/* Rebind a new event channel to an existing irq. */
1110void rebind_evtchn_irq(int evtchn, int irq)
1111{
d77bbd4d
JF
1112 struct irq_info *info = info_for_irq(irq);
1113
eb1e305f
JF
1114 /* Make sure the irq is masked, since the new event channel
1115 will also be masked. */
1116 disable_irq(irq);
1117
1118 spin_lock(&irq_mapping_update_lock);
1119
1120 /* After resume the irq<->evtchn mappings are all cleared out */
1121 BUG_ON(evtchn_to_irq[evtchn] != -1);
1122 /* Expect irq to have been bound before,
d77bbd4d
JF
1123 so there should be a proper type */
1124 BUG_ON(info->type == IRQT_UNBOUND);
eb1e305f 1125
9158c358 1126 xen_irq_info_evtchn_init(irq, evtchn);
eb1e305f
JF
1127
1128 spin_unlock(&irq_mapping_update_lock);
1129
1130 /* new event channels are always bound to cpu 0 */
0de26520 1131 irq_set_affinity(irq, cpumask_of(0));
eb1e305f
JF
1132
1133 /* Unmask the event channel. */
1134 enable_irq(irq);
1135}
1136
e46cdb66 1137/* Rebind an evtchn so that it gets delivered to a specific cpu */
d5dedd45 1138static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
e46cdb66
JF
1139{
1140 struct evtchn_bind_vcpu bind_vcpu;
1141 int evtchn = evtchn_from_irq(irq);
1142
be49472f
IC
1143 if (!VALID_EVTCHN(evtchn))
1144 return -1;
1145
1146 /*
1147 * Events delivered via platform PCI interrupts are always
1148 * routed to vcpu 0 and hence cannot be rebound.
1149 */
1150 if (xen_hvm_domain() && !xen_have_vector_callback)
d5dedd45 1151 return -1;
e46cdb66
JF
1152
1153 /* Send future instances of this interrupt to other vcpu. */
1154 bind_vcpu.port = evtchn;
1155 bind_vcpu.vcpu = tcpu;
1156
1157 /*
1158 * If this fails, it usually just indicates that we're dealing with a
1159 * virq or IPI channel, which don't actually need to be rebound. Ignore
1160 * it, but don't do the xenlinux-level rebind in that case.
1161 */
1162 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
1163 bind_evtchn_to_cpu(evtchn, tcpu);
e46cdb66 1164
d5dedd45
YL
1165 return 0;
1166}
e46cdb66 1167
c9e265e0
TG
1168static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest,
1169 bool force)
e46cdb66 1170{
0de26520 1171 unsigned tcpu = cpumask_first(dest);
d5dedd45 1172
c9e265e0 1173 return rebind_irq_to_cpu(data->irq, tcpu);
e46cdb66
JF
1174}
1175
642e0c88
IY
1176int resend_irq_on_evtchn(unsigned int irq)
1177{
1178 int masked, evtchn = evtchn_from_irq(irq);
1179 struct shared_info *s = HYPERVISOR_shared_info;
1180
1181 if (!VALID_EVTCHN(evtchn))
1182 return 1;
1183
1184 masked = sync_test_and_set_bit(evtchn, s->evtchn_mask);
1185 sync_set_bit(evtchn, s->evtchn_pending);
1186 if (!masked)
1187 unmask_evtchn(evtchn);
1188
1189 return 1;
1190}
1191
c9e265e0 1192static void enable_dynirq(struct irq_data *data)
e46cdb66 1193{
c9e265e0 1194 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1195
1196 if (VALID_EVTCHN(evtchn))
1197 unmask_evtchn(evtchn);
1198}
1199
c9e265e0 1200static void disable_dynirq(struct irq_data *data)
e46cdb66 1201{
c9e265e0 1202 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1203
1204 if (VALID_EVTCHN(evtchn))
1205 mask_evtchn(evtchn);
1206}
1207
c9e265e0 1208static void ack_dynirq(struct irq_data *data)
e46cdb66 1209{
c9e265e0 1210 int evtchn = evtchn_from_irq(data->irq);
e46cdb66 1211
c9e265e0 1212 move_masked_irq(data->irq);
e46cdb66
JF
1213
1214 if (VALID_EVTCHN(evtchn))
3588fe2e 1215 unmask_evtchn(evtchn);
e46cdb66
JF
1216}
1217
c9e265e0 1218static int retrigger_dynirq(struct irq_data *data)
e46cdb66 1219{
c9e265e0 1220 int evtchn = evtchn_from_irq(data->irq);
ee8fa1c6 1221 struct shared_info *sh = HYPERVISOR_shared_info;
e46cdb66
JF
1222 int ret = 0;
1223
1224 if (VALID_EVTCHN(evtchn)) {
ee8fa1c6
JF
1225 int masked;
1226
1227 masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask);
1228 sync_set_bit(evtchn, sh->evtchn_pending);
1229 if (!masked)
1230 unmask_evtchn(evtchn);
e46cdb66
JF
1231 ret = 1;
1232 }
1233
1234 return ret;
1235}
1236
0a85226f 1237static void restore_pirqs(void)
9a069c33
SS
1238{
1239 int pirq, rc, irq, gsi;
1240 struct physdev_map_pirq map_irq;
1241
1242 for (pirq = 0; pirq < nr_irqs; pirq++) {
1243 irq = pirq_to_irq[pirq];
1244 if (irq == -1)
1245 continue;
1246
1247 /* save/restore of PT devices doesn't work, so at this point the
1248 * only devices present are GSI based emulated devices */
1249 gsi = gsi_from_irq(irq);
1250 if (!gsi)
1251 continue;
1252
1253 map_irq.domid = DOMID_SELF;
1254 map_irq.type = MAP_PIRQ_TYPE_GSI;
1255 map_irq.index = gsi;
1256 map_irq.pirq = pirq;
1257
1258 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
1259 if (rc) {
1260 printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
1261 gsi, irq, pirq, rc);
9158c358 1262 xen_free_irq(irq);
9a069c33
SS
1263 pirq_to_irq[pirq] = -1;
1264 continue;
1265 }
1266
1267 printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
1268
c9e265e0 1269 __startup_pirq(irq);
9a069c33
SS
1270 }
1271}
1272
0e91398f
JF
1273static void restore_cpu_virqs(unsigned int cpu)
1274{
1275 struct evtchn_bind_virq bind_virq;
1276 int virq, irq, evtchn;
1277
1278 for (virq = 0; virq < NR_VIRQS; virq++) {
1279 if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
1280 continue;
1281
ced40d0f 1282 BUG_ON(virq_from_irq(irq) != virq);
0e91398f
JF
1283
1284 /* Get a new binding from Xen. */
1285 bind_virq.virq = virq;
1286 bind_virq.vcpu = cpu;
1287 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
1288 &bind_virq) != 0)
1289 BUG();
1290 evtchn = bind_virq.port;
1291
1292 /* Record the new mapping. */
3d4cfa37 1293 xen_irq_info_virq_init(cpu, irq, evtchn, virq);
0e91398f 1294 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1295 }
1296}
1297
1298static void restore_cpu_ipis(unsigned int cpu)
1299{
1300 struct evtchn_bind_ipi bind_ipi;
1301 int ipi, irq, evtchn;
1302
1303 for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
1304 if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
1305 continue;
1306
ced40d0f 1307 BUG_ON(ipi_from_irq(irq) != ipi);
0e91398f
JF
1308
1309 /* Get a new binding from Xen. */
1310 bind_ipi.vcpu = cpu;
1311 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
1312 &bind_ipi) != 0)
1313 BUG();
1314 evtchn = bind_ipi.port;
1315
1316 /* Record the new mapping. */
3d4cfa37 1317 xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
0e91398f 1318 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1319 }
1320}
1321
2d9e1e2f
JF
1322/* Clear an irq's pending state, in preparation for polling on it */
1323void xen_clear_irq_pending(int irq)
1324{
1325 int evtchn = evtchn_from_irq(irq);
1326
1327 if (VALID_EVTCHN(evtchn))
1328 clear_evtchn(evtchn);
1329}
d9a8814f 1330EXPORT_SYMBOL(xen_clear_irq_pending);
168d2f46
JF
1331void xen_set_irq_pending(int irq)
1332{
1333 int evtchn = evtchn_from_irq(irq);
1334
1335 if (VALID_EVTCHN(evtchn))
1336 set_evtchn(evtchn);
1337}
1338
1339bool xen_test_irq_pending(int irq)
1340{
1341 int evtchn = evtchn_from_irq(irq);
1342 bool ret = false;
1343
1344 if (VALID_EVTCHN(evtchn))
1345 ret = test_evtchn(evtchn);
1346
1347 return ret;
1348}
1349
d9a8814f
KRW
1350/* Poll waiting for an irq to become pending with timeout. In the usual case,
1351 * the irq will be disabled so it won't deliver an interrupt. */
1352void xen_poll_irq_timeout(int irq, u64 timeout)
2d9e1e2f
JF
1353{
1354 evtchn_port_t evtchn = evtchn_from_irq(irq);
1355
1356 if (VALID_EVTCHN(evtchn)) {
1357 struct sched_poll poll;
1358
1359 poll.nr_ports = 1;
d9a8814f 1360 poll.timeout = timeout;
ff3c5362 1361 set_xen_guest_handle(poll.ports, &evtchn);
2d9e1e2f
JF
1362
1363 if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
1364 BUG();
1365 }
1366}
d9a8814f
KRW
1367EXPORT_SYMBOL(xen_poll_irq_timeout);
1368/* Poll waiting for an irq to become pending. In the usual case, the
1369 * irq will be disabled so it won't deliver an interrupt. */
1370void xen_poll_irq(int irq)
1371{
1372 xen_poll_irq_timeout(irq, 0 /* no timeout */);
1373}
2d9e1e2f 1374
0e91398f
JF
1375void xen_irq_resume(void)
1376{
1377 unsigned int cpu, irq, evtchn;
1378
1379 init_evtchn_cpu_bindings();
1380
1381 /* New event-channel space is not 'live' yet. */
1382 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1383 mask_evtchn(evtchn);
1384
1385 /* No IRQ <-> event-channel mappings. */
0b8f1efa 1386 for (irq = 0; irq < nr_irqs; irq++)
0e91398f
JF
1387 irq_info[irq].evtchn = 0; /* zap event-channel binding */
1388
1389 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1390 evtchn_to_irq[evtchn] = -1;
1391
1392 for_each_possible_cpu(cpu) {
1393 restore_cpu_virqs(cpu);
1394 restore_cpu_ipis(cpu);
1395 }
6903591f 1396
0a85226f 1397 restore_pirqs();
0e91398f
JF
1398}
1399
e46cdb66 1400static struct irq_chip xen_dynamic_chip __read_mostly = {
c9e265e0 1401 .name = "xen-dyn",
54a353a0 1402
c9e265e0
TG
1403 .irq_disable = disable_dynirq,
1404 .irq_mask = disable_dynirq,
1405 .irq_unmask = enable_dynirq,
54a353a0 1406
c9e265e0
TG
1407 .irq_eoi = ack_dynirq,
1408 .irq_set_affinity = set_affinity_irq,
1409 .irq_retrigger = retrigger_dynirq,
e46cdb66
JF
1410};
1411
d46a78b0 1412static struct irq_chip xen_pirq_chip __read_mostly = {
c9e265e0 1413 .name = "xen-pirq",
d46a78b0 1414
c9e265e0
TG
1415 .irq_startup = startup_pirq,
1416 .irq_shutdown = shutdown_pirq,
d46a78b0 1417
c9e265e0
TG
1418 .irq_enable = enable_pirq,
1419 .irq_unmask = enable_pirq,
d46a78b0 1420
c9e265e0
TG
1421 .irq_disable = disable_pirq,
1422 .irq_mask = disable_pirq,
d46a78b0 1423
c9e265e0 1424 .irq_ack = ack_pirq,
d46a78b0 1425
c9e265e0 1426 .irq_set_affinity = set_affinity_irq,
d46a78b0 1427
c9e265e0 1428 .irq_retrigger = retrigger_dynirq,
d46a78b0
JF
1429};
1430
aaca4964 1431static struct irq_chip xen_percpu_chip __read_mostly = {
c9e265e0 1432 .name = "xen-percpu",
aaca4964 1433
c9e265e0
TG
1434 .irq_disable = disable_dynirq,
1435 .irq_mask = disable_dynirq,
1436 .irq_unmask = enable_dynirq,
aaca4964 1437
c9e265e0 1438 .irq_ack = ack_dynirq,
aaca4964
JF
1439};
1440
38e20b07
SY
1441int xen_set_callback_via(uint64_t via)
1442{
1443 struct xen_hvm_param a;
1444 a.domid = DOMID_SELF;
1445 a.index = HVM_PARAM_CALLBACK_IRQ;
1446 a.value = via;
1447 return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
1448}
1449EXPORT_SYMBOL_GPL(xen_set_callback_via);
1450
ca65f9fc 1451#ifdef CONFIG_XEN_PVHVM
38e20b07
SY
1452/* Vector callbacks are better than PCI interrupts to receive event
1453 * channel notifications because we can receive vector callbacks on any
1454 * vcpu and we don't need PCI support or APIC interactions. */
1455void xen_callback_vector(void)
1456{
1457 int rc;
1458 uint64_t callback_via;
1459 if (xen_have_vector_callback) {
1460 callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK);
1461 rc = xen_set_callback_via(callback_via);
1462 if (rc) {
1463 printk(KERN_ERR "Request for Xen HVM callback vector"
1464 " failed.\n");
1465 xen_have_vector_callback = 0;
1466 return;
1467 }
1468 printk(KERN_INFO "Xen HVM callback vector for event delivery is "
1469 "enabled\n");
1470 /* in the restore case the vector has already been allocated */
1471 if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors))
1472 alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector);
1473 }
1474}
ca65f9fc
SS
1475#else
1476void xen_callback_vector(void) {}
1477#endif
38e20b07 1478
e46cdb66
JF
1479void __init xen_init_IRQ(void)
1480{
e5fc7345 1481 int i;
c7a3589e 1482
b21ddbf5
JF
1483 irq_info = kcalloc(nr_irqs, sizeof(*irq_info), GFP_KERNEL);
1484
e5fc7345
SS
1485 /* We are using nr_irqs as the maximum number of pirq available but
1486 * that number is actually chosen by Xen and we don't know exactly
1487 * what it is. Be careful choosing high pirq numbers. */
1488 pirq_to_irq = kcalloc(nr_irqs, sizeof(*pirq_to_irq), GFP_KERNEL);
1489 for (i = 0; i < nr_irqs; i++)
7a043f11
SS
1490 pirq_to_irq[i] = -1;
1491
b21ddbf5
JF
1492 evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
1493 GFP_KERNEL);
1494 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1495 evtchn_to_irq[i] = -1;
e46cdb66
JF
1496
1497 init_evtchn_cpu_bindings();
1498
1499 /* No event channels are 'live' right now. */
1500 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1501 mask_evtchn(i);
1502
38e20b07
SY
1503 if (xen_hvm_domain()) {
1504 xen_callback_vector();
1505 native_init_IRQ();
3942b740
SS
1506 /* pci_xen_hvm_init must be called after native_init_IRQ so that
1507 * __acpi_register_gsi can point at the right function */
1508 pci_xen_hvm_init();
38e20b07
SY
1509 } else {
1510 irq_ctx_init(smp_processor_id());
38aa66fc
JF
1511 if (xen_initial_domain())
1512 xen_setup_pirqs();
38e20b07 1513 }
e46cdb66 1514}
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